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annotate packages/hal/mips/ref4955/current/src/pc87338.c @ 151:25e238959bae

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Merge from eCos master repository on 2001-02-12-23:44:24-GMT
author jlarmour
date Tue, 13 Feb 2001 01:23:16 +0000
parents d2f49caf9e38
children e0c0827131d1
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1 #ifndef CYGONCE_HAL_PC_SER_H
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2 #define CYGONCE_HAL_PC_SER_H
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3 //=============================================================================
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4 //
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5 // pc87338.c
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6 //
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7 // Simple driver for the serial controllers in the PC87338 SuperIO chip
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8 //
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9 //=============================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.1 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://www.redhat.com/
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17 //
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18 // Software distributed under the License is distributed on an "AS IS"
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //=============================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): jskov
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37 // Contributors:jskov
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38 // Date: 2000-06-20
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39 // Description: Simple driver for the PC87338 serial controllers
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40 //
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41 //####DESCRIPTIONEND####
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42 //
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43 //=============================================================================
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44
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45 #include <pkgconf/hal.h>
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46
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47 #include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
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48 #include <cyg/hal/hal_io.h> // IO macros
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49 #include <cyg/hal/hal_if.h> // interface API
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50 #include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
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51 #include <cyg/hal/hal_misc.h> // Helper functions
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52 #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
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53
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54 //-----------------------------------------------------------------------------
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55 // Controller definitions.
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56
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57 //-----------------------------------------------------------------------------
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58 // There are two serial ports.
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59 #define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1
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60 #define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2
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61
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62 //-----------------------------------------------------------------------------
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63 // Serial registers (shared by all banks)
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64 #define CYG_DEVICE_BSR (0x03)
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65 #define CYG_DEVICE_LCR (0x03)
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66
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67 #define CYG_DEVICE_BSR_BANK0 0x00
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68 #define CYG_DEVICE_BSR_BANK2 0xe0
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69
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70 #define CYG_DEVICE_LCR_LEN_5BIT 0x00
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71 #define CYG_DEVICE_LCR_LEN_6BIT 0x01
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72 #define CYG_DEVICE_LCR_LEN_7BIT 0x02
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73 #define CYG_DEVICE_LCR_LEN_8BIT 0x03
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74 #define CYG_DEVICE_LCR_STOP_1 0x00
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75 #define CYG_DEVICE_LCR_STOP_2 0x04
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76 #define CYG_DEVICE_LCR_PARITY_NONE 0x00
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77 #define CYG_DEVICE_LCR_PARITY_ODD 0x08
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78 #define CYG_DEVICE_LCR_PARITY_EVEN 0x18
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79 #define CYG_DEVICE_LCR_PARITY_LOGIC1 0x28
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80 #define CYG_DEVICE_LCR_PARITY_LOGIC0 0x38
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81 #define CYG_DEVICE_LCR_SBRK 0x40
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82
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83 // Bank 0 (control/status)
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84 #define CYG_DEVICE_BK0_TXD (0x00)
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85 #define CYG_DEVICE_BK0_RXD (0x00)
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86 #define CYG_DEVICE_BK0_IER (0x01)
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87 #define CYG_DEVICE_BK0_EIR (0x02)
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88 #define CYG_DEVICE_BK0_FCR (0x02)
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89 #define CYG_DEVICE_BK0_MCR (0x04)
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90 #define CYG_DEVICE_BK0_LSR (0x05)
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91 #define CYG_DEVICE_BK0_MSR (0x06)
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92 #define CYG_DEVICE_BK0_SPR (0x07)
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93 #define CYG_DEVICE_BK0_ASCR (0x07)
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94
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95 #define CYG_DEVICE_BK0_LSR_RXDA 0x01
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96 #define CYG_DEVICE_BK0_LSR_OE 0x02
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97 #define CYG_DEVICE_BK0_LSR_PE 0x04
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98 #define CYG_DEVICE_BK0_LSR_FE 0x08
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99 #define CYG_DEVICE_BK0_LSR_BRK 0x10
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100 #define CYG_DEVICE_BK0_LSR_TXRDY 0x20
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101 #define CYG_DEVICE_BK0_LSR_TXEMP 0x40
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102 #define CYG_DEVICE_BK0_LSR_ER_INF 0x80
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103
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104 #define CYG_DEVICE_BK0_IER_TMR_IE 0x80
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105 #define CYG_DEVICE_BK0_IER_SFIF_IE 0x40
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106 #define CYG_DEVICE_BK0_IER_TXEMP_IE 0x20
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107 #define CYG_DEVICE_BK0_IER_DMA_IE 0x10
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108 #define CYG_DEVICE_BK0_IER_MS_IE 0x08
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109 #define CYG_DEVICE_BK0_IER_LS_IE 0x04
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110 #define CYG_DEVICE_BK0_IER_TXLDL_IE 0x02
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111 #define CYG_DEVICE_BK0_IER_RXHDL_IE 0x01
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112
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113 #define CYG_DEVICE_BK0_EIR_FEN1 0x80
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114 #define CYG_DEVICE_BK0_EIR_FEN0 0x40
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115 #define CYG_DEVICE_BK0_EIR_RXFT 0x08
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116 #define CYG_DEVICE_BK0_EIR_IPR1 0x04
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117 #define CYG_DEVICE_BK0_EIR_IPR0 0x02
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118 #define CYG_DEVICE_BK0_EIR_IPF 0x01
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119
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120 #define CYG_DEVICE_BK0_EIR_mask 0x07
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121 #define CYG_DEVICE_BK0_EIR_IRQ_ERR 0x06
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122 #define CYG_DEVICE_BK0_EIR_IRQ_RX 0x04
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123 #define CYG_DEVICE_BK0_EIR_IRQ_TX 0x02
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124
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125 #define CYG_DEVICE_BK0_MCR_ISEN 0x08 // interrupt signal enable
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126
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127
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128 // Bank 2 (baud generator)
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129 #define CYG_DEVICE_BK2_BGDL (0x00)
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130 #define CYG_DEVICE_BK2_BGDH (0x01)
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131 #define CYG_DEVICE_BK2_EXCR1 (0x02)
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132 #define CYG_DEVICE_BK2_EXCR2 (0x04)
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133 #define CYG_DEVICE_BK2_TXFLV (0x06)
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134 #define CYG_DEVICE_BK2_RXFLV (0x07)
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135
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136
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137 //-----------------------------------------------------------------------------
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138 typedef struct {
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139 cyg_uint8* base;
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140 cyg_int32 msec_timeout;
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141 int isr_vector;
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142 } channel_data_t;
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143
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144 //-----------------------------------------------------------------------------
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145 // The minimal init, get and put functions. All by polling.
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146
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147 void
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148 cyg_hal_plf_serial_init_channel(void* __ch_data)
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149 {
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150 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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151 cyg_uint8 lcr;
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152
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153 HAL_WRITE_UINT8(base+CYG_DEVICE_BSR, CYG_DEVICE_BSR_BANK0);
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154 HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_IER, 0);
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155 HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_MCR, CYG_DEVICE_BK0_MCR_ISEN);
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156
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157 // Disable FIFOs
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158 HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_FCR, 0);
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159
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160 // 8-1-no parity.
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161 HAL_WRITE_UINT8(base+CYG_DEVICE_LCR,
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162 CYG_DEVICE_LCR_LEN_8BIT | CYG_DEVICE_LCR_STOP_1 | CYG_DEVICE_LCR_PARITY_NONE);
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163
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164 // Set speed to 38400 (switch bank, remember old LCR setting)
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165 HAL_READ_UINT8(base+CYG_DEVICE_LCR, lcr);
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166 HAL_WRITE_UINT8(base+CYG_DEVICE_BSR, CYG_DEVICE_BSR_BANK2);
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167 HAL_WRITE_UINT8(base+CYG_DEVICE_BK2_BGDL, 3);
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168 HAL_WRITE_UINT8(base+CYG_DEVICE_BK2_BGDH, 0);
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169 HAL_WRITE_UINT8(base+CYG_DEVICE_LCR, lcr);
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170 }
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171
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172 void
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173 cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
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174 {
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175 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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176 cyg_uint8 lsr;
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177 CYGARC_HAL_SAVE_GP();
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178
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179 do {
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180 HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
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181 } while ((lsr & CYG_DEVICE_BK0_LSR_TXRDY) == 0);
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182
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183 HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_TXD, __ch);
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184
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185 // Hang around until the character has been safely sent.
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186 do {
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187 HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
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188 } while ((lsr & CYG_DEVICE_BK0_LSR_TXRDY) == 0);
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189
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190 CYGARC_HAL_RESTORE_GP();
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191 }
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192
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193 static cyg_bool
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194 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
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195 {
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196 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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197 cyg_uint8 lsr;
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198
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199 HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
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200 if ((lsr & CYG_DEVICE_BK0_LSR_RXDA) == 0)
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201 return false;
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202
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203 HAL_READ_UINT8 (base+CYG_DEVICE_BK0_RXD, *ch);
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204
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205 return true;
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206 }
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207
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208 cyg_uint8
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209 cyg_hal_plf_serial_getc(void* __ch_data)
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210 {
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211 cyg_uint8 ch;
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212 CYGARC_HAL_SAVE_GP();
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213
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214 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
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215
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216 CYGARC_HAL_RESTORE_GP();
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217 return ch;
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218 }
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219
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220 static const channel_data_t channels[2] = {
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221 { (cyg_uint8*)CYG_DEVICE_SERIAL_SCC1, 1000, CYGNUM_HAL_INTERRUPT_DEBUG_UART},
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222 { (cyg_uint8*)CYG_DEVICE_SERIAL_SCC2, 1000, CYGNUM_HAL_INTERRUPT_USER_UART}
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223 };
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224
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225 static void
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226 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
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227 cyg_uint32 __len)
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228 {
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229 CYGARC_HAL_SAVE_GP();
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230
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231 while(__len-- > 0)
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232 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
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233
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234 CYGARC_HAL_RESTORE_GP();
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235 }
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236
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237 static void
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238 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
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239 {
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240 CYGARC_HAL_SAVE_GP();
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241
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242 while(__len-- > 0)
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243 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
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244
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245 CYGARC_HAL_RESTORE_GP();
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246 }
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247
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248
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249 cyg_bool
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250 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
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251 {
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252 int delay_count;
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253 channel_data_t* chan = (channel_data_t*)__ch_data;
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254 cyg_bool res;
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255 CYGARC_HAL_SAVE_GP();
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256
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257 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
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258
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259 for(;;) {
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260 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
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261 if (res || 0 == delay_count--)
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262 break;
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263
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264 CYGACC_CALL_IF_DELAY_US(100);
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265 }
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266
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267 CYGARC_HAL_RESTORE_GP();
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268 return res;
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269 }
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270
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271 static int
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272 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
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273 {
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274 static int irq_state = 0;
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275 channel_data_t* chan = (channel_data_t*)__ch_data;
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276 cyg_uint8 ier;
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277 int ret = 0;
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278 CYGARC_HAL_SAVE_GP();
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279
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280 switch (__func) {
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281 case __COMMCTL_IRQ_ENABLE:
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282 irq_state = 1;
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283
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284 HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
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285 ier |= CYG_DEVICE_BK0_IER_RXHDL_IE;
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286 HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
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287
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288 HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
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289 HAL_INTERRUPT_UNMASK(chan->isr_vector);
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290 break;
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291 case __COMMCTL_IRQ_DISABLE:
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292 ret = irq_state;
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293 irq_state = 0;
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294
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295 HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
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296 ier &= ~CYG_DEVICE_BK0_IER_RXHDL_IE;
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297 HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
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298
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299 HAL_INTERRUPT_MASK(chan->isr_vector);
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300 break;
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301 case __COMMCTL_DBG_ISR_VECTOR:
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302 ret = chan->isr_vector;
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303 break;
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304 case __COMMCTL_SET_TIMEOUT:
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305 {
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306 va_list ap;
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307
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308 va_start(ap, __func);
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309
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310 ret = chan->msec_timeout;
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311 chan->msec_timeout = va_arg(ap, cyg_uint32);
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312
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313 va_end(ap);
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314 }
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315 default:
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316 break;
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317 }
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318 CYGARC_HAL_RESTORE_GP();
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319 return ret;
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320 }
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321
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322 static int
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323 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
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324 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
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325 {
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326 int res = 0;
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327 cyg_uint8 eir, c;
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328 channel_data_t* chan = (channel_data_t*)__ch_data;
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329 CYGARC_HAL_SAVE_GP();
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330
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331 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
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332
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333 HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_EIR, eir);
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334
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335 *__ctrlc = 0;
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336 if( (eir & CYG_DEVICE_BK0_EIR_mask) == CYG_DEVICE_BK0_EIR_IRQ_RX ) {
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337
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338 HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_RXD, c);
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339
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340 if( cyg_hal_is_break( &c , 1 ) )
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341 *__ctrlc = 1;
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342
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343 res = CYG_ISR_HANDLED;
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344 }
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345
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346 CYGARC_HAL_RESTORE_GP();
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347 return res;
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348 }
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349
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350 static void
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351 cyg_hal_plf_serial_init(void)
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352 {
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353 hal_virtual_comm_table_t* comm;
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354 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
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355
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356 // Disable interrupts.
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357 HAL_INTERRUPT_MASK(channels[0].isr_vector);
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358 HAL_INTERRUPT_MASK(channels[1].isr_vector);
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359
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360 // Init channels
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361 cyg_hal_plf_serial_init_channel((void*)&channels[0]);
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362 cyg_hal_plf_serial_init_channel((void*)&channels[1]);
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363
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364 // Setup procs in the vector table
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365
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366 // Set channel 0
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367 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
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368 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
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369 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
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370 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
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371 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
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372 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
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373 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
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374 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
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375 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
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376 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
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377
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378 // Set channel 1
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379 CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
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380 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
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381 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
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382 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
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383 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
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384 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
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385 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
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386 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
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387 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
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388 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
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389
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390 // Restore original console
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391 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
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392 }
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393
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394 void
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395 cyg_hal_plf_comms_init(void)
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396 {
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397 static int initialized = 0;
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398
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399 if (initialized)
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400 return;
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401
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402 initialized = 1;
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403
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404 cyg_hal_plf_serial_init();
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405 }
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406
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407 //-----------------------------------------------------------------------------
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408 // end of pc87338.c
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409 #endif // CYGONCE_HAL_PC_SER_INL