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annotate packages/hal/powerpc/arch/current/src/vectors.S @ 76:435cced73e2f ecos-v1_3_1-release
eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
| author | jlarmour |
|---|---|
| date | Tue, 28 Mar 2000 14:10:45 +0000 |
| parents | da3908c9cd10 |
| children | 6736c52df507 |
| rev | line source |
|---|---|
| 2 | 1 ##========================================================================== |
| 0 | 2 ## |
| 3 ## vectors.S | |
| 4 ## | |
| 5 ## PowerPC exception vectors | |
| 6 ## | |
| 2 | 7 ##========================================================================== |
| 0 | 8 #####COPYRIGHTBEGIN#### |
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9 # |
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10 # ------------------------------------------- |
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11 # The contents of this file are subject to the Red Hat eCos Public License |
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12 # Version 1.1 (the "License"); you may not use this file except in |
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13 # compliance with the License. You may obtain a copy of the License at |
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14 # http://www.redhat.com/ |
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15 # |
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16 # Software distributed under the License is distributed on an "AS IS" |
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 # License for the specific language governing rights and limitations under |
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19 # the License. |
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20 # |
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21 # The Original Code is eCos - Embedded Configurable Operating System, |
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22 # released September 30, 1998. |
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23 # |
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24 # The Initial Developer of the Original Code is Red Hat. |
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25 # Portions created by Red Hat are |
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26 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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27 # All Rights Reserved. |
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28 # ------------------------------------------- |
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29 # |
| 0 | 30 #####COPYRIGHTEND#### |
| 2 | 31 ##========================================================================== |
| 0 | 32 #######DESCRIPTIONBEGIN#### |
| 33 ## | |
| 2 | 34 ## Author(s): nickg, jskov |
| 35 ## Contributors: nickg, jskov | |
| 36 ## Date: 1999-02-20 | |
| 37 ## Purpose: PowerPC exception vectors | |
| 38 ## Description: This file defines the code placed into the exception | |
| 39 ## vectors. It also contains the first level default VSRs | |
| 40 ## that save and restore state for both exceptions and | |
| 41 ## interrupts. | |
| 0 | 42 ## |
| 43 ######DESCRIPTIONEND#### | |
| 44 ## | |
| 2 | 45 ##========================================================================== |
| 0 | 46 |
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47 #=========================================================================== |
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48 # |
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49 # The PowerPC exception handling has changed as of version 1.3.1. |
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50 # The primary motivation for rewriting the code was to bring it more |
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51 # in line with the other HALs, in particular to allow a RAM application |
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52 # to cleanly take over only a subset of vectors from a running ROM |
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53 # monitor. |
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54 # |
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55 # GDB stubs (and CygMon, should it be ported to PPC) copies |
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56 # exception vector entry handler code to address 0. These vector entry |
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57 # handlers (defined by the exception_vector macro below) compute |
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58 # a vector index into the hal_vsr_table, fetch the pointer, and |
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59 # jump to the HAL vector service routine (VSR). |
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60 # |
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61 # The hal_vsr_table is located immediately after the vector |
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62 # handlers (at address 0x3000), allowing RAM applications to |
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63 # change VSRs as necessary, while still keeping desired ROM |
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64 # monitor functionality available for debugging. |
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65 # |
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66 # ROM applications can still be configured to leave the vector entry |
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67 # handlers at 0xff000000, but there is at the moment no |
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68 # provision for reclaiming the reserved vector space in RAM to |
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69 # application usage. |
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70 # |
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71 # RAM applications can also be configured to provide exception |
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72 # handlers which are copied to address 0 on startup, thus taking |
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73 # full control of the target. |
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74 # |
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75 # |
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76 # Default configuration is for RAM applications to rely on an |
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77 # existing ROM monitor to provide debugging functionality, and |
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78 # for ROM applications to copy vectors to address 0. |
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79 # |
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80 # |
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81 # Unfortunately the new exception scheme is not compatible with the |
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82 # old scheme. Stubs and applications must be compiled using the same |
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83 # scheme (i.e., old binaries will not run with new stubs, and new |
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84 # binaries will not run with old stubs). |
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85 # |
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86 #=========================================================================== |
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87 |
| 0 | 88 #include <pkgconf/hal.h> |
| 89 | |
| 90 #ifdef CYGPKG_KERNEL | |
| 91 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT | |
| 92 #endif | |
| 2 | 93 |
| 94 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS | |
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95 #include <cyg/hal/ppc_regs.h> |
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96 |
| 2 | 97 #=========================================================================== |
| 0 | 98 |
| 99 .file "vectors.S" | |
| 100 | |
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101 .extern hal_interrupt_data |
| 0 | 102 .extern hal_interrupt_handlers |
| 103 .extern hal_interrupt_objects | |
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104 .extern hal_vsr_table |
| 0 | 105 |
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106 .extern cyg_hal_invoke_constructors |
| 0 | 107 .extern cyg_instrument |
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108 .extern cyg_start |
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109 .extern hal_IRQ_init |
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110 .extern hal_MMU_init |
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111 .extern hal_enable_caches |
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112 .extern hal_hardware_init |
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113 .extern initialize_stub |
| 0 | 114 |
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115 .extern __bss_start |
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116 .extern __bss_end |
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117 .extern __sbss_start |
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118 .extern __sbss_end |
| 0 | 119 |
| 2 | 120 #=========================================================================== |
| 0 | 121 # MSR initialization value |
| 122 # zero all bits except: | |
| 123 # FP = floating point available | |
| 124 # ME = machine check enabled | |
| 125 # IP = vectors at 0xFFFxxxxx (ROM startup only) | |
| 2 | 126 # IR = instruction address translation |
| 127 # DR = data address translation | |
| 0 | 128 # RI = recoverable interrupt |
| 129 | |
| 2 | 130 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_IR | MSR_DR | MSR_RI) |
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131 #if defined(CYG_HAL_STARTUP_ROM) |
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132 # ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS |
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133 # define CYG_MSR CYG_MSR_COMMON |
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134 # else |
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135 # define CYG_MSR (CYG_MSR_COMMON | MSR_IP) |
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136 # endif |
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137 #elif defined(CYG_HAL_STARTUP_RAM) |
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138 # define CYG_MSR CYG_MSR_COMMON |
| 0 | 139 #endif |
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140 |
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141 #ifdef CYGPKG_HAL_POWERPC_SIM |
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142 # When building for SIM, don~t enable MMU -- it~s not needed since caches |
| 2 | 143 # are disabled, and there is a runtime simulation overhead. |
| 144 #undef CYG_MSR | |
| 145 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR | MSR_DR)) | |
| 0 | 146 #endif |
| 147 | |
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148 # Include variant macros after MSR definition. |
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149 #include <cyg/hal/arch.inc> |
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150 #include <cyg/hal/ppc_offsets.inc> |
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151 |
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152 |
| 2 | 153 #=========================================================================== |
| 0 | 154 # If the following option is enabled, we only save registers up to R12. |
| 155 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do | |
| 156 # not need to save them when calling C functions. | |
| 157 | |
| 158 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT | |
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159 # define MAX_SAVE_REG 12 |
| 0 | 160 #else |
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161 # define MAX_SAVE_REG 31 |
| 0 | 162 #endif |
| 163 | |
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164 |
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165 #if defined(CYG_HAL_STARTUP_ROM) || \ |
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166 defined(CYGPKG_HAL_POWERPC_SIM) || \ |
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167 defined(CYGSEM_HAL_POWERPC_COPY_VECTORS) |
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168 |
| 2 | 169 #=========================================================================== |
| 0 | 170 # Start by defining the exceptions vectors that must be placed at |
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171 # locations 0xFFF00000 or 0x00000000. The following code will normally |
| 0 | 172 # be located at 0xFFF00000 in the ROM. It may optionally be copied out |
| 173 # to 0x00000000 if we want to use the RAM vectors. For this reason this code | |
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174 # MUST BE POSITION INDEPENDENT. |
| 0 | 175 |
| 176 .section ".vectors","ax" | |
| 177 | |
| 2 | 178 #--------------------------------------------------------------------------- |
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179 # Macros for generating an exception vector service routine |
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180 |
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181 # Reset vector macro |
| 0 | 182 |
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183 .macro reset_vector name |
| 0 | 184 .p2align 8 |
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185 .globl __exception_\name |
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186 __exception_\name: |
| 0 | 187 lwi r3,_start |
| 188 mtlr r3 | |
| 189 blr | |
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190 .endm |
| 0 | 191 |
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192 # Generic vector macro |
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193 |
| 0 | 194 .macro exception_vector name |
| 195 .p2align 8 | |
| 196 .globl __exception_\name | |
| 197 __exception_\name: | |
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198 mtspr SPRG1,r3 # stash some work registers away |
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199 mtspr SPRG2,r4 |
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200 mtspr SPRG3,r5 |
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201 mfcr r4 # stash CR |
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202 li r5,__exception_\name@L # load low half of vector addr |
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203 srwi r5,r5,6 # shift right by 6 |
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204 lwi r3,hal_vsr_table # table base |
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205 lwzx r3,r3,r5 # address of vsr |
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206 mflr r5 # save link register |
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207 mtlr r3 # put vsr address into it |
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208 li r3,__exception_\name@L # reload low half of vector addr |
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209 blr # go to common code |
| 0 | 210 .endm |
| 211 | |
| 2 | 212 #--------------------------------------------------------------------------- |
| 0 | 213 # Define the exception vectors. |
| 214 | |
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215 rom_vectors: |
| 0 | 216 # These are the architecture defined vectors that |
| 217 # are always present. | |
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218 exception_vector reserved_00000 |
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219 reset_vector reset |
| 0 | 220 exception_vector machine_check |
| 221 exception_vector data_storage | |
| 222 exception_vector instruction_storage | |
| 223 exception_vector external | |
| 224 exception_vector alignment | |
| 225 exception_vector program | |
| 226 exception_vector floatingpoint_unavailable | |
| 227 exception_vector decrementer | |
| 228 exception_vector reserved_00a00 | |
| 229 exception_vector reserved_00b00 | |
| 230 exception_vector system_call | |
| 231 exception_vector trace | |
| 232 exception_vector floatingpoint_assist | |
| 233 exception_vector reserved_00f00 | |
| 234 | |
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235 # Variants may define extra vectors. |
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236 hal_extra_vectors |
| 0 | 237 |
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238 rom_vectors_end: |
| 0 | 239 |
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240 #else // CYG_HAL_STARTUP_ROM || CYGSEM_HAL_POWERPC_COPY_VECTORS |
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241 |
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242 # When vectors are not included this is the primary entry point. |
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243 .globl __exception_reset |
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244 __exception_reset: |
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245 lwi r3,_start |
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246 mtlr r3 |
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247 blr |
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248 |
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249 #endif // CYG_HAL_STARTUP_ROM || CYGSEM_HAL_POWERPC_COPY_VECTORS |
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250 |
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251 |
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252 |
| 2 | 253 #=========================================================================== |
| 254 # Real startup code. We jump here from the various reset vectors to set up | |
| 255 # the world. | |
| 0 | 256 |
| 257 .text | |
| 258 .globl _start | |
| 2 | 259 _start: |
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260 # Initialize CPU to a post-reset state, ensuring the ground doesn''t |
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261 # shift under us while we try to set things up. |
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262 hal_cpu_init |
| 0 | 263 |
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264 #if !defined(CYG_HAL_STARTUP_ROM) && defined(CYGSEM_HAL_POWERPC_COPY_VECTORS) |
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265 lwi r3,rom_vectors-4 |
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266 lwi r4,0x0000-4 |
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267 lwi r5,rom_vectors_end-4 |
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268 0: lwzu r0,4(r3) |
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269 stwu r0,4(r4) |
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270 cmplw r3,r5 |
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271 bne 0b |
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272 #endif |
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273 |
| 0 | 274 # Set up global offset table |
| 275 lwi r2,_GLOBAL_OFFSET_TABLE_ | |
| 276 | |
| 277 # set up time base register to zero | |
| 278 xor r3,r3,r3 | |
| 2 | 279 mtspr TBL_W,r3 |
| 0 | 280 xor r4,r4,r4 |
| 2 | 281 mtspr TBU_W,r4 |
| 282 | |
| 283 # Call platform specific hardware initialization | |
| 284 # This may include memory controller initialization. It is not | |
| 285 # safe to access RAM until after this point. | |
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286 bl hal_hardware_init # this is platform dependent |
| 0 | 287 |
| 288 # set up stack | |
| 289 lwi sp,__interrupt_stack | |
| 2 | 290 mtspr SPRG0,sp # save in sprg0 for later use |
| 0 | 291 |
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292 # Set up exception handlers and VSR table, taking care not to |
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293 # step on any ROM monitor''s toes. |
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294 hal_mon_init |
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295 |
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296 #if defined(CYG_HAL_STARTUP_ROM) |
| 0 | 297 |
| 298 # Copy data from ROM to ram | |
| 299 lwi r3,__rom_data_start # r3 = rom start | |
| 300 lwi r4,__ram_data_start # r4 = ram start | |
| 301 lwi r5,__ram_data_end # r5 = ram end | |
| 302 | |
| 303 cmplw r4,r5 # skip if no data | |
| 304 beq 2f | |
| 305 | |
| 306 1: | |
| 307 lwz r0,0(r3) # get word from ROM | |
| 308 stw r0,0(r4) # store in RAM | |
| 309 addi r3,r3,4 # increment by 1 word | |
| 310 addi r4,r4,4 # increment by 1 word | |
| 311 cmplw r4,r5 # compare | |
| 312 blt 1b # loop if not yet done | |
| 313 2: | |
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314 #endif |
| 2 | 315 |
| 0 | 316 # clear BSS |
| 317 lwi r3,__bss_start # r3 = start | |
| 2 | 318 lwi r4,__bss_end # r4 = end |
| 0 | 319 li r0,0 # r0 = 0 |
| 320 cmplw r3,r4 # skip if no bss | |
| 321 beq 2f | |
| 322 | |
| 2 | 323 1: stw r0,0(r3) # store zero |
| 0 | 324 addi r3,r3,4 # increment by 1 word |
| 325 cmplw r3,r4 # compare | |
| 326 blt 1b # loop if not yet done | |
| 327 2: | |
| 328 | |
| 2 | 329 # clear SBSS |
| 330 lwi r3,__sbss_start # r3 = start | |
| 331 lwi r4,__sbss_end # r4 = end | |
| 332 cmplw r3,r4 # skip if no sbss | |
| 333 beq 2f | |
| 334 | |
| 335 1: stw r0,0(r3) # store zero | |
| 336 addi r3,r3,4 # increment by 1 word | |
| 337 cmplw r3,r4 # compare | |
| 338 blt 1b # loop if not yet done | |
| 339 2: | |
| 340 | |
| 341 # It is now safe to call C functions which may rely on initialized | |
| 342 # data. | |
| 343 | |
| 344 # Set up stack for calls to C code. | |
| 0 | 345 subi sp,sp,12 # make space on stack |
| 346 li r0,0 | |
| 347 stw r0,0(sp) # clear back chain | |
| 348 stw r0,8(sp) # zero return pc | |
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349 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 2 | 350 |
| 351 # Initialize MMU. | |
| 352 bl hal_MMU_init | |
| 353 | |
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354 # Enable MMU so we can safely enable caches. |
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355 lwi r3,CYG_MSR # interrupts enabled later |
| 2 | 356 sync |
| 357 mtmsr r3 | |
| 358 sync | |
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359 |
| 2 | 360 # Enable caches |
| 361 bl hal_enable_caches | |
| 0 | 362 |
| 2 | 363 # call c++ constructors |
| 364 bl cyg_hal_invoke_constructors | |
| 0 | 365 |
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366 # set up platform specific interrupt environment |
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367 bl hal_IRQ_init |
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368 |
| 2 | 369 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
| 370 bl initialize_stub | |
| 0 | 371 #endif |
| 372 | |
| 373 bl cyg_start # call cyg_start | |
| 374 9: | |
| 375 b 9b # if we return, loop | |
| 376 | |
| 2 | 377 #--------------------------------------------------------------------------- |
| 0 | 378 # This code handles the common part of all exception handlers. |
| 379 # It saves the machine state onto the stack and then calls | |
| 380 # a "C" routine to do the rest of the work. This work may result | |
| 381 # in thread switches, and changes to the saved state. When we return | |
| 382 # here the saved state is restored and execution is continued. | |
| 383 | |
| 384 .text | |
| 385 | |
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386 .globl cyg_hal_default_exception_vsr |
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387 cyg_hal_default_exception_vsr: |
| 0 | 388 |
| 389 # We come here with all register containing their | |
| 390 # pre-exception values except: | |
| 391 # R3 = ls 16 bits of vector address | |
| 392 # R4 = saved CR | |
| 393 # R5 = saved LR | |
| 394 # LR = VSR address | |
| 395 # SPRG1 = old R3 | |
| 396 # SPRG2 = old R4 | |
| 397 # SPRG3 = old R5 | |
| 398 # SRR0 = old PC | |
| 2 | 399 # SRR1 = old MSR and the exception cause (the POW state is lost!) |
| 0 | 400 |
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401 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT |
| 0 | 402 # leave space for registers and |
| 403 # a safety margin | |
| 404 | |
| 405 # First, save away some registers | |
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406 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector |
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407 stw r4,CYGARC_PPCREG_CR(sp) # stash CR |
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408 stw r5,CYGARC_PPCREG_LR(sp) # stash LR |
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409 |
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410 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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411 # Mark this fram as an Exception frame |
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412 lwi r3,0xDDDDDDE0 |
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413 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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414 lwi r3,0xDDDDDDE1 |
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415 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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416 #endif |
| 2 | 417 |
| 418 # Enable MMU. | |
|
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419 lwi r3,CYG_MSR |
| 2 | 420 sync |
| 421 mtmsr r3 | |
| 422 sync | |
| 423 | |
| 424 mfspr r3,SPRG1 # save original R3 | |
|
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425 stw r3,CYGARC_PPCREG_REGS+3*4(sp) |
| 2 | 426 mfspr r4,SPRG2 # save original R4 |
|
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427 stw r4,CYGARC_PPCREG_REGS+4*4(sp) |
| 2 | 428 mfspr r5,SPRG3 # save original R5 |
|
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429 stw r5,CYGARC_PPCREG_REGS+5*4(sp) |
| 0 | 430 |
|
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431 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0 |
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432 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2 |
| 0 | 433 |
|
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434 mr r3,sp # recreate original SP |
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435 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT |
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436 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state |
| 0 | 437 |
| 2 | 438 # Save registers r6..r12/r31 |
| 0 | 439 .set _reg,6 |
| 440 .rept MAX_SAVE_REG+1-6 | |
|
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441 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 442 .set _reg,_reg+1 |
| 443 .endr | |
| 444 | |
| 2 | 445 # Save registers used in vsr (r14+r15) |
|
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446 stw r14,(CYGARC_PPCREG_REGS+14*4)(sp) |
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447 stw r15,(CYGARC_PPCREG_REGS+15*4)(sp) |
| 2 | 448 |
|
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449 # get remaining family CPU registers |
| 0 | 450 mfxer r3 |
|
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451 mfctr r4 |
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452 mfsrr0 r5 |
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453 mfsrr1 r6 |
| 0 | 454 # and store them |
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455 stw r3,CYGARC_PPCREG_XER(sp) |
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456 stw r4,CYGARC_PPCREG_CTR(sp) |
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457 stw r5,CYGARC_PPCREG_PC(sp) |
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458 stw r6,CYGARC_PPCREG_MSR(sp) |
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459 |
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460 # Save variant registers |
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461 hal_variant_save sp |
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462 |
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463 # Save FPU registers |
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464 hal_fpu_save sp |
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465 |
| 0 | 466 # The entire CPU state is now stashed on the stack, |
| 467 # call into C to do something with it. | |
| 468 | |
| 469 mr r3,sp # R3 = register dump | |
| 470 | |
|
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471 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 472 |
| 473 li r0,0 # R0 = 0 | |
| 474 stw r0,0(sp) # backchain = 0 | |
| 475 stw r0,8(sp) # return pc = 0 | |
| 476 | |
|
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477 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 478 # where C code can save LR |
| 479 | |
| 480 lwi r5,restore_state # get return link | |
| 481 mtlr r5 # to link register | |
| 482 | |
| 2 | 483 .extern cyg_hal_exception_handler |
| 484 b cyg_hal_exception_handler # call C code, r3 = registers | |
| 0 | 485 |
| 486 # When the call returns it will go to restore_state below. | |
| 487 | |
| 488 | |
| 2 | 489 ##-------------------------------------------------------------------------- |
| 490 ## The following macros are defined depending on whether the Interrupt | |
| 491 ## system is using isr tables or chaining, and depending on the interrupt | |
| 492 ## controller in the system. | |
| 493 | |
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494 #ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED |
| 2 | 495 |
|
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496 ## This is the simple version. No interrupt controller, CYGARC_PPCREG_VECTOR |
| 2 | 497 ## is updated with the decoded interrupt vector. Isr tables/chaining |
| 498 ## use same interrupt decoder. | |
| 499 ## Bit 21 biffers between decrementer (0) and external (1). | |
| 500 | |
| 501 # decode the interrupt | |
|
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502 .macro hal_intc_decode dreg,state |
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503 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number, |
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504 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update |
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505 stw \dreg,CYGARC_PPCREG_VECTOR(\state) # vector in state frame. |
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506 slwi \dreg,\dreg,2 # convert to word offset. |
| 2 | 507 .endm |
| 508 | |
|
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509 #endif // CYGPKG_HAL_POWERPC_INTC_DEFINED |
| 2 | 510 |
| 511 #--------------------------------------------------------------------------- | |
| 0 | 512 # Common interrupt handling code. |
| 513 | |
|
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514 .globl cyg_hal_default_interrupt_vsr |
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515 cyg_hal_default_interrupt_vsr: |
| 0 | 516 |
| 517 # We come here with all register containing their | |
| 518 # pre-exception values except: | |
| 519 # R3 = ls 16 bits of vector address | |
| 520 # R4 = saved CR | |
| 521 # R5 = saved LR | |
| 522 # LR = VSR address | |
| 523 # SPRG1 = old R3 | |
| 524 # SPRG2 = old R4 | |
| 525 # SPRG3 = old R5 | |
| 526 # SRR0 = old PC | |
| 527 # SRR1 = old MSR | |
| 528 | |
| 529 | |
|
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530 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT |
| 0 | 531 # leave space for registers and |
| 532 # a safety margin | |
| 533 | |
|
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534 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector |
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535 stw r4,CYGARC_PPCREG_CR(sp) # stash CR |
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536 stw r5,CYGARC_PPCREG_LR(sp) # stash LR |
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537 |
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538 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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539 # Mark this fram as an 1nterrupt frame |
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540 lwi r3,0xDDDDDD10 |
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541 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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542 lwi r3,0xDDDDDD11 |
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543 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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544 #endif |
| 0 | 545 |
| 2 | 546 # Enable MMU. |
|
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547 lwi r3,CYG_MSR |
| 2 | 548 sync |
| 549 mtmsr r3 | |
| 550 sync | |
| 551 | |
| 552 mfspr r3,SPRG1 # save original R3 | |
|
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553 stw r3,CYGARC_PPCREG_REGS+3*4(sp) |
| 2 | 554 mfspr r4,SPRG2 # save original R4 |
|
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555 stw r4,CYGARC_PPCREG_REGS+4*4(sp) |
| 2 | 556 mfspr r5,SPRG3 # save original R5 |
|
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557 stw r5,CYGARC_PPCREG_REGS+5*4(sp) |
| 0 | 558 |
|
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559 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0 |
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560 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2 |
| 0 | 561 |
|
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562 mr r3,sp # recreate original SP |
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563 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT |
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564 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state |
| 0 | 565 |
| 2 | 566 # Save registers r6..r12/r31 |
| 0 | 567 .set _reg,6 |
| 568 .rept MAX_SAVE_REG+1-6 | |
|
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569 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 570 .set _reg,_reg+1 |
| 571 .endr | |
| 572 | |
| 2 | 573 # Save registers used in vsr (r14+r15) |
|
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574 stw r14,CYGARC_PPCREG_REGS+14*4(sp) |
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575 stw r15,CYGARC_PPCREG_REGS+15*4(sp) |
| 2 | 576 |
|
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577 # get remaining family CPU registers |
| 0 | 578 mfxer r3 |
|
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579 mfctr r4 |
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580 mfsrr0 r5 |
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581 mfsrr1 r6 |
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582 |
| 0 | 583 # and store them |
|
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584 stw r3,CYGARC_PPCREG_XER(sp) |
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585 stw r4,CYGARC_PPCREG_CTR(sp) |
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586 stw r5,CYGARC_PPCREG_PC(sp) |
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587 stw r6,CYGARC_PPCREG_MSR(sp) |
| 0 | 588 |
|
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589 # Save variant registers |
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590 hal_variant_save sp |
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591 |
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592 # Save FPU registers |
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593 hal_fpu_save sp |
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594 |
| 0 | 595 # The entire CPU state is now stashed on the stack, |
| 596 # increment the scheduler lock and call the ISR | |
| 597 # for this vector. | |
| 598 | |
| 599 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 2 | 600 .extern cyg_scheduler_sched_lock |
| 601 lwi r3,cyg_scheduler_sched_lock | |
| 0 | 602 lwz r4,0(r3) |
| 603 addi r4,r4,1 | |
| 604 stw r4,0(r3) | |
| 605 #endif | |
| 606 | |
| 2 | 607 mr r14,sp # r14 = register dump |
| 0 | 608 |
| 609 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 610 lwi r3,__interrupt_stack # stack top | |
| 611 lwi r4,__interrupt_stack_base # stack base | |
| 612 sub. r5,sp,r4 # sp - base | |
| 613 blt 1f # if < 0 - not on istack | |
| 614 sub. r5,r3,sp # top - sp | |
| 615 bgt 2f # if > 0 - already on istack | |
| 616 | |
| 617 1: mr sp,r3 # switch to istack | |
| 618 | |
| 2 | 619 2: stwu r14,-4(sp) # save old SP on stack |
| 0 | 620 |
| 621 #endif | |
| 622 | |
|
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623 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 624 |
| 625 li r0,0 # R0 = 0 | |
| 626 stw r0,0(sp) # backchain = 0 | |
| 627 stw r0,8(sp) # return pc = 0 | |
| 628 | |
|
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629 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 630 # where C code can save LR |
| 631 | |
| 632 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 633 | |
| 634 lwi r3,0x0301 # r3 = type = INTR,RAISE | |
|
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635 lwz r4,CYGARC_PPCREG_VECTOR(r14) # arg1 = vector address |
| 0 | 636 srwi r4,r4,8 # arg1 = vector number |
| 637 xor r5,r5,r5 # arg2 = 0 | |
| 638 bl cyg_instrument # call instrument function | |
| 639 | |
| 640 #endif | |
| 641 | |
|
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642 hal_intc_decode r15,r14 # get table index |
| 2 | 643 |
| 0 | 644 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
| 645 .extern cyg_hal_gdb_isr | |
|
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646 lwz r3,CYGARC_PPCREG_PC(r14) # for serial receive irq. |
| 2 | 647 bl cyg_hal_gdb_isr # (arg1 is PC) |
| 0 | 648 cmpwi r3,0x0000 # Call ISR proper? |
| 649 beq 2f # (r3 is 0 when skipping | |
| 650 # to avoid DSR call) | |
| 651 1: | |
| 652 #endif | |
| 653 | |
| 2 | 654 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING |
| 0 | 655 |
|
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656 #ifdef CYGPKG_HAL_POWERPC_MPC8xx |
| 2 | 657 # The CPM controller allows nested interrupts. However, |
| 658 # it sits on the back of the SIU controller which has no | |
| 659 # HW support for this. In effect, SW masking of lower | |
| 660 # priority IRQs in the SIU would be required for this to work. | |
| 661 #endif | |
| 662 | |
| 663 #endif | |
| 664 | |
|
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665 lwz r3,CYGARC_PPCREG_VECTOR(r14) # retrieve decoded vector # |
| 0 | 666 |
| 667 lwi r6,hal_interrupt_handlers # get interrupt handler table | |
| 668 lwzx r6,r6,r15 # load routine pointer | |
| 669 | |
| 670 lwi r4,hal_interrupt_data # get interrupt data table | |
| 671 lwzx r4,r4,r15 # load data pointer | |
| 672 # R4 = data argument | |
| 673 | |
| 674 mtctr r6 # put isr address in ctr | |
| 675 | |
| 676 bctrl # branch to ctr reg and link | |
| 677 | |
| 678 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT | |
| 679 # If interrupt was caused by GDB, the ISR call above | |
| 680 # is skipped by jumping here. | |
| 681 2: | |
| 682 #endif | |
| 683 | |
| 684 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 685 | |
| 686 # If we are returning from the last nested interrupt, move back | |
| 687 # to the thread stack. interrupt_end() must be called on the | |
| 688 # thread stack since it potentially causes a context switch. | |
| 689 # Since we have arranged for the top of stack location to | |
| 690 # contain the sp we need to go back to here, just pop it off | |
| 691 # and put it in SP. | |
| 692 | |
| 693 | |
|
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694 lwz sp,CYGARC_PPC_STACK_FRAME_SIZE*2(sp) # sp = *sp |
| 0 | 695 |
|
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696 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 697 |
| 698 li r0,0 # R0 = 0 | |
| 699 stw r0,0(sp) # backchain = 0 | |
| 700 stw r0,8(sp) # return pc = 0 | |
| 701 | |
|
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702 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 703 # where C code can save LR |
| 704 #endif | |
| 705 | |
| 706 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 707 | |
| 708 # We only need to call _interrupt_end() when there is a kernel | |
| 709 # present to do any tidying up. | |
| 710 | |
| 711 # on return r3 bit 1 will indicate whether a DSR is | |
| 712 # to be posted. Pass this together with a pointer to | |
| 713 # the interrupt object we have just used to the | |
| 714 # interrupt tidy up routine. | |
| 715 | |
| 2 | 716 # Note that r14 and r15 are defined to be preserved across |
| 0 | 717 # calls by the calling convention, so they still contain |
| 718 # the register dump and the vector number respectively. | |
| 2 | 719 |
| 0 | 720 lwi r4,hal_interrupt_objects # get interrupt object table |
| 721 lwzx r4,r4,r15 # load object pointer | |
|
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722 mr r5,r14 # arg3 = saved register dump |
| 0 | 723 |
| 724 .extern interrupt_end | |
| 725 bl interrupt_end # call into C to finish off | |
| 726 #endif | |
| 727 | |
| 728 restore_state: | |
| 729 # All done, restore CPU state and continue | |
| 730 | |
|
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731 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE*2 # retrieve CPU state pointer |
| 0 | 732 |
| 733 # get sprs we want to restore | |
|
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734 # stuff some of them into the CPU |
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735 lwz r3,CYGARC_PPCREG_XER(sp) |
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736 lwz r4,CYGARC_PPCREG_LR(sp) |
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737 lwz r5,CYGARC_PPCREG_CTR(sp) |
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738 mtxer r3 |
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739 mtlr r4 |
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740 mtctr r5 |
| 0 | 741 |
| 2 | 742 # Restore registers used in vsr (r14+r15) |
|
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743 lwz r14,CYGARC_PPCREG_REGS+14*4(r1) |
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744 lwz r15,CYGARC_PPCREG_REGS+15*4(r1) |
| 2 | 745 |
| 746 # restore registers r6..r12/r31 | |
| 0 | 747 .set _reg,6 |
| 748 .rept MAX_SAVE_REG+1-6 | |
|
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749 lwz _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 750 .set _reg,_reg+1 |
| 751 .endr | |
| 752 | |
|
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753 hal_cpu_int_disable |
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754 |
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755 # restore R0 and R2 |
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756 lwz r0,CYGARC_PPCREG_REGS+0*4(sp) |
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757 lwz r2,CYGARC_PPCREG_REGS+2*4(sp) |
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758 |
| 0 | 759 # Here all the registers are loaded except |
|
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760 # sp = HAL_SavedRegisters |
| 0 | 761 # r3 = ccr |
| 762 # r4 = srr0 = pc | |
| 763 # r5 = srr1 = msr | |
|
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764 # |
| 0 | 765 # We have to disable interrupts while srr0 and |
| 766 # srr1 are loaded, since another interrupt will | |
| 767 # destroy them. | |
| 768 | |
|
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769 lwz r3,CYGARC_PPCREG_CR(sp) |
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770 lwz r4,CYGARC_PPCREG_PC(sp) |
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771 lwz r5,CYGARC_PPCREG_MSR(sp) |
| 0 | 772 mtcr r3 # set ccr |
| 773 mtsrr0 r4 # load old pc | |
| 774 mtsrr1 r5 # load old msr | |
| 775 | |
|
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776 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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777 # Mark this frame as (almost) dead. |
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778 lwi r3,0xDDDDDDD0 |
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779 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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780 lwi r3,0xDDDDDDD1 |
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781 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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782 #endif |
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783 |
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784 lwz r3,CYGARC_PPCREG_REGS+3*4(sp) # load r3 value |
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785 lwz r4,CYGARC_PPCREG_REGS+4*4(sp) # load r4 value |
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786 lwz r5,CYGARC_PPCREG_REGS+5*4(sp) # load r5 value |
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787 lwz sp,CYGARC_PPCREG_REGS+1*4(sp) # restore sp |
| 0 | 788 |
| 789 sync # settle things down | |
| 790 isync | |
| 791 rfi # and return | |
| 792 | |
|
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793 |
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794 |
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795 ##----------------------------------------------------------------------------- |
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796 ## Execute pending DSRs on the interrupt stack with interrupts enabled. |
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797 ## Note: this can only be called from code running on a thread stack |
|
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798 |
|
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799 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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800 .extern cyg_interrupt_call_pending_DSRs |
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801 |
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802 FUNC_START(hal_interrupt_stack_call_pending_DSRs) |
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803 # Change to interrupt stack, save state and set up stack for |
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804 # calls to C code. |
|
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805 mr r3,sp |
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806 lwi r4,__interrupt_stack |
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807 subi r4,r4,24 # make space on stack |
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808 mr sp,r4 |
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809 stw r3,12(sp) # save old sp |
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810 mfmsr r3 |
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811 stw r3,16(sp) # save old MSR |
|
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812 mflr r3 |
|
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813 stw r3,20(sp) # save old LR |
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814 |
|
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815 li r0,0 |
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816 stw r0,0(sp) # clear back chain |
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817 stw r0,8(sp) # zero return pc |
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818 |
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819 hal_cpu_int_enable |
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820 |
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821 # Call into kernel which will execute DSRs |
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822 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) |
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823 bl cyg_interrupt_call_pending_DSRs |
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824 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE |
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825 |
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826 lwz r3,20(sp) # restore LR |
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827 mtlr r3 |
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828 lwz r5,12(sp) # get SP from saved state |
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829 lwz r3,16(sp) # restore interrupt setting |
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830 hal_cpu_int_merge r3 |
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831 |
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832 mr sp,r5 # restore stack pointer |
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833 blr # and return to caller |
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834 #endif |
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835 |
| 2 | 836 #--------------------------------------------------------------------------- |
| 0 | 837 ## Temporary interrupt stack |
| 838 | |
| 839 .section ".bss" | |
| 840 | |
| 841 .balign 16 | |
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842 .global cyg_interrupt_stack_base |
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843 cyg_interrupt_stack_base: |
| 0 | 844 __interrupt_stack_base: |
| 845 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 846 .byte 0 | |
| 847 .endr | |
| 848 .balign 16 | |
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849 .global cyg_interrupt_stack |
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850 cyg_interrupt_stack: |
| 0 | 851 __interrupt_stack: |
| 852 | |
| 853 .long 0,0,0,0,0,0,0,0 | |
| 854 | |
| 2 | 855 #--------------------------------------------------------------------------- |
| 0 | 856 # end of vectors.S |