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1 #ifndef CYGONCE_HAL_HAL_ARCH_H |
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2 #define CYGONCE_HAL_HAL_ARCH_H |
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3 |
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4 //========================================================================== |
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5 // |
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6 // hal_arch.h |
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7 // |
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8 // Architecture specific abstractions |
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9 // |
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10 //========================================================================== |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //========================================================================== |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg |
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36 // Contributors: nickg |
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37 // Date: 1999-02-17 |
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38 // Purpose: Define architecture abstractions |
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39 // Usage: #include <cyg/hal/hal_arch.h> |
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40 // |
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41 //####DESCRIPTIONEND#### |
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42 // |
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43 //========================================================================== |
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44 |
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45 #include <pkgconf/hal.h> |
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46 #include <cyg/infra/cyg_type.h> |
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47 |
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48 //-------------------------------------------------------------------------- |
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49 // Processor saved states: |
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50 // The layout of this structure is also defined in "mips.inc", for assembly |
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51 // code. Do not change this without changing that (or vice versa). |
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52 |
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53 typedef struct |
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54 { |
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55 // These are common to all saved states |
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56 cyg_uint32 d[32]; /* Data regs */ |
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57 cyg_uint32 hi; /* hi word of mpy/div reg */ |
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58 cyg_uint32 lo; /* lo word of mpy/div reg */ |
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59 |
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60 // These are only saved for exceptions and interrupts |
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61 cyg_uint32 vector; /* Vector number */ |
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62 cyg_uint32 pc; /* Program Counter */ |
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63 cyg_uint32 sr; /* Status Reg */ |
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64 cyg_uint32 cache; /* Cache control register */ |
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65 |
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66 |
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67 // These are only saved for exceptions, and are not restored |
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68 // when continued. |
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69 cyg_uint32 cause; /* Exception cause register */ |
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70 cyg_uint32 badvr; /* Bad virtual address reg */ |
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71 cyg_uint32 prid; /* Processor Version */ |
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72 cyg_uint32 config; /* Config register */ |
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73 } HAL_SavedRegisters; |
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74 |
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75 //-------------------------------------------------------------------------- |
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76 // Exception handling function. |
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77 // This function is defined by the kernel according to this prototype. It is |
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78 // invoked from the HAL to deal with any CPU exceptions that the HAL does |
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79 // not want to deal with itself. It usually invokes the kernel's exception |
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80 // delivery mechanism. |
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81 |
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82 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); |
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83 |
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84 //-------------------------------------------------------------------------- |
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85 // Bit manipulation macros |
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86 |
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87 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); |
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88 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); |
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89 |
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90 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask); |
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91 |
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92 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask); |
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93 |
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94 //-------------------------------------------------------------------------- |
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95 // Context Initialization |
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96 // Initialize the context of a thread. |
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97 // Arguments: |
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98 // _sparg_ name of variable containing current sp, will be written with new sp |
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99 // _thread_ thread object address, passed as argument to entry point |
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100 // _entry_ entry point address. |
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101 // _id_ bit pattern used in initializing registers, for debugging. |
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102 |
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103 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ |
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104 { \ |
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105 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56; \ |
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106 register HAL_SavedRegisters *_regs_; \ |
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107 int _i_; \ |
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108 _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \ |
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109 for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_; \ |
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110 (_regs_)->d[29] = (CYG_WORD)(_sp_); /* SP = top of stack */ \ |
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111 (_regs_)->d[04] = (CYG_WORD)(_thread_); /* R4 = arg1 = thread ptr */ \ |
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112 (_regs_)->lo = 0; /* LO = 0 */ \ |
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113 (_regs_)->hi = 0; /* HI = 0 */ \ |
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114 (_regs_)->d[30] = (CYG_WORD)(_sp_); /* FP = top of stack */ \ |
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115 (_regs_)->d[31] = (CYG_WORD)(_entry_); /* LR(d[31]) = entry point*/ \ |
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116 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = entry point */ \ |
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117 _sparg_ = (CYG_ADDRESS)_regs_; \ |
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118 } |
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119 |
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120 //-------------------------------------------------------------------------- |
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121 // Context switch macros. |
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122 // The arguments are pointers to locations where the stack pointer |
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123 // of the current thread is to be stored, and from where the sp of the |
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124 // next thread is to be fetched. |
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125 |
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126 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); |
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127 externC void hal_thread_load_context( CYG_ADDRESS to ) |
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128 __attribute__ ((noreturn)); |
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129 |
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130 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ |
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131 hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \ |
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132 (CYG_ADDRESS)_fspptr_); |
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133 |
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134 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ |
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135 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); |
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136 |
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137 //-------------------------------------------------------------------------- |
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138 // Execution reorder barrier. |
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139 // When optimizing the compiler can reorder code. In multithreaded systems |
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140 // where the order of actions is vital, this can sometimes cause problems. |
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141 // This macro may be inserted into places where reordering should not happen. |
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142 // The "memory" keyword is potentially unnecessary, but it is harmless to |
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143 // keep it. |
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144 |
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145 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) |
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146 |
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147 //-------------------------------------------------------------------------- |
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148 // Breakpoint support |
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149 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to |
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150 // happen if executed. |
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151 // HAL_BREAKINST is the value of the breakpoint instruction and |
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152 // HAL_BREAKINST_SIZE is its size in bytes. |
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153 |
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154 #ifdef CYG_HAL_MIPS_SIM |
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155 #define HAL_BREAKPOINT(_label_) \ |
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156 /* This code causes a fake breakpoint. */ \ |
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157 asm volatile ( \ |
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158 "lui $24,0x0000;" \ |
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159 "ori $24,0x0024;" \ |
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160 "mtc0 $24,$13;" \ |
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161 "lui $25,%%hi(1f);" \ |
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162 "ori $25,$25,%%lo(1f);" \ |
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163 "j other_vector;" \ |
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164 "nop;" \ |
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165 ".global " #_label_ ";" \ |
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166 #_label_":" \ |
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167 "1: nop;" \ |
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168 : \ |
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169 : \ |
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170 : "t8", "t9" \ |
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171 ); |
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172 #else |
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173 #define HAL_BREAKPOINT(_label_) \ |
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174 asm volatile (" .globl " #_label_ ";" \ |
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175 #_label_":" \ |
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176 " break 5" \ |
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177 ); |
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178 #endif // CYG_HAL_MIPS_SIM |
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179 |
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180 #define HAL_BREAKINST 0x0005000d |
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181 |
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182 #define HAL_BREAKINST_SIZE 4 |
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183 |
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184 //-------------------------------------------------------------------------- |
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185 // Thread register state manipulation for GDB support. |
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186 |
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187 // Translate a stack pointer as saved by the thread context macros above into |
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188 // a pointer to a HAL_SavedRegisters structure. |
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189 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ |
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190 (_regs_) = (HAL_SavedRegisters *)(_sp_) |
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191 |
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192 // Copy a set of registers from a HAL_SavedRegisters structure into a |
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193 // GDB ordered array. |
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194 #define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ |
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195 { \ |
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196 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ |
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197 int _i_; \ |
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198 \ |
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199 for( _i_ = 0; _i_ < 32; _i_++ ) \ |
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200 _regval_[_i_] = (_regs_)->d[_i_]; \ |
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201 \ |
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202 _regval_[32] = (_regs_)->sr; \ |
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203 _regval_[33] = (_regs_)->lo; \ |
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204 _regval_[34] = (_regs_)->hi; \ |
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205 _regval_[35] = (_regs_)->badvr; \ |
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206 _regval_[36] = (_regs_)->cause; \ |
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207 _regval_[37] = (_regs_)->pc; \ |
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208 } |
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209 |
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210 // Copy a GDB ordered array into a HAL_SavedRegisters structure. |
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211 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ |
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212 { \ |
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213 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ |
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214 int _i_; \ |
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215 \ |
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216 for( _i_ = 0; _i_ < 32; _i_++ ) \ |
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217 (_regs_)->d[_i_] = _regval_[_i_]; \ |
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218 \ |
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219 (_regs_)->sr = _regval_[32]; \ |
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220 (_regs_)->lo = _regval_[33]; \ |
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221 (_regs_)->hi = _regval_[34]; \ |
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222 (_regs_)->badvr = _regval_[35]; \ |
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223 (_regs_)->cause = _regval_[36]; \ |
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224 (_regs_)->pc = _regval_[37]; \ |
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225 } |
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226 |
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227 //-------------------------------------------------------------------------- |
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228 // HAL setjmp |
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229 // Note: These definitions are repeated in hal_arch.h. If changes are |
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230 // required remember to update both sets. |
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231 |
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232 #define CYGARC_JMP_BUF_SP 0 |
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233 #define CYGARC_JMP_BUF_R16 1 |
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234 #define CYGARC_JMP_BUF_R17 2 |
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235 #define CYGARC_JMP_BUF_R18 3 |
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236 #define CYGARC_JMP_BUF_R19 4 |
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237 #define CYGARC_JMP_BUF_R20 5 |
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238 #define CYGARC_JMP_BUF_R21 6 |
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239 #define CYGARC_JMP_BUF_R22 7 |
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240 #define CYGARC_JMP_BUF_R23 8 |
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241 #define CYGARC_JMP_BUF_R28 9 |
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242 #define CYGARC_JMP_BUF_R30 10 |
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243 #define CYGARC_JMP_BUF_R31 11 |
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244 |
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245 #define CYGARC_JMP_BUF_SIZE 12 |
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246 |
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247 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; |
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248 |
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249 externC int hal_setjmp(hal_jmp_buf env); |
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250 externC void hal_longjmp(hal_jmp_buf env, int val); |
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251 |
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252 //------------------------------------------------------------------------- |
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253 // Idle thread code. |
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254 // This macro is called in the idle thread loop, and gives the HAL the |
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255 // chance to insert code. Typical idle thread behaviour might be to halt the |
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256 // processor. |
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257 |
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258 externC void hal_idle_thread_action(cyg_uint32 loop_count); |
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259 |
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260 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) |
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261 |
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262 //-------------------------------------------------------------------------- |
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263 // Minimal and sensible stack sizes: the intention is that applications |
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264 // will use these to provide a stack size in the first instance prior to |
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265 // proper analysis. Idle thread stack should be this big. |
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266 |
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267 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. |
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268 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. |
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269 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! |
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270 |
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271 // We define quite large stack needs for SPARClite, for it requires 576 |
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272 // bytes (144 words) to process an interrupt and thread-switch, and |
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273 // momentarily, but needed in case of recursive interrupts, it needs 208 |
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274 // words - if a sequence of saves to push out other regsets is interrupted. |
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275 |
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276 // This is not a config option because it should not be adjusted except |
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277 // under "enough rope" sort of disclaimers. |
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278 |
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279 // Worst case stack frame size: return link + 5 pushed registers. |
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280 #define CYGNUM_HAL_STACK_FRAME_SIZE (24) |
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281 |
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282 // Stack needed for a context switch: |
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283 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (42*4) |
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284 |
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285 // Interrupt + call to ISR, interrupt_end() and the DSR |
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286 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE) |
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287 |
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288 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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289 |
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290 // An interrupt stack which is large enough for all possible interrupt |
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291 // conditions (and only used for that purpose) exists. "User" stacks |
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292 // can be much smaller |
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293 |
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294 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \ |
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295 CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \ |
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296 CYGNUM_HAL_STACK_FRAME_SIZE*4) |
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297 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (2048) |
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298 |
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299 #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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300 |
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301 // No separate interrupt stack exists. Make sure all threads contain |
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302 // a stack sufficiently large. |
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303 |
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304 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096) |
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305 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096) |
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306 |
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307 #endif |
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308 |
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309 //-------------------------------------------------------------------------- |
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310 #endif // CYGONCE_HAL_HAL_ARCH_H |
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311 // End of hal_arch.h |
