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annotate packages/hal/powerpc/ppc40x/current/include/var_regs.h @ 149:52c99470ec11

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Merge from eCos master repository on 2001-01-19-06:43:03-GMT
author jlarmour
date Fri, 19 Jan 2001 07:37:45 +0000
parents a9ac27ec7abc
children e0c0827131d1
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1 #ifndef CYGONCE_HAL_VAR_REGS_H
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2 #define CYGONCE_HAL_VAR_REGS_H
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3
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4 //==========================================================================
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5 //
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6 // var_regs.h
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7 //
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8 // PowerPC 40x variant CPU definitions
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9 //
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10 //==========================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //==========================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): jskov
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38 // Contributors: jskov,gthomas
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39 // Date: 2000-08-27
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40 // Purpose: Provide PPC40x register definitions
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41 // Description: Provide PPC40x register definitions
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42 // The short difinitions (sans CYGARC_REG_) are exported only
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43 // if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
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44 // Usage: Included via the acrhitecture register header:
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45 // #include <cyg/hal/ppc_regs.h>
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46 // ...
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47 //
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //==========================================================================
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52
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53 //--------------------------------------------------------------------------
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54 // Cache
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55 #define CYGARC_REG_HID0 1008
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56
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57 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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58 #define HID0 CYGARC_REG_HID0
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59 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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60
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61 //--------------------------------------------------------------------------
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62 // MMU control.
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63 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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64
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65 #define SPR_EVPR 982 // Exception vector prefix
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66 #define SPR_PID 945 // Process ID
134
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67
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68 #define M_EPN_EPNMASK 0xfffff000 // effective page no mask
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69 #define M_EPN_EV 0x00000040 // entry valid
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70 #define M_EPN_SIZE(n) (n<<7) // entry size (0=1K, 1=4K, ... 7=16M)
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71
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72 #define M_RPN_RPNMASK 0xfffff000 // real page no mask
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73 #define M_RPN_EX 0x00000200 // execute enable
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74 #define M_RPN_WR 0x00000100 // write enable
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75 #define M_RPN_W 0x00000008 // write-through (when cache enabled)
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76 #define M_RPN_I 0x00000004 // cache inhibited
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77 #define M_RPN_M 0x00000002 // memory coherent (not implemented)
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78 #define M_RPN_G 0x00000001 // guarded
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79
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80 #define CYGARC_TLBWE(_id_, _hi_, _lo_) \
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81 asm volatile ("tlbwe %1,%0,0; tlbwe %2,%0,1" :: "r"(_id_), "r"(_hi_), "r"(_lo_));
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82
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83 #define CYGARC_TLBRE(_id_, _hi_, _lo_) \
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84 asm volatile ("tlbre %0,%2,0; tlbre %1,%2,1" : "=r"(_hi_), "=r"(_lo_) : "r"(_id_));
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85
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86 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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87
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88 //--------------------------------------------------------------------------
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89 // Device control register access macros.
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90 #define CYGARC_MTDCR(_tbr_, _v_) \
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91 asm volatile ("mtdcr %0, %1;" :: "I" (_tbr_), "r" (_v_));
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92 #define CYGARC_MFDCR(_tbr_, _v_) \
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93 asm volatile ("mfdcr %0, %1;" : "=r" (_v_) : "I" (_tbr_));
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94
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95 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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96
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97 // Interrupt control (device) registers
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98 #define DCR_EXIER 66
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99 #define DCR_EXISR 64
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100 #define DCR_IOCR 160
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101
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102 // Timer control (special) registers
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103 #define SPR_PIT 987
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104 #define SPR_TCR 986
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105 #define SPR_TSR 984
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106
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107 // Interval and watchdog timer control
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108 #define TCR_WP 0xC0000000 // Watchdog timer period
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109 #define TCR_WP_17 0x00000000 // 2^17 clocks
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110 #define TCR_WP_21 0x40000000 // 2^21 clocks
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111 #define TCR_WP_25 0x80000000 // 2^25 clocks
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112 #define TCR_WP_29 0xC0000000 // 2^29 clocks
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113 #define TCR_WRC 0x30000000 // Reset control
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114 #define TCR_WRC_None 0x00000000 // No reset on timeout
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115 #define TCR_WRC_Core 0x10000000 // Reset core on timeout
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116 #define TCR_WRC_Chip 0x20000000 // Reset chip on timeout
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117 #define TCR_WRC_System 0x30000000 // Reset system on timeout
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118 #define TCR_WIE 0x08000000 // Watchdog interrupt enable
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119 #define TCR_PIE 0x04000000 // Programmable timer interrupt
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120 #define TCR_FP 0x03000000 // Fixed timer interval
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121 #define TCR_FP_9 0x00000000 // 2^9 clocks
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122 #define TCR_FP_13 0x01000000 // 2^13 clocks
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123 #define TCR_FP_17 0x02000000 // 2^17 clocks
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124 #define TCR_FP_21 0x03000000 // 2^21 clocks
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125 #define TCR_FIE 0x00800000 // Fixed timer interrupt
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126 #define TCR_ARE 0x00400000 // Auto-reload enable
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127
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128 // Interval and watchdog status
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129 #define TSR_ENW 0x80000000 // Enable next watchdog
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130 #define TSR_WIS 0x40000000 // Watchdog interrupt pending
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131 #define TSR_WRS 0x30000000 // Watchdog reset state
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132 #define TSR_WRS_None 0x00000000 // No watchdog reset
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133 #define TSR_WRS_Core 0x10000000 // Core reset by watchdog
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134 #define TSR_WRS_Chip 0x20000000 // Chip reset by watchdog
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135 #define TSR_WRS_System 0x30000000 // System reset by watchdog
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136 #define TSR_PIS 0x08000000 // Programmable timer interrupt
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137 #define TSR_FIS 0x04000000 // Fixed timer interrupt
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138
149
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139 // Debug registers
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140 #define SPR_DBSR 1008
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141 #define SPR_DBCR 1010
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142
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143 #define DBCR_IDM 0x40000000 // Internal debug enable
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144 #define DBCR_IC 0x08000000 // Instruction completion
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145
136
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146 #endif // CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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147
134
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148 //-----------------------------------------------------------------------------
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149 #endif // ifdef CYGONCE_HAL_VAR_REGS_H
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150 // End of var_regs.h