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annotate packages/hal/arm/edb7xxx/current/include/hal_cache.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg, gthomas
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46 // Contributors: nickg, gthomas
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47 // Date: 1998-09-28
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48 // Purpose: Cache control API
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // cache control operations.
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51 // Usage:
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52 // #include <cyg/hal/hal_cache.h>
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53 // ...
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54 //
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //=============================================================================
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59
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60 #include <cyg/infra/cyg_type.h>
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61 #include <cyg/hal/hal_mmu.h>
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62
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63 //-----------------------------------------------------------------------------
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64 // FIXME: This definition forces the IO flash driver to use a
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65 // known-good procedure for fiddling flash before calling flash device
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66 // driver functions. The procedure breaks on other platform/driver
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67 // combinations though so is depricated. Hence this definition.
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68 //
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69 // If you work on this target, please try to remove this definition
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70 // and verify that the flash driver still works (both from RAM and
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71 // flash). If it does, remove the definition and this comment for good
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72 // [and the old macro definition if this happens to be the last client
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73 // of that code].
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74 #define HAL_FLASH_CACHES_OLD_MACROS
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75
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76 //-----------------------------------------------------------------------------
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77 // Cache dimensions
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78
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79 #define HAL_UCACHE_SIZE 0x2000 // Size of data cache in bytes
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80 #define HAL_UCACHE_LINE_SIZE 16 // Size of a data cache line
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81 #define HAL_UCACHE_WAYS 4 // Associativity of the cache
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82 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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83
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84 #define HAL_CACHE_UNIFIED // Let programs know the caches are combined
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85
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86 //-----------------------------------------------------------------------------
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87 // Global control of caches
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88
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89 // Note: the 'mrc' doesn't seem to work.
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90 #if 0
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91 // Enable the data cache
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92 // mrc MMU_CP,0,r1,MMU_Control,c0
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93 // orr r1,r1,#MMU_Control_C|MMU_Control_B
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94 // mcr MMU_CP,0,r1,MMU_Control,c0
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95
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96 #define HAL_UCACHE_ENABLE() \
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97 { \
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98 asm volatile ("mrc p15,0,r1,c1,c0;" \
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99 "orr r1,r1,#0x000C;" \
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100 "mcr p15,0,r1,c1,c0;" \
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101 : \
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102 : \
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103 : "r1" /* Clobber list */ \
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104 ); \
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105 \
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106 }
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107
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108 // Disable the data cache
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109 #define HAL_UCACHE_DISABLE() \
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110 { \
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111 asm volatile ("mrc p15,0,r1,c1,c0;" \
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112 "bic r1,r1,#0x000C;" \
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113 "mcr p15,0,r1,c1,c0;" \
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114 : \
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115 : \
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116 : "r1" /* Clobber list */ \
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117 ); \
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118 \
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119 }
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120 #else
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121 #define HAL_UCACHE_ENABLE() \
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122 { \
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123 asm volatile ("mov r1,#0x7D;" \
143
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124 "mcr p15,0,r1,c1,c0,0;" \
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125 : \
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126 : \
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127 : "r1" /* Clobber list */ \
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128 ); \
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129 }
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130
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131 // Disable the data cache
143
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132 #define HAL_UCACHE_DISABLE() \
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133 { \
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134 asm volatile ("mov r1,#0x71;" \
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135 "mcr p15,0,r1,c1,c0,0;" \
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136 "mov r1,#0;" \
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137 "mcr p15,0,r1,c8,c7,0;" /* flush I+D TLBs */ \
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138 "nop; nop; nop; nop; nop;" \
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139 : \
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140 : \
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141 : "r1" /* Clobber list */ \
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142 ); \
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143 }
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144 #endif
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145
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146 // Is the cache turned on?
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147 #define HAL_UCACHE_IS_ENABLED(_state_) _state_ = 1;
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148
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149 // Invalidate the entire cache
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150 // mcr MMU_CP,0,r1,MMU_InvalidateCache,c0
143
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151 #define HAL_UCACHE_INVALIDATE_ALL() \
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152 { \
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153 asm volatile ( \
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154 "mov r1,#0;" \
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155 "mcr p15,0,r1,c7,c7,0;" \
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156 : \
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157 : \
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158 : "r1","memory" /* Clobber list */ \
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159 ); \
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160 \
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161 }
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162
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163 // Synchronize the contents of the cache with memory.
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164 #define HAL_UCACHE_SYNC() \
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165 { \
143
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166 cyg_uint32 *RAM = (cyg_uint32 *)0x00000000; \
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167 int i; \
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168 volatile cyg_uint32 val; \
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169 for (i = 0; i < HAL_UCACHE_SETS; i++) { \
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170 val = *RAM; \
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171 RAM += HAL_UCACHE_LINE_SIZE; \
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172 } \
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173 }
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174
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175 // Purge contents of data cache
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176 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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177
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178 // Set the data cache refill burst size
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179 //#define HAL_UCACHE_BURST_SIZE(_size_)
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180
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181 // Set the data cache write mode
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182 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
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183
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184 //#define HAL_UCACHE_WRITETHRU_MODE 0
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185 //#define HAL_UCACHE_WRITEBACK_MODE 1
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186
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187 // Load the contents of the given address range into the data cache
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188 // and then lock the cache so that it stays there.
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189 //#define HAL_UCACHE_LOCK(_base_, _size_)
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190
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191 // Undo a previous lock operation
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192 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
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193
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194 // Unlock entire cache
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195 //#define HAL_UCACHE_UNLOCK_ALL()
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196
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197 //-----------------------------------------------------------------------------
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198 // Data cache line control
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199
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200 // Allocate cache lines for the given address range without reading its
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201 // contents from memory.
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202 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
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203
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204 // Write dirty cache lines to memory and invalidate the cache entries
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205 // for the given address range.
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206 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_SYNC()
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207
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208 // Invalidate cache lines in the given range without writing to memory.
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209 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
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210
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211 // Write dirty cache lines to memory for the given address range.
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212 #define HAL_UCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_SYNC()
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213
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214 // Preread the given range into the cache with the intention of reading
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215 // from it later.
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216 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
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217
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218 // Preread the given range into the cache with the intention of writing
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219 // to it later.
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220 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
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221
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222 // Allocate and zero the cache lines associated with the given range.
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223 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
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224
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225 //-----------------------------------------------------------------------------
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226 // Global control of data cache
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227
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228 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
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229 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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230 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
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231 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
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232
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233 // Enable the data cache
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234 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
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235
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236 // Disable the data cache
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237 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
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238
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239 // Invalidate the entire cache
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240 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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241
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242 // Synchronize the contents of the cache with memory.
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243 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
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244
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245 // Query the state of the data cache
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246 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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247
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248 // Set the data cache refill burst size
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249 //#define HAL_DCACHE_BURST_SIZE(_size_)
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250
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251 // Set the data cache write mode
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252 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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253
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254 //#define HAL_DCACHE_WRITETHRU_MODE 0
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255 //#define HAL_DCACHE_WRITEBACK_MODE 1
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256
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257 // Load the contents of the given address range into the data cache
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258 // and then lock the cache so that it stays there.
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259 //#define HAL_DCACHE_LOCK(_base_, _size_)
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260
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261 // Undo a previous lock operation
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262 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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263
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264 // Unlock entire cache
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265 //#define HAL_DCACHE_UNLOCK_ALL()
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266
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267 //-----------------------------------------------------------------------------
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268 // Data cache line control
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269
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270 // Allocate cache lines for the given address range without reading its
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271 // contents from memory.
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272 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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273
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274 // Write dirty cache lines to memory and invalidate the cache entries
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275 // for the given address range.
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276 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_ , _size_ )
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277
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278 // Invalidate cache lines in the given range without writing to memory.
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279 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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280
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281 // Write dirty cache lines to memory for the given address range.
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282 #define HAL_DCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_STORE( _base_ , _size_ )
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283
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284 // Preread the given range into the cache with the intention of reading
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285 // from it later.
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286 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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287
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288 // Preread the given range into the cache with the intention of writing
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289 // to it later.
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290 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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291
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292 // Allocate and zero the cache lines associated with the given range.
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293 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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294
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295 //-----------------------------------------------------------------------------
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296 // Global control of Instruction cache - use Data cache controls since they
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297 // are not separatable.
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298
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299 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
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300 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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301 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
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302 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
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303
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304 // Enable the instruction cache
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305 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
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306
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307 // Disable the instruction cache
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308 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
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309
159
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310 // Is the cache turned on?
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311 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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312
54
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313 // Invalidate the entire cache
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314 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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315
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316 // Synchronize the contents of the cache with memory.
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317 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
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318
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319 // Set the instruction cache refill burst size
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320 //#define HAL_ICACHE_BURST_SIZE(_size_)
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321
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322 // Load the contents of the given address range into the instruction cache
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323 // and then lock the cache so that it stays there.
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324 //#define HAL_ICACHE_LOCK(_base_, _size_)
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325
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326 // Undo a previous lock operation
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327 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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328
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329 // Unlock entire cache
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330 //#define HAL_ICACHE_UNLOCK_ALL()
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331
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332 //-----------------------------------------------------------------------------
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333 // Instruction cache line control
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334
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335 // Invalidate cache lines in the given range without writing to memory.
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336 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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337
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338 //-----------------------------------------------------------------------------
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339 #endif // ifndef CYGONCE_HAL_CACHE_H
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340 // End of hal_cache.h