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annotate packages/hal/calmrisc16/arch/current/include/hal_cache.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors: nickg
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47 // Date: 1998-02-17
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48 // Purpose: Cache control API
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // cache control operations.
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51 // Usage:
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52 // #include <cyg/hal/hal_cache.h>
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53 // ...
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54 //
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //=============================================================================
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59
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60 #include <pkgconf/hal.h>
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61 #include <cyg/infra/cyg_type.h>
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62
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63 #include <cyg/hal/var_cache.h>
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64
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65
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66 //-----------------------------------------------------------------------------
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67 // Cache dimensions.
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68 // These really should be defined in var_cache.h. If they are not, then provide
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69 // a set of numbers that are typical of many variants.
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70
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71 #ifndef HAL_DCACHE_SIZE
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72
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73 // Data cache
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74 //#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes
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75 //#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line
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76 //#define HAL_DCACHE_WAYS 0 // Associativity of the cache
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77
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78 // Instruction cache
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79 //#define HAL_ICACHE_SIZE 0 // Size of cache in bytes
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80 //#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line
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81 //#define HAL_ICACHE_WAYS 0 // Associativity of the cache
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82
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83 //#define HAL_DCACHE_SETS 0
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84 //#define HAL_ICACHE_SETS 0
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85
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86 #endif
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87
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88 //-----------------------------------------------------------------------------
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89 // Global control of data cache
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90
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91 // Enable the data cache
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92 // There is no default mechanism for enabling or disabling the caches.
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93 #ifndef HAL_DCACHE_ENABLE_DEFINED
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94 #define HAL_DCACHE_ENABLE()
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95 #endif
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96
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97 // Disable the data cache
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98 #ifndef HAL_DCACHE_DISABLE_DEFINED
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99 #define HAL_DCACHE_DISABLE()
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100 #endif
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101
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102 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
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103 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
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104 #endif
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105
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106 // Invalidate the entire cache
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107 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
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108 // is not quite what we want, but there is no index-invalidate operation
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109 // available.
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110 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
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111 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
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112 #endif
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113
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114 // Synchronize the contents of the cache with memory.
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115 // This uses the index-writeback-invalidate operation.
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116 #ifndef HAL_DCACHE_SYNC_DEFINED
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117 #define HAL_DCACHE_SYNC() \
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118 CYG_MACRO_START \
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119 CYG_MACRO_END
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120 #endif
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121
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122 // Set the data cache refill burst size
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123 //#define HAL_DCACHE_BURST_SIZE(_size_)
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124
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125 // Set the data cache write mode
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126 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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127
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128 //#define HAL_DCACHE_WRITETHRU_MODE 0
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129 //#define HAL_DCACHE_WRITEBACK_MODE 1
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130
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131 // Load the contents of the given address range into the data cache
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132 // and then lock the cache so that it stays there.
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133 // This uses the fetch-and-lock cache operation.
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134 #ifndef HAL_DCACHE_LOCK_DEFINED
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135 #define HAL_DCACHE_LOCK(_base_, _asize_) \
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136 CYG_MACRO_START \
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137 CYG_MACRO_END
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138 #endif
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139
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140 // Undo a previous lock operation.
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141 // Do this by flushing the cache, which is defined to clear the lock bit.
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142 #ifndef HAL_DCACHE_UNLOCK_DEFINED
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143 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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144 HAL_DCACHE_FLUSH( _base_, _size_ )
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145 #endif
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146
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147 // Unlock entire cache
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148 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
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149 #define HAL_DCACHE_UNLOCK_ALL() \
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150 HAL_DCACHE_INVALIDATE_ALL()
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151 #endif
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152
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153 //-----------------------------------------------------------------------------
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154 // Data cache line control
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155
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156 // Allocate cache lines for the given address range without reading its
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157 // contents from memory.
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158 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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159
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160 // Write dirty cache lines to memory and invalidate the cache entries
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161 // for the given address range.
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162 // This uses the hit-writeback-invalidate cache operation.
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163 #ifndef HAL_DCACHE_FLUSH_DEFINED
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164 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
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165 CYG_MACRO_START \
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166 CYG_MACRO_END
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167 #endif
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168
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169 // Invalidate cache lines in the given range without writing to memory.
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170 // This uses the hit-invalidate cache operation.
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171 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
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172 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
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173 CYG_MACRO_START \
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174 CYG_MACRO_END
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175 #endif
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176
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177 // Write dirty cache lines to memory for the given address range.
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178 // This uses the hit-writeback cache operation.
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179 #ifndef HAL_DCACHE_STORE_DEFINED
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180 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
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181 CYG_MACRO_START \
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182 CYG_MACRO_END
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183 #endif
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184
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185 // Preread the given range into the cache with the intention of reading
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186 // from it later.
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187 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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188
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189 // Preread the given range into the cache with the intention of writing
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190 // to it later.
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191 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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192
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193 // Allocate and zero the cache lines associated with the given range.
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194 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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195
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196 //-----------------------------------------------------------------------------
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197 // Global control of Instruction cache
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198
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199 // Enable the instruction cache
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200 // There is no default mechanism for enabling or disabling the caches.
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201 #ifndef HAL_ICACHE_ENABLE_DEFINED
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202 #define HAL_ICACHE_ENABLE()
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203 #endif
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204
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205 // Disable the instruction cache
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206 #ifndef HAL_ICACHE_DISABLE_DEFINED
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207 #define HAL_ICACHE_DISABLE()
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208 #endif
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209
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210 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
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211 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
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212 #endif
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213
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214 // Invalidate the entire cache
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215 // This uses the index-invalidate cache operation.
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216 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
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217 #define HAL_ICACHE_INVALIDATE_ALL() \
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218 CYG_MACRO_START \
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219 CYG_MACRO_END
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220 #endif
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221
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222 // Synchronize the contents of the cache with memory.
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223 // Simply force the cache to reload.
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224 #ifndef HAL_ICACHE_SYNC_DEFINED
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225 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
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226 #endif
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227
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228 // Set the instruction cache refill burst size
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229 //#define HAL_ICACHE_BURST_SIZE(_size_)
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230
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231 // Load the contents of the given address range into the instruction cache
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232 // and then lock the cache so that it stays there.
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233 // This uses the fetch-and-lock cache operation.
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234 #ifndef HAL_ICACHE_LOCK_DEFINED
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235 #define HAL_ICACHE_LOCK(_base_, _asize_) \
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236 CYG_MACRO_START \
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237 CYG_MACRO_END
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238 #endif
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239
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240 // Undo a previous lock operation.
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241 // Do this by invalidating the cache, which is defined to clear the lock bit.
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242 #ifndef HAL_ICACHE_UNLOCK_DEFINED
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243 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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244 HAL_ICACHE_INVALIDATE( _base_, _size_ )
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245 #endif
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246
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247 // Unlock entire cache
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248 //#define HAL_ICACHE_UNLOCK_ALL()
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249
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250 //-----------------------------------------------------------------------------
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251 // Instruction cache line control
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252
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253 // Invalidate cache lines in the given range without writing to memory.
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254 // This uses the hit-invalidate cache operation.
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255 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
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256 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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257 CYG_MACRO_START \
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258 CYG_MACRO_END
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259 #endif
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260
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261
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262 //-----------------------------------------------------------------------------
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263 #endif // ifndef CYGONCE_HAL_CACHE_H
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264 // End of hal_cache.h