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annotate packages/hal/sparclite/sleb/current/include/halboot.si @ 2729:74dbf4c3f2e1 after-copyright-change-20090129
Update all copyright banners to reflect FSF ownership; fix and improve licence text.
| author | jlarmour |
|---|---|
| date | Thu, 29 Jan 2009 17:47:46 +0000 |
| parents | d2c90368aeef |
| children |
| rev | line source |
|---|---|
| 2 | 1 #ifndef CYGONCE_HAL_HALBOOT_SI /* -*-asm-*- */ |
| 2 #define CYGONCE_HAL_HALBOOT_SI | |
| 3 // ==================================================================== | |
| 4 // | |
| 5 // <platform>/halboot.si | |
| 6 // | |
| 7 // HAL bootup platform-oriented code (assembler) | |
| 8 // | |
| 9 // ==================================================================== | |
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10 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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11 // ------------------------------------------- |
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12 // This file is part of eCos, the Embedded Configurable Operating System. |
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
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14 // |
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15 // eCos is free software; you can redistribute it and/or modify it under |
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16 // the terms of the GNU General Public License as published by the Free |
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17 // Software Foundation; either version 2 or (at your option) any later |
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18 // version. |
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19 // |
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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21 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 // for more details. |
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24 // |
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25 // You should have received a copy of the GNU General Public License |
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26 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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27 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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28 // |
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29 // As a special exception, if other files instantiate templates or use |
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30 // macros or inline functions from this file, or you compile this file |
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31 // and link it with other works to produce a work based on this file, |
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32 // this file does not by itself cause the resulting work to be covered by |
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33 // the GNU General Public License. However the source code for this file |
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34 // must still be made available in accordance with section (3) of the GNU |
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35 // General Public License v2. |
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36 // |
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37 // This exception does not invalidate any other reasons why a work based |
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38 // on this file might be covered by the GNU General Public License. |
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39 // ------------------------------------------- |
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40 // ####ECOSGPLCOPYRIGHTEND#### |
| 2 | 41 // ==================================================================== |
| 42 //#####DESCRIPTIONBEGIN#### | |
| 43 // | |
| 44 // Author(s): hmt | |
| 45 // Contributors: hmt | |
| 46 // Date: 1999-02-01 | |
| 47 // Purpose: Bootup code, platform oriented. | |
| 48 // Description: | |
| 49 // | |
| 50 //####DESCRIPTIONEND#### | |
| 51 // | |
| 52 // ==================================================================== | |
| 53 | |
| 54 // External Platform Initial Setup | |
| 55 // | |
| 56 // This should set up RAM and caches, and calm down any external | |
| 57 // interrupt sources. | |
| 58 // | |
| 59 // It is just plain included in vectors.S | |
| 60 // | |
| 61 // RAM has not yet been touched at all; in fact all you have is a | |
| 62 // register window selected. | |
| 63 | |
| 64 | |
| 65 #ifdef CYG_HAL_STARTUP_RAM | |
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66 ! Hit the entry point instructions in situ |
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67 #ifndef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM |
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68 ! *unless* we are going to copy into a different RAM area anyway: |
| 2 | 69 ! copy the real instructions into the vector: |
| 70 rd %tbr, %g1 | |
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71 andn %g1, 0xfff, %g1 ! clear non-address bits |
| 2 | 72 set real_vector_instructions, %l0 |
| 73 ld [ %l0 ], %l1 | |
| 74 st %l1, [ %g1 ] ! into the vector | |
| 75 ld [ %l0 + 4 ], %l1 | |
| 76 st %l1, [ %g1 + 4 ] ! into the vector | |
| 77 ! then invalidate the instruction cache: | |
| 78 set 3, %l0 | |
| 79 set 0x00001000, %l1 | |
| 80 set 0x80001000, %l2 | |
| 81 sta %l0, [ %l1 ] 0x0c | |
| 82 sta %l0, [ %l2 ] 0x0c | |
| 83 ! and the data cache | |
| 84 sta %l0, [ %l1 ] 0x0e | |
| 85 sta %l0, [ %l2 ] 0x0e | |
| 86 nop | |
| 87 nop | |
| 88 nop | |
| 89 nop ! should be enough | |
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90 #endif // !CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM |
| 2 | 91 #endif // CYG_HAL_STARTUP_RAM |
| 92 | |
| 93 | |
| 94 #include <cyg/hal/hal_cpu.h> // a copy of CygMon~s cpu.h | |
| 95 | |
| 96 | |
| 97 /* Address of clock switch */ | |
| 98 #define CLKSW_ADDR 0x01000003 | |
| 99 | |
| 100 /* Address of SW1 */ | |
| 101 #define SW1_ADDR 0x02000003 | |
| 102 | |
| 103 /* Address of LED bank */ | |
| 104 #define LED_ADDR 0x02000003 | |
| 105 | |
| 106 #define SRAM_BASE 0x30000000 | |
| 107 #define SRAM_END 0x30080000 | |
| 108 | |
| 109 | |
| 110 #define DRAM_BASE 0x04000000 /* base of system DRAM */ | |
| 111 #define CS3_BASE 0x00000000 /* base of internal resource regs */ | |
| 112 #define CS3_ASI 7 /* ASI of internal resource regs */ | |
| 113 | |
| 114 // DRAM_BASE2 is defined so that we run the same RAM-sizing code in both | |
| 115 // RAM and ROM startup versions; but the RAM startup one starts RAM sizing | |
| 116 // at 0x043ff000 ie. 4k down from the top of the 4M available. | |
| 117 | |
| 118 #ifdef CYG_HAL_STARTUP_RAM | |
| 119 #define DRAM_BASE2 DRAM_BASE + 0x00400000 - 0x1000 | |
| 120 #else | |
| 121 #define DRAM_BASE2 DRAM_BASE | |
| 122 #endif | |
| 123 | |
| 124 .macro led val | |
| 125 sethi %hi(LED_ADDR),%l7 | |
| 126 set \val,%l6 | |
| 127 not %l6, %l6 | |
| 128 stb %l6,[%l7 + %lo(LED_ADDR)] | |
| 129 .endm | |
| 130 | |
| 131 /* | |
| 132 * First, setup chip selects. | |
| 133 * | |
| 134 * NB: The AMR_VAL macro actually inverts the mask bits. For me, it is | |
| 135 * more natural to write a 1 bit where I want the address compared. | |
| 136 * The sparc registers use 0 bits, instead. | |
| 137 */ | |
| 138 | |
| 139 /* -CS0 ADDR_MASK:0xfc000000 ASI_MASK:0xfc */ | |
| 140 set AMR_VAL(0xfc,0xfc000000),%l0 | |
| 141 mov AMR0,%l1 | |
| 142 sta %l0,[%l1] 1 | |
| 143 | |
| 144 /* -CS1 BASE:0x10000000 ASI:4 */ | |
| 145 set ARSR_VAL(4,0x10000000),%l0 | |
| 146 mov ARSR1,%l1 | |
| 147 sta %l0,[%l1] 1 | |
| 148 /* -CS1 ADDR MASK:0xf0000000 ASI MASK:0x7 */ | |
| 149 set AMR_VAL(7,0xf0000000),%l0 | |
| 150 mov AMR1,%l1 | |
| 151 sta %l0,[%l1] 1 | |
| 152 | |
| 153 /* -CS2 BASE:0x20000000 ASI:4 */ | |
| 154 set ARSR_VAL(4,0x20000000), %l0 | |
| 155 mov ARSR2,%l1 | |
| 156 sta %l0,[%l1] 1 | |
| 157 /* -CS2 ADDR MASK:0xf0000000 ASI MASK:0x7 */ | |
| 158 set AMR_VAL(7,0xf0000000),%l0 | |
| 159 mov AMR2,%l1 | |
| 160 sta %l0,[%l1] 1 | |
| 161 | |
| 162 /* -CS3 BASE:CS3_BASE ASI:CS3_ASI */ | |
| 163 set ARSR_VAL(CS3_ASI,CS3_BASE),%l0 | |
| 164 mov ARSR3,%l1 | |
| 165 sta %l0,[%l1] 1 | |
| 166 /* -CS3 ADDR MASK:0xffff0000 ASI MASK:0x7 */ | |
| 167 set AMR_VAL(7,0xffff0000),%l0 | |
| 168 mov AMR3,%l1 | |
| 169 sta %l0,[%l1] 1 | |
| 170 | |
| 171 /* -CS4 BASE: DRAM_BASE ASI:0xb */ | |
| 172 set ARSR_VAL(0xb,DRAM_BASE),%l0 | |
| 173 mov ARSR4,%l1 | |
| 174 sta %l0,[%l1] 1 | |
| 175 /* -CS4 ADDR MASK:0xfc000000 ASI MASK:0xfc */ | |
| 176 set AMR_VAL(0xfc,0xfc000000),%l0 | |
| 177 mov AMR4,%l1 | |
| 178 sta %l0,[%l1] 1 | |
| 179 | |
| 180 /* -CS5 BASE:0x30000000 ASI:0xb */ | |
| 181 set ARSR_VAL(0xb,0x30000000),%l0 | |
| 182 mov ARSR5,%l1 | |
| 183 sta %l0,[%l1] 1 | |
| 184 /* -CS5 ADDR MASK:0xfff80000 ASI MASK:0xfc */ | |
| 185 set AMR_VAL(0xfc,0xfff80000),%l0 | |
| 186 mov AMR5,%l1 | |
| 187 sta %l0,[%l1] 1 | |
| 188 | |
| 189 | |
| 190 /* | |
| 191 * Setup wait states. Each wait state register sets the wait states for | |
| 192 * a pair of chip selects. The lower bits hold the wait state info for | |
| 193 * the lower numbered chip select. | |
| 194 */ | |
| 195 | |
| 196 /* -CS0: 5 wait states, -CS1: 7 wait states */ | |
| 197 // set WSSR_VAL(7,7,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 | |
| 198 // set WSSR_VAL(4,4,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 // FOUR -> CS1 | |
| 199 set WSSR_VAL(10,10,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 // TEN -> CS1 | |
| 200 mov WSSR0,%l1 | |
| 201 sta %l0,[%l1] 1 | |
| 202 | |
| 203 /* -CS2: wait states disabled, -CS3: wait states disabled */ | |
| 204 set WSSR_VAL(0,0,0,0,0,0),%l0 | |
| 205 mov WSSR1,%l1 | |
| 206 sta %l0,[%l1] 1 | |
| 207 | |
| 208 /* -CS4: wait states disabled, -CS5: 0 wait states */ | |
| 209 set WSSR_VAL(0,0,WSSR_WAITEN|WSSR_OVERRIDE,0,0,0),%l0 | |
| 210 mov WSSR2,%l1 | |
| 211 sta %l0,[%l1] 1 | |
| 212 | |
| 213 led 0x10 | |
| 214 | |
| 215 /* clear cache/BIU control register */ | |
| 216 mov CBIR,%l1 | |
| 217 sta %g0,[%l1] 1 | |
| 218 | |
| 219 /* Read clock switch to determine the value of the refresh timer */ | |
| 220 sethi %hi(CLKSW_ADDR),%l1 | |
| 221 ldub [%l1 + %lo(CLKSW_ADDR)],%l0 | |
| 222 btst 0x80,%l0 | |
| 223 bne,a 1f | |
| 224 mov 10,%l0 /* force to 10MHz if CLKSW-8 is ON */ | |
| 225 1: | |
| 226 umul %l0,15,%l0 | |
| 227 mov DRLD,%l1 | |
| 228 sta %l0,[%l1] 1 | |
| 229 mov REFTMR,%l1 | |
| 230 sta %l0,[%l1] 1 | |
| 231 | |
| 232 /* read SW1 to get DRAM page size */ | |
| 233 sethi %hi(SW1_ADDR),%l1 | |
| 234 ldub [%l1 + %lo(SW1_ADDR)],%l0 | |
| 235 btst 0x10,%l0 | |
| 236 be,a 1f | |
| 237 mov 0x0e,%l0 /* 1K page if branch taken (SW1-5 is OFF) */ | |
| 238 mov 0x06,%l0 /* 2K page (SW1-5 is OFF) */ | |
| 239 1: | |
| 240 mov SPGMR,%l1 | |
| 241 sta %l0,[%l1] 1 | |
| 242 | |
| 243 led 0x20 | |
| 244 | |
| 245 #ifdef CYG_HAL_STARTUP_ROM | |
| 246 /* Turn on all system services */ | |
| 247 mov SSCR_TIMER|SSCR_WAIT|SSCR_CS|SSCR_SAMEPG,%l0 | |
| 248 mov SSCR,%l1 | |
| 249 sta %l0,[%l1] 1 | |
| 250 nop | |
| 251 nop | |
| 252 nop | |
| 253 nop | |
| 254 | |
| 255 #endif | |
| 256 | |
| 257 led 0x30 | |
| 258 | |
| 259 /* | |
| 260 * Initialize caches. | |
| 261 */ | |
| 262 sethi %hi(0x1000),%l0 /* bank 1 invalidate */ | |
| 263 sethi %hi(0x80000000),%l1 /* bank 2 invalidate */ | |
| 264 mov 3,%l2 /* clear lock, lru, and valid bits */ | |
| 265 sta %l2,[%l0] 0xc /* do it - icache bank 1 */ | |
| 266 sta %l2,[%l0] 0xe /* do it - dcache bank 1 */ | |
| 267 sta %l2,[%l0 + %l1] 0xc /* do it - icache bank 2 */ | |
| 268 sta %l2,[%l0 + %l1] 0xe /* do it - dcache bank 2 */ | |
| 269 | |
| 270 /* now, enable caches and buffers */ | |
| 271 mov CBIR_ICEN|CBIR_DCEN|CBIR_PBEN|CBIR_WBEN,%l0 | |
| 272 mov CBIR,%l1 | |
| 273 sta %l0,[%l1] 1 | |
| 274 nop | |
| 275 nop | |
| 276 nop | |
| 277 nop | |
| 278 | |
| 279 /* enable data and insn bursts */ | |
| 280 mov BCR_IBE|BCR_DBE,%l0 | |
| 281 mov BCR,%l1 | |
| 282 sta %l0,[%l1] 1 | |
| 283 nop | |
| 284 nop | |
| 285 nop | |
| 286 nop | |
| 287 | |
| 288 /* | |
| 289 * DRAM setup/test. | |
| 290 */ | |
| 291 led 0x40 | |
| 292 | |
| 293 /* | |
| 294 * Test SW1-7 to determine normal or EDO mode. | |
| 295 * SW1-7 ON = EDO | |
| 296 * SW1-7 OFF = Normal. | |
| 297 */ | |
| 298 sethi %hi(SW1_ADDR),%l1 | |
| 299 ldub [%l1 + %lo(SW1_ADDR)],%l7 | |
| 300 mov DBANKR_SA04,%l0 /* DRAM starts at 0x04000000 */ | |
| 301 btst 0x40,%l7 | |
| 302 bne 1f /* branch if SW1-7 is OFF */ | |
| 303 mov SSCR_DRAM,%l1 | |
| 304 /* EDO DRAM, enable burst in SSCR and EDO in DBANKR */ | |
| 305 or %l1,SSCR_BURST,%l1 | |
| 306 or %l0,DBANKR_EDO,%l0 | |
| 307 1: | |
| 308 /* | |
| 309 * Now, test SW1 to get DRAM page and bank size. | |
| 310 * SW1-5 ON = 2k page, 16MB bank. (up to 64MB total) | |
| 311 * SW1-5 OFF = 1k page, 4MB bank. (up to 16MB total) | |
| 312 */ | |
| 313 btst 0x10,%l7 | |
| 314 bne,a 1f /* branch if OFF */ | |
| 315 or %l0,DBANKR_4M|DBANKR_CA10,%l0 /* 1K page */ | |
| 316 or %l0,DBANKR_16M|DBANKR_CA11,%l0 /* 2K page */ | |
| 317 1: | |
| 318 mov CS3_BASE+DBANKR,%l2 | |
| 319 sta %l0,[%l2] CS3_ASI | |
| 320 | |
| 321 mov DTIMR_RPS2|DTIMR_CBR3|DTIMR_CAS2|DTIMR_RP2,%l0 | |
| 322 mov CS3_BASE+DTIMR,%l2 | |
| 323 sta %l0,[%l2] CS3_ASI | |
| 324 | |
| 325 mov SSCR,%l2 | |
| 326 lda [%l2] 1, %l0 | |
| 327 or %l0,%l1,%l0 | |
| 328 sta %l0,[%l2] 1 | |
| 329 | |
| 330 /* | |
| 331 * Test SW1 to get potential DRAM limit. | |
| 332 * SW1-5 ON = 2k page, up to 64MB total | |
| 333 * SW1-5 OFF = 1k page, up to 16MB total | |
| 334 */ | |
| 335 btst 0x10,%l7 | |
| 336 bne,a 1f /* branch if OFF */ | |
| 337 sethi %hi(DRAM_BASE + 16*1024*1024),%l0 | |
| 338 sethi %hi(DRAM_BASE + 64*1024*1024),%l0 | |
| 339 1: | |
| 340 | |
| 341 /* subtract 4 to get last valid DRAM address */ | |
| 342 add %l0,-4,%l0 | |
| 343 | |
| 344 /* Assume maximim memory and fill with pattern */ | |
| 345 set DRAM_BASE2,%l2 | |
| 346 set 0xaaaaaaaa,%l3 | |
| 347 1: | |
| 348 st %l3,[%l2] | |
| 349 cmp %l2,%l0 | |
| 350 blt 1b | |
| 351 add %l2,4,%l2 | |
| 352 | |
| 353 /* | |
| 354 * Go back, read data and compare with written data. | |
| 355 * Fill in with zero as we go along. | |
| 356 */ | |
| 357 set DRAM_BASE2,%l2 | |
| 358 1: | |
| 359 ld [%l2],%l4 | |
| 360 cmp %l4,%l3 | |
| 361 bne 2f | |
| 362 st %g0,[%l2] | |
| 363 cmp %l2,%l0 | |
| 364 blt,a 1b | |
| 365 add %l2,4,%l2 | |
| 366 2: | |
| 367 led 0x50 | |
| 368 | |
| 369 sub %l2,64,%i6 | |
| 370 sethi %hi(DRAM_BASE),%l1 | |
| 371 sub %l2,%l1,%l0 | |
| 372 st %l0,[%i6] | |
| 373 | |
| 374 // NOTE that here, the frame pointer is set up to the top of RAM minus a | |
| 375 // little bit with the size of RAM at %fp (%i6) | |
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376 #ifdef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM |
| 2 | 377 |
| 378 led 0x58 | |
| 379 | |
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380 ! copy the trampoline code into the base of RAM (__ram_vectors_start) |
| 2 | 381 ! including the two ~rogue~ instructions... |
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382 |
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383 .extern __ram_vectors_start |
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797268ecc331
Merge from eCos master repository on 1999-10-19-18:55:31-BST
jlarmour
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384 ! Using the true address here for the copy makes a badly-aligned |
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797268ecc331
Merge from eCos master repository on 1999-10-19-18:55:31-BST
jlarmour
parents:
2
diff
changeset
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385 ! __ram_vectors less likely to hide as an obscure failure: |
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797268ecc331
Merge from eCos master repository on 1999-10-19-18:55:31-BST
jlarmour
parents:
2
diff
changeset
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386 set __ram_vectors_start, %l0 ! get the start of RAM |
| 2 | 387 set rom_vectors, %l1 ! get the start of the trampoline |
| 388 set rom_vectors_end, %l2 ! ...and its end. | |
| 389 33: | |
| 390 ldd [ %l1 ], %l4 ! also uses %l5 | |
| 391 std %l4, [ %l0 ] | |
| 392 inc 8, %l1 | |
| 393 inc 8, %l0 | |
| 394 cmp %l1, %l2 | |
| 395 bl 33b | |
| 396 nop | |
| 397 | |
| 398 led 0x59 | |
| 399 | |
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797268ecc331
Merge from eCos master repository on 1999-10-19-18:55:31-BST
jlarmour
parents:
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diff
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400 sethi %hi(__ram_vectors_start), %g1 ! get the start of RAM |
| 2 | 401 andn %g1, 0xfff, %g1 |
| 402 set real_vector_instructions, %l0 | |
| 403 ld [ %l0 ], %l1 | |
| 404 st %l1, [ %g1 ] ! into the vector | |
| 405 ld [ %l0 + 4 ], %l1 | |
| 406 st %l1, [ %g1 + 4 ] ! into the vector | |
| 407 | |
| 408 led 0x5a | |
| 409 | |
| 410 ! then invalidate the instruction cache: | |
| 411 set 3, %l0 | |
| 412 set 0x00001000, %l1 | |
| 413 set 0x80001000, %l2 | |
| 414 sta %l0, [ %l1 ] 0x0c | |
| 415 sta %l0, [ %l2 ] 0x0c | |
| 416 | |
| 417 led 0x5b | |
| 418 | |
| 419 ! and the data cache | |
| 420 sta %l0, [ %l1 ] 0x0e | |
| 421 sta %l0, [ %l2 ] 0x0e | |
| 422 nop | |
| 423 nop | |
| 424 nop | |
| 425 nop ! should be enough | |
| 426 | |
| 427 led 0x5c | |
| 428 | |
| 429 ! and (re)set the tbr, finally. | |
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797268ecc331
Merge from eCos master repository on 1999-10-19-18:55:31-BST
jlarmour
parents:
2
diff
changeset
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430 sethi %hi(__ram_vectors_start), %g1 |
| 2 | 431 andn %g1, 0xfff, %g1 |
| 432 wr %g1, %tbr ! Traps are at RAM start | |
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797268ecc331
Merge from eCos master repository on 1999-10-19-18:55:31-BST
jlarmour
parents:
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433 nop ! (__ram_vectors_start) |
| 2 | 434 nop |
| 435 nop | |
| 436 | |
| 437 led 0x5d | |
| 438 | |
| 439 #else | |
| 440 | |
| 441 led 0x5f | |
| 442 | |
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797268ecc331
Merge from eCos master repository on 1999-10-19-18:55:31-BST
jlarmour
parents:
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diff
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443 #endif // CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM (was CYG_HAL_STARTUP_ROM) |
| 2 | 444 |
| 445 ! turn on caches - copied from the book | |
| 446 #define set_size 64 | |
| 447 #define ini_tag 0 | |
| 448 #define adr1 0x00000000 | |
| 449 #define adr2 0x80000000 | |
| 450 #define step 16 | |
| 451 #define CTL_BITS 0x35 | |
| 452 | |
| 453 set set_size, %l7 | |
| 454 set adr1, %o1 | |
| 455 set adr2, %o2 | |
| 456 set ini_tag, %l0 | |
| 457 10: | |
| 458 sta %l0, [ %o1 ] 0x0c | |
| 459 sta %l0, [ %o1 ] 0x0e | |
| 460 sta %l0, [ %o2 ] 0x0c | |
| 461 sta %l0, [ %o2 ] 0x0e | |
| 462 add %o1, step, %o1 | |
| 463 subcc %l7, 1, %l7 | |
| 464 bne 10b | |
| 465 add %o2, step, %o2 | |
| 466 | |
| 467 set 0, %l1 | |
| 468 set CTL_BITS, %l2 | |
| 469 sta %l2, [ %l1 ] 0x01 | |
| 470 nop | |
| 471 nop | |
| 472 nop | |
| 473 nop ! delay to let caches stabilize | |
| 474 | |
| 475 led 0x60 | |
| 476 | |
| 477 // Now set up the 86940 | |
| 478 | |
| 479 #define TRGM0 0 | |
| 480 #define TRGM1 4 | |
| 481 #define REQSNS 8 | |
| 482 #define REQCLR 12 | |
| 483 #define IMASK 16 | |
| 484 #define IRLAT 20 | |
| 485 #define IMODE 24 | |
| 486 | |
| 487 sethi %hi( 0x10000000 ), %l1 ! base address of the 86940 companion | |
| 488 | |
| 489 set 0xfffe0000, %l4 ! mask all intrs | |
| 490 add %l1, IMASK, %l3 | |
| 491 sta %l4, [ %l3 ] 4 | |
| 492 | |
| 493 set 0x11400000, %l6 ! Channels 14,12,11 into Active Low | |
| 494 add %l1, TRGM0, %l3 | |
| 495 sta %l6, [ %l3 ] 4 | |
| 496 | |
| 497 set 0x05100000, %l6 ! Channels 5,4,2 into Active Low | |
| 498 add %l1, TRGM1, %l3 | |
| 499 sta %l6, [ %l3 ] 4 | |
| 500 | |
| 501 add %l1, REQCLR, %l3 ! clear all pending intrs | |
| 502 sta %l4, [ %l3 ] 4 | |
| 503 | |
| 504 set 0x00100000, %l6 ! clear the latch | |
| 505 add %l1, IRLAT, %l3 | |
| 506 sta %l6, [ %l3 ] 4 | |
| 507 | |
| 508 nop | |
| 509 nop | |
| 510 nop | |
| 511 | |
| 512 led 0x70 | |
| 513 | |
| 514 #endif /* CYGONCE_HAL_HALBOOT_SI */ | |
| 515 /* EOF halboot.si */ |