Mercurial > ecos
annotate packages/kernel/current/src/intr/intr.cxx @ 103:95f3e12a6327 ecos-sw-2000-06-23
Merge from eCos master repository on 2000-06-23-16:41:10-BST
| author | jlarmour |
|---|---|
| date | Fri, 23 Jun 2000 17:06:31 +0000 |
| parents | 6512add4f5d6 |
| children | 0c2b7be0d798 |
| rev | line source |
|---|---|
| 0 | 1 //========================================================================== |
| 2 // | |
| 2 | 3 // intr/intr.cxx |
| 0 | 4 // |
| 2 | 5 // Interrupt class implementations |
| 0 | 6 // |
| 7 //========================================================================== | |
| 8 //####COPYRIGHTBEGIN#### | |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
9 // |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
10 // ------------------------------------------- |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
11 // The contents of this file are subject to the Red Hat eCos Public License |
|
66
bf00f99aec69
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
jlarmour
parents:
64
diff
changeset
|
12 // Version 1.1 (the "License"); you may not use this file except in |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
13 // compliance with the License. You may obtain a copy of the License at |
|
66
bf00f99aec69
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
jlarmour
parents:
64
diff
changeset
|
14 // http://www.redhat.com/ |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
15 // |
|
66
bf00f99aec69
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
jlarmour
parents:
64
diff
changeset
|
16 // Software distributed under the License is distributed on an "AS IS" |
|
64
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
18 // License for the specific language governing rights and limitations under |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
19 // the License. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
20 // |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
21 // The Original Code is eCos - Embedded Configurable Operating System, |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
22 // released September 30, 1998. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
23 // |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
24 // The Initial Developer of the Original Code is Red Hat. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
25 // Portions created by Red Hat are |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
27 // All Rights Reserved. |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
28 // ------------------------------------------- |
|
c38311975d4f
Merge from eCos master repository on 2000-01-28-04:28:11-GMT
jlarmour
parents:
38
diff
changeset
|
29 // |
| 0 | 30 //####COPYRIGHTEND#### |
| 31 //========================================================================== | |
| 32 //#####DESCRIPTIONBEGIN#### | |
| 33 // | |
| 2 | 34 // Author(s): nickg |
| 35 // Contributors: nickg | |
| 36 // Date: 1999-02-17 | |
| 37 // Purpose: Interrupt class implementation | |
| 38 // Description: This file contains the definitions of the interrupt | |
| 39 // class. | |
| 0 | 40 // |
| 41 //####DESCRIPTIONEND#### | |
| 42 // | |
| 43 //========================================================================== | |
| 44 | |
| 45 #include <pkgconf/kernel.h> | |
| 46 | |
| 47 #include <cyg/kernel/ktypes.h> // base kernel types | |
| 48 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 49 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 50 #include <cyg/kernel/instrmnt.h> // instrumentation | |
| 51 | |
| 52 #include <cyg/kernel/intr.hxx> // our header | |
| 53 | |
| 54 #include <cyg/kernel/sched.hxx> // scheduler | |
| 55 | |
| 56 #include <cyg/kernel/sched.inl> | |
| 57 | |
| 58 // ------------------------------------------------------------------------- | |
| 2 | 59 // Statics |
| 60 | |
| 61 // Interrupt disable counter. Note that this is initialized to 1 since | |
| 62 // enable_interrupts() is called in Cyg_Scheduler::start(). | |
| 63 | |
| 64 cyg_int32 Cyg_Interrupt::disable_counter = 1; | |
| 65 | |
| 66 // ------------------------------------------------------------------------- | |
| 0 | 67 |
| 68 Cyg_Interrupt::Cyg_Interrupt( | |
| 69 cyg_vector vec, // Vector to attach to | |
| 70 cyg_priority pri, // Queue priority | |
| 71 CYG_ADDRWORD d, // Data pointer | |
| 72 cyg_ISR *ir, // Interrupt Service Routine | |
| 73 cyg_DSR *dr // Deferred Service Routine | |
| 74 ) | |
| 75 { | |
| 2 | 76 CYG_REPORT_FUNCTION(); |
| 77 CYG_REPORT_FUNCARG5("vector=%d, priority=%d, data=%08x, isr=%08x, " | |
| 78 "dsr=%08x", vec, pri, d, ir, dr); | |
| 79 | |
| 0 | 80 vector = vec; |
| 81 priority = pri; | |
| 82 isr = ir; | |
| 83 dsr = dr; | |
| 84 data = d; | |
| 85 | |
| 86 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 87 | |
| 88 dsr_count = 0; | |
| 89 next_dsr = NULL; | |
| 90 | |
| 91 #endif | |
| 92 | |
| 93 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 94 | |
| 95 next = NULL; | |
| 96 | |
| 97 #endif | |
| 2 | 98 |
| 99 CYG_REPORT_RETURN(); | |
| 0 | 100 |
| 101 }; | |
| 102 | |
| 103 // ------------------------------------------------------------------------- | |
| 104 | |
| 105 Cyg_Interrupt::~Cyg_Interrupt() | |
| 106 { | |
| 2 | 107 CYG_REPORT_FUNCTION(); |
| 0 | 108 detach(); |
| 2 | 109 CYG_REPORT_RETURN(); |
| 0 | 110 }; |
| 111 | |
| 112 // ------------------------------------------------------------------------- | |
| 113 // DSR handling statics: | |
| 114 | |
| 115 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 116 | |
| 2 | 117 Cyg_Interrupt * |
| 118 Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; | |
| 0 | 119 |
| 120 cyg_ucount32 Cyg_Interrupt::dsr_table_head = 0; | |
| 121 | |
| 122 cyg_ucount32 Cyg_Interrupt::dsr_table_tail = 0; | |
| 123 | |
| 124 #endif | |
| 125 | |
| 126 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 127 | |
| 128 Cyg_Interrupt *Cyg_Interrupt::dsr_list = NULL; | |
| 129 | |
| 130 #endif | |
| 131 | |
| 132 // ------------------------------------------------------------------------- | |
| 133 // Call any pending DSRs | |
| 134 | |
| 2 | 135 void |
| 136 Cyg_Interrupt::call_pending_DSRs_inner(void) | |
| 0 | 137 { |
| 138 // CYG_REPORT_FUNCTION(); | |
| 139 | |
| 140 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 141 | |
| 142 while( dsr_table_head != dsr_table_tail ) | |
| 143 { | |
| 144 Cyg_Interrupt *intr = dsr_table[dsr_table_head]; | |
| 145 | |
| 146 dsr_table_head++; | |
| 147 if( dsr_table_head >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 148 dsr_table_head = 0; | |
| 149 | |
| 150 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0); | |
| 151 | |
|
38
e7ba79f6d3a8
Merge from eCos master repository on 1999-09-23-20:10:25-BST
jlarmour
parents:
18
diff
changeset
|
152 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
|
e7ba79f6d3a8
Merge from eCos master repository on 1999-09-23-20:10:25-BST
jlarmour
parents:
18
diff
changeset
|
153 |
| 0 | 154 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data ); |
| 155 } | |
| 156 | |
| 157 #endif | |
| 158 | |
| 159 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 160 | |
| 161 while( dsr_list != NULL ) | |
| 162 { | |
| 163 Cyg_Interrupt *intr; | |
| 164 cyg_uint32 old_intr; | |
| 165 cyg_count32 count; | |
| 166 | |
| 167 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 168 | |
| 169 intr = dsr_list; | |
| 170 dsr_list = intr->next_dsr; | |
| 171 count = intr->dsr_count; | |
| 172 intr->dsr_count = 0; | |
| 173 | |
| 174 HAL_RESTORE_INTERRUPTS(old_intr); | |
|
38
e7ba79f6d3a8
Merge from eCos master repository on 1999-09-23-20:10:25-BST
jlarmour
parents:
18
diff
changeset
|
175 |
|
e7ba79f6d3a8
Merge from eCos master repository on 1999-09-23-20:10:25-BST
jlarmour
parents:
18
diff
changeset
|
176 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
| 0 | 177 |
| 178 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data ); | |
| 179 | |
| 180 } | |
| 181 | |
| 182 #endif | |
| 183 | |
| 184 }; | |
| 185 | |
| 2 | 186 externC void |
| 187 cyg_interrupt_call_pending_DSRs(void) | |
| 188 { | |
| 189 Cyg_Interrupt::call_pending_DSRs_inner(); | |
| 190 } | |
| 191 | |
|
8
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
192 // |
|
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
193 // Use HAL supported function to run through the DSRs, but executing using |
|
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
194 // the separate interrupt stack if available. This function calls back |
|
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
195 // into this module via 'cyg_interrupt_call_pending_DSRs' above, to keep |
|
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
196 // the whole process as general as possible. |
| 2 | 197 |
| 198 void | |
| 199 Cyg_Interrupt::call_pending_DSRs(void) | |
| 200 { | |
|
8
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
201 HAL_INTERRUPT_STACK_CALL_PENDING_DSRS(); |
| 2 | 202 } |
| 203 | |
| 204 | |
| 0 | 205 // ------------------------------------------------------------------------- |
| 206 | |
| 2 | 207 void |
| 208 Cyg_Interrupt::post_dsr(void) | |
| 0 | 209 { |
| 210 // CYG_REPORT_FUNCTION(); | |
| 211 | |
| 212 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0); | |
| 213 | |
| 214 cyg_uint32 old_intr; | |
| 215 | |
| 216 // We need to disable interrupts during this part to | |
| 217 // guard against nested interrupts. | |
| 218 | |
| 219 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 220 | |
| 221 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 222 | |
| 223 dsr_table[dsr_table_tail++] = this; | |
| 224 if( dsr_table_tail >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 225 dsr_table_tail = 0; | |
| 226 | |
| 227 #endif | |
| 228 | |
| 229 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 230 | |
| 231 // Only add the interrupt to the dsr list if this is | |
| 232 // the first DSR call. | |
| 233 // At present DSRs are pushed onto the list and will be | |
| 234 // called in reverse order. We do not define the order | |
| 235 // in which DSRs are called, so this is acceptable. | |
| 236 | |
| 237 if( dsr_count++ == 0 ) | |
| 238 { | |
| 239 next_dsr = dsr_list; | |
| 240 dsr_list = this; | |
| 241 } | |
| 242 | |
| 243 #endif | |
| 244 | |
| 245 HAL_RESTORE_INTERRUPTS(old_intr); | |
| 246 }; | |
| 247 | |
| 248 // ------------------------------------------------------------------------- | |
| 2 | 249 // A C callable interface to Cyg_Interrupt::post_dsr() that can be used from |
| 250 // the HAL. | |
| 0 | 251 |
| 2 | 252 externC void |
| 253 cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ) | |
| 254 { | |
| 255 Cyg_Interrupt* intr = (Cyg_Interrupt*) intr_obj; | |
| 256 intr->post_dsr (); | |
| 257 } | |
| 258 | |
| 259 // ------------------------------------------------------------------------- | |
| 260 | |
| 261 // FIXME: should have better name - Jifl | |
| 262 externC void | |
| 263 interrupt_end( | |
| 0 | 264 cyg_uint32 isr_ret, |
| 265 Cyg_Interrupt *intr, | |
| 266 HAL_SavedRegisters *regs | |
| 267 ) | |
| 268 { | |
| 269 // CYG_REPORT_FUNCTION(); | |
| 270 | |
| 2 | 271 // Sometimes we have a NULL intr object pointer. |
| 272 cyg_vector vector = (intr!=NULL)?intr->vector:0; | |
|
86
6512add4f5d6
Merge from eCos master repository on 2000-05-05-07:47:05-BST
jlarmour
parents:
66
diff
changeset
|
273 |
| 2 | 274 CYG_INSTRUMENT_INTR(END, vector, isr_ret); |
| 275 | |
|
86
6512add4f5d6
Merge from eCos master repository on 2000-05-05-07:47:05-BST
jlarmour
parents:
66
diff
changeset
|
276 CYG_UNUSED_PARAM( cyg_vector, vector ); // prevent compiler warning |
| 2 | 277 |
| 0 | 278 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
| 279 | |
| 280 // Only do this if we are in a non-chained configuration. | |
| 281 // If we are chained, then chain_isr below will do the DSR | |
| 282 // posting. | |
| 283 | |
| 2 | 284 if( isr_ret & Cyg_Interrupt::CALL_DSR && intr != NULL ) intr->post_dsr(); |
| 0 | 285 |
| 286 #endif | |
| 287 | |
| 288 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 289 | |
| 290 // If we have GDB support enabled, and there is the possibility | |
| 291 // that this thread will be context switched as a result of this | |
| 292 // interrupt, then save the pointer to the saved thread context in | |
| 293 // the thread object so that GDB can get a meaningful context to | |
| 294 // look at. | |
| 295 | |
| 296 Cyg_Scheduler::get_current_thread()->set_saved_context(regs); | |
| 297 | |
| 298 #endif | |
| 299 | |
| 300 // Now unlock the scheduler, which may also call DSRs | |
| 301 // and cause a thread switch to happen. | |
| 302 | |
| 303 Cyg_Scheduler::unlock(); | |
| 304 | |
| 305 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 306 | |
| 307 Cyg_Scheduler::get_current_thread()->set_saved_context(0); | |
| 308 | |
| 309 #endif | |
| 310 | |
| 2 | 311 CYG_INSTRUMENT_INTR(RESTORE, vector, 0); |
| 0 | 312 } |
| 313 | |
| 314 // ------------------------------------------------------------------------- | |
| 315 // Interrupt chaining statics. | |
| 316 | |
| 317 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 318 | |
| 2 | 319 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYGNUM_HAL_ISR_COUNT]; |
| 0 | 320 |
| 321 #endif | |
| 322 | |
| 323 // ------------------------------------------------------------------------- | |
| 324 // Chaining ISR inserted in HAL vector | |
| 325 | |
| 326 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 327 | |
| 2 | 328 cyg_uint32 |
| 329 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data) | |
| 0 | 330 { |
| 331 Cyg_Interrupt *p = *(Cyg_Interrupt **)data; | |
|
10
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
332 register cyg_uint32 isr_ret = 0; |
|
103
95f3e12a6327
Merge from eCos master repository on 2000-06-23-16:41:10-BST
jlarmour
parents:
86
diff
changeset
|
333 register cyg_uint32 isr_chain_ret = 0; |
|
95f3e12a6327
Merge from eCos master repository on 2000-06-23-16:41:10-BST
jlarmour
parents:
86
diff
changeset
|
334 |
| 0 | 335 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0); |
| 336 | |
| 337 while( p != NULL ) | |
| 338 { | |
| 339 if( p->vector == vector ) | |
| 340 { | |
|
10
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
341 isr_ret = p->isr(vector, p->data); |
| 0 | 342 |
|
103
95f3e12a6327
Merge from eCos master repository on 2000-06-23-16:41:10-BST
jlarmour
parents:
86
diff
changeset
|
343 isr_chain_ret |= isr_ret; |
|
95f3e12a6327
Merge from eCos master repository on 2000-06-23-16:41:10-BST
jlarmour
parents:
86
diff
changeset
|
344 |
| 2 | 345 if( isr_ret & Cyg_Interrupt::CALL_DSR ) p->post_dsr(); |
| 0 | 346 |
| 2 | 347 if( isr_ret & Cyg_Interrupt::HANDLED ) break; |
| 0 | 348 } |
| 349 | |
| 350 p = p->next; | |
| 351 } | |
| 352 | |
|
18
7253dcc42a09
Merge from eCos master repository on 1999-06-25-15:31:50-BST
jlarmour
parents:
10
diff
changeset
|
353 #ifdef HAL_DEFAULT_ISR |
|
103
95f3e12a6327
Merge from eCos master repository on 2000-06-23-16:41:10-BST
jlarmour
parents:
86
diff
changeset
|
354 if( (isr_chain_ret & (Cyg_Interrupt::HANDLED|Cyg_Interrupt::CALL_DSR)) == 0 ) |
|
10
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
355 { |
|
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
356 // If we finished the loop for some reason other than that an |
|
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
357 // ISR has handled the interrupt, call any default ISR to either |
|
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
358 // report the spurious interrupt, or do some other HAL level processing |
|
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
359 // such as GDB interrupt detection etc. |
|
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
360 |
|
18
7253dcc42a09
Merge from eCos master repository on 1999-06-25-15:31:50-BST
jlarmour
parents:
10
diff
changeset
|
361 HAL_DEFAULT_ISR( vector, NULL ); |
|
10
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
362 } |
|
d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
8
diff
changeset
|
363 #endif |
| 0 | 364 return 0; |
| 365 } | |
| 366 | |
| 367 #endif | |
| 368 | |
| 369 // ------------------------------------------------------------------------- | |
| 370 // Attach an ISR to an interrupt vector. | |
| 371 | |
| 2 | 372 void |
| 373 Cyg_Interrupt::attach(void) | |
| 0 | 374 { |
| 375 CYG_REPORT_FUNCTION(); | |
| 376 | |
| 2 | 377 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 378 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 379 |
| 380 CYG_INSTRUMENT_INTR(ATTACH, vector, 0); | |
| 381 | |
| 382 HAL_INTERRUPT_SET_LEVEL( vector, priority ); | |
| 383 | |
| 384 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 385 | |
| 386 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list"); | |
| 387 | |
| 388 cyg_uint32 index; | |
| 389 | |
| 390 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 391 | |
| 392 if( chain_list[index] == NULL ) | |
| 393 { | |
| 2 | 394 int in_use; |
| 0 | 395 // First Interrupt on this chain, just assign it and register |
| 396 // the chain_isr with the HAL. | |
| 397 | |
| 398 chain_list[index] = this; | |
| 399 | |
| 2 | 400 HAL_INTERRUPT_IN_USE( vector, in_use ); |
| 401 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 0 | 402 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL ); |
| 403 } | |
| 404 else | |
| 405 { | |
| 406 // There are already interrupts chained, add this one into the | |
| 407 // chain in priority order. | |
| 408 | |
| 409 Cyg_Interrupt **p = &chain_list[index]; | |
| 410 | |
| 411 while( *p != NULL ) | |
| 412 { | |
| 413 Cyg_Interrupt *n = *p; | |
| 414 | |
| 415 if( n->priority < priority ) break; | |
| 416 | |
| 417 p = &n->next; | |
| 418 } | |
| 419 next = *p; | |
| 420 *p = this; | |
| 421 } | |
| 422 | |
| 423 #else | |
| 424 | |
| 2 | 425 { |
| 426 int in_use; | |
| 427 | |
| 428 | |
| 429 HAL_INTERRUPT_IN_USE( vector, in_use ); | |
| 430 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 431 | |
| 432 HAL_INTERRUPT_ATTACH( vector, isr, data, this ); | |
| 433 } | |
| 0 | 434 |
| 435 #endif | |
| 2 | 436 CYG_REPORT_RETURN(); |
| 0 | 437 } |
| 438 | |
| 439 // ------------------------------------------------------------------------- | |
| 440 // Detach the ISR from the vector | |
| 441 | |
| 2 | 442 void |
| 443 Cyg_Interrupt::detach(void) | |
| 0 | 444 { |
| 445 CYG_REPORT_FUNCTION(); | |
| 446 | |
| 2 | 447 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 448 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 449 |
| 450 CYG_INSTRUMENT_INTR(DETACH, vector, 0); | |
| 451 | |
| 452 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 453 | |
| 454 // Remove the interrupt object from the vector chain. | |
| 455 | |
| 2 | 456 cyg_uint32 index; |
| 457 | |
| 458 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 459 | |
| 460 Cyg_Interrupt **p = &chain_list[index]; | |
| 0 | 461 |
| 462 while( *p != NULL ) | |
| 463 { | |
| 464 Cyg_Interrupt *n = *p; | |
| 465 | |
| 466 if( n == this ) | |
| 467 { | |
| 468 *p = next; | |
| 469 break; | |
| 470 } | |
| 471 | |
| 472 p = &n->next; | |
| 473 } | |
| 474 | |
| 475 // If this was the last one, detach the vector. | |
| 476 | |
| 2 | 477 if( chain_list[index] == NULL ) |
| 0 | 478 HAL_INTERRUPT_DETACH( vector, chain_isr ); |
| 479 | |
| 480 #else | |
| 481 | |
| 482 HAL_INTERRUPT_DETACH( vector, isr ); | |
| 483 | |
| 484 #endif | |
| 2 | 485 |
| 486 CYG_REPORT_RETURN(); | |
| 0 | 487 |
| 488 } | |
| 489 | |
| 490 // ------------------------------------------------------------------------- | |
| 491 // Get the current service routine | |
| 492 | |
| 2 | 493 void |
| 494 Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr) | |
| 0 | 495 { |
| 496 CYG_REPORT_FUNCTION(); | |
| 2 | 497 CYG_REPORT_FUNCARG2("vector = %d, mem to put VSR in is at %08x", vector, |
| 498 vsr); | |
| 0 | 499 |
| 2 | 500 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 501 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 502 |
| 503 HAL_VSR_GET( vector, vsr ); | |
| 2 | 504 |
| 505 CYG_REPORT_RETURN(); | |
| 0 | 506 } |
| 507 | |
| 508 // ------------------------------------------------------------------------- | |
| 509 // Install a vector service routine | |
| 510 | |
| 2 | 511 void |
| 512 Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old) | |
| 0 | 513 { |
| 514 CYG_REPORT_FUNCTION(); | |
| 515 | |
| 2 | 516 CYG_REPORT_FUNCARG3( "vector = %d, new vsr is at %08x, mem to put " |
| 517 "old VSR in is at %08x", vector, vsr, old); | |
| 518 | |
| 0 | 519 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr); |
| 520 | |
| 2 | 521 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 522 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 523 |
| 524 CYG_INTERRUPT_STATE old_ints; | |
| 525 | |
| 526 HAL_DISABLE_INTERRUPTS(old_ints); | |
| 527 | |
| 528 HAL_VSR_SET( vector, vsr, old ); | |
| 529 | |
| 530 HAL_RESTORE_INTERRUPTS(old_ints); | |
| 2 | 531 |
| 532 CYG_REPORT_RETURN(); | |
| 0 | 533 } |
| 534 | |
| 535 // ------------------------------------------------------------------------- | |
| 536 // Disable interrupts at the CPU | |
| 537 | |
| 538 | |
| 2 | 539 void |
| 540 Cyg_Interrupt::disable_interrupts(void) | |
| 0 | 541 { |
| 542 CYG_REPORT_FUNCTION(); | |
| 543 | |
| 2 | 544 CYG_INSTRUMENT_INTR(DISABLE, disable_counter+1, 0); |
| 0 | 545 |
| 546 CYG_INTERRUPT_STATE dummy; | |
| 547 | |
| 548 HAL_DISABLE_INTERRUPTS(dummy); | |
| 549 | |
| 2 | 550 CYG_ASSERT( disable_counter >= 0 , "Disable counter negative"); |
| 551 | |
| 552 disable_counter++; | |
| 553 | |
| 554 CYG_REPORT_RETURN(); | |
| 0 | 555 } |
| 556 | |
| 557 | |
| 558 // ------------------------------------------------------------------------- | |
| 559 // Re-enable CPU interrupts | |
| 560 | |
| 2 | 561 void |
| 562 Cyg_Interrupt::enable_interrupts(void) | |
| 0 | 563 { |
| 564 CYG_REPORT_FUNCTION(); | |
| 565 | |
| 2 | 566 CYG_INSTRUMENT_INTR(ENABLE, disable_counter, 0); |
| 567 | |
| 568 CYG_ASSERT( disable_counter > 0 , "Disable counter not greater than zero"); | |
| 569 | |
| 570 disable_counter--; | |
| 0 | 571 |
| 2 | 572 if ( disable_counter == 0 ) |
| 573 { | |
| 574 HAL_ENABLE_INTERRUPTS(); | |
| 575 } | |
| 576 | |
| 577 CYG_REPORT_RETURN(); | |
| 0 | 578 } |
| 579 | |
| 580 // ------------------------------------------------------------------------- | |
| 581 // Mask a specific interrupt in a PIC | |
| 582 | |
| 2 | 583 void |
| 584 Cyg_Interrupt::mask_interrupt(cyg_vector vector) | |
| 0 | 585 { |
| 586 CYG_REPORT_FUNCTION(); | |
| 2 | 587 CYG_REPORT_FUNCARG1("vector=%d", vector); |
| 0 | 588 |
| 2 | 589 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 590 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 591 |
| 592 CYG_INSTRUMENT_INTR(MASK, vector, 0); | |
| 593 | |
| 2 | 594 HAL_INTERRUPT_MASK( vector ); |
| 595 | |
| 596 CYG_REPORT_RETURN(); | |
| 0 | 597 } |
| 598 | |
| 599 // ------------------------------------------------------------------------- | |
| 600 // Clear PIC mask | |
| 601 | |
| 2 | 602 void |
| 603 Cyg_Interrupt::unmask_interrupt(cyg_vector vector) | |
| 0 | 604 { |
| 605 CYG_REPORT_FUNCTION(); | |
| 606 | |
| 2 | 607 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 608 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 609 |
| 610 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); | |
| 611 | |
| 612 HAL_INTERRUPT_UNMASK( vector ); | |
| 2 | 613 |
| 614 CYG_REPORT_RETURN(); | |
| 0 | 615 } |
| 616 | |
| 617 | |
| 618 // ------------------------------------------------------------------------- | |
| 619 // Acknowledge interrupt at PIC | |
| 620 | |
| 2 | 621 void |
| 622 Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector) | |
| 0 | 623 { |
| 624 // CYG_REPORT_FUNCTION(); | |
| 625 | |
| 2 | 626 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 627 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 628 |
| 629 CYG_INSTRUMENT_INTR(ACK, vector, 0); | |
| 630 | |
| 631 HAL_INTERRUPT_ACKNOWLEDGE( vector ); | |
| 632 } | |
| 633 | |
| 634 // ------------------------------------------------------------------------- | |
| 635 // Change interrupt detection at PIC | |
| 636 | |
| 2 | 637 void |
| 638 Cyg_Interrupt::configure_interrupt( | |
| 0 | 639 cyg_vector vector, // vector to control |
| 640 cyg_bool level, // level or edge triggered | |
| 641 cyg_bool up // hi/lo level, rising/falling edge | |
| 642 ) | |
| 643 { | |
| 644 CYG_REPORT_FUNCTION(); | |
| 2 | 645 CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level, |
| 646 up); | |
| 0 | 647 |
| 2 | 648 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 649 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 650 |
| 651 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up); | |
| 652 | |
| 653 HAL_INTERRUPT_CONFIGURE( vector, level, up ); | |
| 2 | 654 |
| 655 CYG_REPORT_RETURN(); | |
| 0 | 656 } |
| 657 | |
| 658 // ------------------------------------------------------------------------- | |
| 659 // EOF intr/intr.cxx |