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RedBoot 'exec' command is now controlled by RedBoot CDL.
author gthomas
date Tue, 06 Aug 2002 14:34:03 +0000
parents d2c90368aeef
children 74dbf4c3f2e1
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1 #ifndef CYGONCE_PLF_IO_H
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2 #define CYGONCE_PLF_IO_H
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3
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4 //=============================================================================
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5 //
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6 // plf_io.h
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7 //
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8 // Platform specific IO support
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9 //
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10 //=============================================================================
208
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
208
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): hmt, jskov
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47 // Contributors: hmt, jskov
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48 // Date: 1999-08-09
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49 // Purpose: Intel EBSA285 PCI IO support macros
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50 // Description:
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51 // Usage: #include <cyg/hal/plf_io.h>
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52 //
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53 // Note: Based on information in
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54 // "21285 Core Logic for SA-110 Microprocessor"
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55 //####DESCRIPTIONEND####
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56 //
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57 //=============================================================================
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58
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59 #include <pkgconf/hal_arm_ebsa285.h>
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60
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61 #include <cyg/hal/hal_ebsa285.h>
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62
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63 #include <cyg/hal/hal_io.h> // IO macros
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64 #include <cyg/hal/hal_platform_ints.h> // Interrupt vectors
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65
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66 // Memory map is 1-1
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67 #define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_)
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68
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69 // The PCI resources required by the EBSA are hardcoded to the lowest
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70 // addresses in the PCI address space, thus:
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71 // PCI Memory Space
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72 #define EBSA_SDRAM_PCI_ADDR 0
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73 #define EBSA_SDRAM_PCI_SIZE (CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE)
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74 #define EBSA_CSR_MEM_PCI_ADDR (EBSA_SDRAM_PCI_SIZE)
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75 #define EBSA_CSR_MEM_PCI_SIZE 0x80
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76 // PCI IO Space
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77 #define EBSA_CSR_IO_PCI_ADDR 0
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78 #define EBSA_CSR_IO_PCI_SIZE 0x80
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79
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80 // Incidentally I now understand why it's necessary to force PCI reset
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81 // (2000-08-07) - with RedBoot in ROM, the RAM app was unconditionally
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82 // reinitializing the PCI bus when it was already initialized, without
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83 // resetting it. We cannot play the same game here as with
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84 // hal_platform_setup.h - I tried - because otherwise the net cannot
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85 // re-initialize itself; the scan for devices fails.
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86
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87 // Initialize the PCI bus.
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88 #define HAL_PCI_INIT() \
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89 CYG_MACRO_START \
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90 cyg_uint32 __tmp, __tmp2; \
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91 \
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92 /* Assert PCI_reset */ \
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93 HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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94 __tmp &= ~SA110_CONTROL_RST_I; \
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95 HAL_WRITE_UINT32(SA110_CONTROL, __tmp); \
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96 \
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97 /* Disable PCI Outbound interrupts */ \
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98 /* (according to 7-14 SA110_OUT_INT_MASK is not accessible */ \
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99 /* by SA-100) */ \
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100 HAL_WRITE_UINT32(SA110_OUT_INT_STATUS, \
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101 SA110_OUT_INT_STATUS_DOORBELL_INT \
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102 |SA110_OUT_INT_STATUS_OUTBOUND_INT); \
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103 \
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104 /* Disable Doorbells */ \
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105 HAL_WRITE_UINT32(SA110_DOORBELL_PCI_MASK, 0); \
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106 HAL_WRITE_UINT32(SA110_DOORBELL_SA_MASK, 0); \
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107 \
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108 /* Map high PCI address bits to 0 */ \
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109 HAL_WRITE_UINT32(SA110_PCI_ADDR_EXT, 0); \
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110 \
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111 /* Interrupt ID to 1 */ \
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112 HAL_WRITE_UINT16(SA110_PCI_CFG_INT_LINE, 0x0100); \
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113 \
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114 /* Remove PCI_reset */ \
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115 HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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116 __tmp |= SA110_CONTROL_RST_I; \
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117 HAL_WRITE_UINT32(SA110_CONTROL, __tmp); \
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118 \
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119 /* Open a window to SDRAM from PCI address space */ \
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120 HAL_WRITE_UINT32(SA110_SDRAM_BASE_ADDRESS_MASK, \
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121 ((CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE-1) & 0xfffc0000)); \
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122 HAL_WRITE_UINT32(SA110_SDRAM_BASE_ADDRESS_OFFSET, \
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123 CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE); \
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124 \
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125 /* Only init PCI if central function is set and */ \
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126 /* standalone bit is cleared */ \
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127 HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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128 HAL_READ_UINT32(SA110_XBUS_XCS2, __tmp2); \
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129 if ((__tmp & SA110_CONTROL_CFN) == SA110_CONTROL_CFN \
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130 && (__tmp2 & SA110_XBUS_XCS2_PCI_DISABLE) == 0) { \
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131 \
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132 /* Don't respond to any commands */ \
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133 HAL_WRITE_UINT16(SA110_PCI_CFG_COMMAND, 0); \
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134 \
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135 /* Set up default addresses for board's resources. */ \
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136 HAL_WRITE_UINT32(SA110_PCI_CFG_CSR_MEM_BAR, \
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137 EBSA_CSR_MEM_PCI_ADDR); \
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138 HAL_WRITE_UINT32(SA110_PCI_CFG_CSR_IO_BAR, EBSA_CSR_IO_PCI_ADDR);\
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139 HAL_WRITE_UINT32(SA110_PCI_CFG_SDRAM_BAR, EBSA_SDRAM_PCI_ADDR); \
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140 \
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141 /* Respond to I/O space & Memory transactions. */ \
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142 HAL_WRITE_UINT32(SA110_PCI_CFG_COMMAND, \
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143 CYG_PCI_CFG_COMMAND_INVALIDATE \
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144 |CYG_PCI_CFG_COMMAND_IO \
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145 |CYG_PCI_CFG_COMMAND_MEMORY \
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146 |CYG_PCI_CFG_COMMAND_MASTER); \
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147 } \
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148 /* Signal PCI_init_complete */ \
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149 HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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150 __tmp |= SA110_CONTROL_INIT_COMPLETE; \
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151 HAL_WRITE_UINT32(SA110_CONTROL, __tmp); \
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152 \
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153 CYG_MACRO_END
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154
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155
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156 // Compute address necessary to access PCI config space for the given
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157 // bus and device.
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158 #define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
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159 ({ \
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160 cyg_uint32 __addr; \
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161 cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
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162 if (0 == __bus) { \
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163 if (0 == __dev) { \
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164 /* Access self via CSR base */ \
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165 __addr = SA110_CONTROL_STATUS_BASE; \
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166 } else { \
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167 /* Page 3-17, table 3-5: bits 15-11 generate PCI address */ \
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168 __addr = SA110_PCI_CONFIG0_BASE | 0x00c00000 | (__dev << 11);\
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169 } \
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170 } else { \
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171 __addr = SA110_PCI_CONFIG1_BASE | (__bus << 16) | (__dev << 11); \
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172 } \
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173 __addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \
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174 __addr |= __offset; \
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175 __addr; \
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176 })
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177
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178 // Read a value from the PCI configuration space of the appropriate
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179 // size at an address composed from the bus, devfn and offset.
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180 #define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
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181 HAL_READ_UINT8(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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182
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183 #define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
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184 HAL_READ_UINT16(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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185
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186 #define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
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187 HAL_READ_UINT32(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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188
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189 // Write a value to the PCI configuration space of the appropriate
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190 // size at an address composed from the bus, devfn and offset.
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191 #define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
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192 HAL_WRITE_UINT8(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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193
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194 #define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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195 HAL_WRITE_UINT16(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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196
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197 #define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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198 HAL_WRITE_UINT32(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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199
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200 //-----------------------------------------------------------------------------
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201 // Resources
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202
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203 // Map PCI device resources starting from these addresses in PCI space.
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204 #define HAL_PCI_ALLOC_BASE_MEMORY (EBSA_SDRAM_PCI_SIZE+EBSA_CSR_MEM_PCI_SIZE)
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205 #define HAL_PCI_ALLOC_BASE_IO (EBSA_CSR_IO_PCI_SIZE)
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206
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207 // This is where the PCI spaces are mapped in the CPU's address space.
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208 #define HAL_PCI_PHYSICAL_MEMORY_BASE 0x80000000
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209 #define HAL_PCI_PHYSICAL_IO_BASE 0x7c000000
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210
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211 // Translate the PCI interrupt requested by the device (INTA#, INTB#,
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212 // INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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213 #define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
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214 CYG_MACRO_START \
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215 cyg_uint8 __req; \
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216 HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
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217 if (0 != __req) { \
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218 /* Interrupt assignment as 21285 sees them. (From */ \
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219 /* EBSA285 Eval Board Reference Manual, 3.4 Interrupt Assignment) */ \
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220 CYG_ADDRWORD __translation[4] = { \
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221 CYGNUM_HAL_INTERRUPT_IRQ_IN_1, /* INTC# */ \
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222 CYGNUM_HAL_INTERRUPT_IRQ_IN_0, /* INTB# */ \
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223 CYGNUM_HAL_INTERRUPT_PCI_IRQ, /* INTA# */ \
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224 CYGNUM_HAL_INTERRUPT_IRQ_IN_3}; /* INTD# */ \
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225 \
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226 /* The PCI lines from the different slots are wired like this */ \
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227 /* on the PCI backplane: */ \
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228 /* pin6A pin7B pin7A pin8B */ \
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229 /* System Slot INTA# INTB# INTC# INTD# */ \
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230 /* I/O Slot 1 INTB# INTC# INTD# INTA# */ \
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231 /* I/O Slot 2 INTC# INTD# INTA# INTB# */ \
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232 /* I/O Slot 3 INTD# INTA# INTB# INTC# */ \
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233 /* I/O Slot 4 INTA# INTB# INTC# INTD# */ \
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234 /* */ \
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235 /* (From PCI Development Backplane, 3.2.2 Interrupts) */ \
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236 /* */ \
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237 /* Devsel signals are wired to, resulting in device IDs: */ \
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238 /* I/O Slot 1 AD19 / dev 8 [(8+1)&3 = 1] */ \
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239 /* I/O Slot 2 AD18 / dev 7 [(7+1)&3 = 0] */ \
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240 /* I/O Slot 3 AD17 / dev 6 [(6+1)&3 = 3] */ \
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241 /* I/O Slot 4 AD16 / dev 5 [(5+1)&3 = 2] */ \
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242 /* */ \
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243 /* (From PCI Development Backplane, 3.2.1 General) */ \
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244 /* */ \
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245 /* The observant reader will notice that the array does not */ \
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246 /* match the table of how interrupts are wired. The array */ \
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247 /* does however match observed behavior of the hardware: */ \
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248 /* */ \
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249 /* Observed interrupts with an Intel ethernet card */ \
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250 /* put in the slots in turn and set to generate interrupts: */ \
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251 /* slot 1/intA# (dev 8): caused host INTB# */ \
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252 /* slot 2/intA# (dev 7): caused host INTC# */ \
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253 /* slot 3/intA# (dev 6): caused host INTD# */ \
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254 /* slot 4/intA# (dev 5): caused host INTA# */ \
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255 \
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256 __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
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257 __valid = true; \
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258 } else { \
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259 /* Device will not generate interrupt requests. */ \
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260 __valid = false; \
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261 } \
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262 CYG_MACRO_END
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263
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264 //-----------------------------------------------------------------------------
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265 // end of plf_io.h
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266 #endif // CYGONCE_PLF_IO_H