Mercurial > ecos
annotate packages/hal/cortexm/arch/current/src/hal_misc.c @ 3138:9dd3ea41e5b6
* src/hal_misc.c (hal_reset_vsr): Ensure we only init intr vectors
up to top of VSR table.
| author | jlarmour |
|---|---|
| date | Sun, 01 Apr 2012 01:58:28 +0000 |
| parents | 9aec6a8ff9b9 |
| children | abf5be1b8582 |
| rev | line source |
|---|---|
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1 /*========================================================================== |
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2 // |
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3 // hal_misc.c |
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4 // |
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5 // Cortex-M exception vectors |
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6 // |
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7 //========================================================================== |
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8 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 2008 Free Software Foundation, Inc. |
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12 // |
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13 // eCos is free software; you can redistribute it and/or modify it under |
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14 // the terms of the GNU General Public License as published by the Free |
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15 // Software Foundation; either version 2 or (at your option) any later |
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16 // version. |
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17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
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22 // |
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23 // You should have received a copy of the GNU General Public License |
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24 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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26 // |
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27 // As a special exception, if other files instantiate templates or use |
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28 // macros or inline functions from this file, or you compile this file |
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29 // and link it with other works to produce a work based on this file, |
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30 // this file does not by itself cause the resulting work to be covered by |
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31 // the GNU General Public License. However the source code for this file |
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32 // must still be made available in accordance with section (3) of the GNU |
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33 // General Public License v2. |
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34 // |
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35 // This exception does not invalidate any other reasons why a work based |
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36 // on this file might be covered by the GNU General Public License. |
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37 // ------------------------------------------- |
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38 // ####ECOSGPLCOPYRIGHTEND#### |
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39 //========================================================================== |
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40 //#####DESCRIPTIONBEGIN#### |
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41 // |
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42 // Author(s): nickg |
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43 // Date: 2008-07-30 |
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44 // |
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45 //####DESCRIPTIONEND#### |
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46 // |
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47 //========================================================================*/ |
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48 |
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49 #include <pkgconf/hal.h> |
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50 #include <pkgconf/hal_cortexm.h> |
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51 #ifdef CYGPKG_KERNEL |
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52 #include <pkgconf/kernel.h> |
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53 #endif |
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54 |
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55 #include <cyg/infra/diag.h> |
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56 #include <cyg/infra/cyg_type.h> |
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57 #include <cyg/infra/cyg_trac.h> // tracing macros |
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58 #include <cyg/infra/cyg_ass.h> // assertion macros |
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59 |
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60 #include <cyg/hal/hal_arch.h> // HAL header |
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61 #include <cyg/hal/hal_intr.h> // HAL header |
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62 |
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63 #include <cyg/hal/drv_api.h> |
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64 |
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65 |
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66 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \ |
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67 defined(CYGDBG_KERNEL_INSTRUMENT_INTR) |
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68 #include <cyg/kernel/instrmnt.h> |
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69 #endif |
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70 |
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71 //========================================================================== |
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72 |
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73 typedef cyg_uint32 cyg_isr(cyg_uint32 vector, CYG_ADDRWORD data); |
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74 |
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75 //========================================================================== |
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76 // External references |
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77 |
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78 // VSRs in vectors.S |
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79 __externC void hal_default_exception_vsr( void ); |
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80 __externC void hal_default_interrupt_vsr( void ); |
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81 __externC void hal_default_svc_vsr( void ); |
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82 __externC void hal_pendable_svc_vsr( void ); |
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83 __externC void hal_switch_state_vsr( void ); |
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84 |
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85 // HAL and eCos functions |
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86 __externC void hal_system_init( void ); |
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87 __externC void hal_variant_init( void ); |
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88 __externC void hal_platform_init( void ); |
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89 __externC void hal_ctrlc_isr_init( void ); |
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90 __externC void initialize_stub( void ); |
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91 __externC void cyg_hal_invoke_constructors( void ); |
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92 __externC void cyg_start( void ); |
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93 __externC void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ); |
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94 __externC void interrupt_end(cyg_uint32 isr_ret, CYG_ADDRWORD intr, HAL_SavedRegisters *regs ); |
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95 |
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96 // DATA and BSS locations |
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97 __externC cyg_uint32 __ram_data_start; |
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98 __externC cyg_uint32 __ram_data_end; |
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99 __externC cyg_uint32 __rom_data_start; |
| 2774 | 100 __externC cyg_uint32 __sram_data_start; |
| 101 __externC cyg_uint32 __sram_data_end; | |
| 102 __externC cyg_uint32 __srom_data_start; | |
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103 __externC cyg_uint32 __bss_start; |
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104 __externC cyg_uint32 __bss_end; |
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105 |
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106 // Scheduler lock |
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107 __externC volatile cyg_uint32 cyg_scheduler_sched_lock; |
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108 |
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109 //========================================================================== |
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110 // Interrupt tables |
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111 |
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112 volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; |
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113 volatile CYG_ADDRWORD hal_interrupt_data [CYGNUM_HAL_ISR_COUNT]; |
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114 volatile CYG_ADDRESS hal_interrupt_objects [CYGNUM_HAL_ISR_COUNT]; |
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115 |
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116 //========================================================================== |
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117 // Main entry point |
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118 // |
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119 // Enter here from reset via slot 1 of VSR table. The stack pointer is |
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120 // already set to the value in VSR slot 0, usually the top of internal |
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121 // SRAM. |
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122 |
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123 void hal_reset_vsr( void ) |
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124 { |
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125 // Call system init routine. This should do the minimum necessary |
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126 // for the rest of the initialization to complete. For example set |
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127 // up GPIO, the SRAM, power management etc. This routine is |
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128 // usually supplied by the platform HAL. Calls to |
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129 // hal_variant_init() and hal_platform_init() later will perform |
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130 // the main initialization. |
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131 |
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132 hal_system_init(); |
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133 |
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134 // Initialize vector table in base of SRAM. |
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135 { |
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136 register int i; |
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137 |
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138 #if !defined(CYG_HAL_STARTUP_RAM) |
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139 |
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140 // Only install the exception vectors for non-RAM startup. For |
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141 // RAM startup we want these to continue to point to the original |
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142 // VSRs, which will belong to RedBoot or GDB stubs. |
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143 |
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144 for( i = 2; i < 15; i++ ) |
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145 hal_vsr_table[i] = (CYG_ADDRESS)hal_default_exception_vsr; |
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146 |
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147 #endif |
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148 // Always point SVC and PENDSVC vectors to our local versions |
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149 |
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150 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr; |
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151 hal_vsr_table[CYGNUM_HAL_VECTOR_PENDSV] = (CYG_ADDRESS)hal_pendable_svc_vsr; |
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152 |
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153 // For all startup type, redirect interrupt vectors to our VSR. |
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154 for( i = CYGNUM_HAL_VECTOR_SYS_TICK ; |
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155 i < CYGNUM_HAL_VSR_MAX; |
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156 i++ ) |
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157 hal_vsr_table[i] = (CYG_ADDRESS)hal_default_interrupt_vsr; |
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158 } |
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159 |
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160 |
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161 #if !defined(CYG_HAL_STARTUP_RAM) |
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162 |
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163 // Ensure that the CPU will use the vector table we have just set |
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164 // up. |
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165 |
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166 # if defined(CYGHWR_HAL_CORTEXM_M3) || defined(CYGHWR_HAL_CORTEXM_M4) |
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167 |
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168 // On M3 and M4 parts, the NVIC contains a vector table base register. |
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169 // We program this to relocate the vector table base to the base of SRAM. |
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170 |
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171 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR, |
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172 CYGARC_REG_NVIC_VTOR_TBLOFF(0)| |
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173 CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM ); |
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174 |
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175 # else |
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176 |
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177 # error Unknown SRAM/VECTAB remap mechanism |
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178 |
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179 # endif |
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180 |
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181 // Use SVC to switch our state to thread mode running on the PSP. |
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182 // We don't need to do this for RAM startup since the ROM code |
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183 // will have already done it. |
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184 |
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185 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr; |
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186 |
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187 __asm__ volatile( "swi 0" ); |
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188 |
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189 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr; |
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190 |
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191 #endif // !defined(CYG_HAL_STARTUP_RAM) |
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192 |
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193 #if defined(CYG_HAL_STARTUP_ROM) |
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194 // Relocate data from ROM to RAM |
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195 { |
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196 register cyg_uint32 *p, *q; |
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197 for( p = &__ram_data_start, q = &__rom_data_start; |
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198 p < &__ram_data_end; |
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199 p++, q++ ) |
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200 *p = *q; |
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201 } |
| 2774 | 202 |
| 203 // Relocate data from ROM to SRAM | |
| 204 { | |
| 205 register cyg_uint32 *p, *q; | |
| 206 for( p = &__sram_data_start, q = &__srom_data_start; | |
| 207 p < &__sram_data_end; | |
| 208 p++, q++ ) | |
| 209 *p = *q; | |
| 210 } | |
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211 #endif |
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212 |
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213 // Clear BSS |
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214 { |
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215 register cyg_uint32 *p; |
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216 for( p = &__bss_start; p < &__bss_end; p++ ) |
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217 *p = 0; |
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218 } |
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219 |
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220 // Initialize interrupt vectors. Set the levels for all interrupts |
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221 // to default values. Also set the default priorities of the |
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222 // system handlers: all exceptions maximum priority except SVC and |
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223 // PendSVC which are lowest priority. |
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224 { |
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225 register int i; |
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226 |
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227 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR0, 0x00000000 ); |
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228 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR1, 0xFF000000 ); |
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229 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, 0x00FF0000 ); |
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230 |
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231 hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SYS_TICK] = (CYG_ADDRESS)hal_default_isr; |
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232 |
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233 for( i = 1; i < CYGNUM_HAL_ISR_COUNT; i++ ) |
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234 { |
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235 hal_interrupt_handlers[i] = (CYG_ADDRESS)hal_default_isr; |
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236 HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(i-CYGNUM_HAL_INTERRUPT_EXTERNAL), 0x80 ); |
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237 } |
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238 } |
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239 |
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240 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) |
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241 // Enable DebugMonitor exceptions. This is needed to enable single |
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242 // step. This only has an effect if no external JTAG device is |
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243 // attached. |
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244 { |
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245 CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE; |
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246 cyg_uint32 demcr; |
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247 |
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248 HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr ); |
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249 demcr |= CYGARC_REG_DEBUG_DEMCR_MON_EN; |
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250 HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr ); |
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251 } |
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252 #endif |
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253 |
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254 #if !defined(CYG_HAL_STARTUP_RAM) |
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255 // Enable Usage, Bus and Mem fault handlers. Do this for ROM and |
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256 // JTAG startups. For RAM startups, this will have already been |
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257 // done by the ROM monitor. |
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258 { |
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259 CYG_ADDRESS base = CYGARC_REG_NVIC_BASE; |
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260 cyg_uint32 shcsr; |
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261 |
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262 HAL_READ_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr ); |
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263 shcsr |= CYGARC_REG_NVIC_SHCSR_USGFAULTENA; |
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264 shcsr |= CYGARC_REG_NVIC_SHCSR_BUSFAULTENA; |
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265 shcsr |= CYGARC_REG_NVIC_SHCSR_MEMFAULTENA; |
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266 HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr ); |
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267 } |
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268 #endif |
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269 |
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270 // Call variant and platform init routines |
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271 hal_variant_init(); |
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272 hal_platform_init(); |
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273 |
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274 // Start up the system clock |
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275 HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD ); |
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276 |
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277 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
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278 |
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279 initialize_stub(); |
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280 |
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281 #endif |
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282 |
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283 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \ |
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284 defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) |
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285 |
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286 hal_ctrlc_isr_init(); |
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287 |
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288 #endif |
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289 |
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290 // Run through static constructors |
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291 cyg_hal_invoke_constructors(); |
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292 |
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293 // Finally call into application |
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294 cyg_start(); |
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295 for(;;); |
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296 } |
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297 |
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298 //========================================================================== |
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299 // Handle Exceptions |
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300 // |
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301 // Exceptions are passed here from the initial VSR. We pass the |
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302 // exception on to GDB stubs or the kernel as appropriate. |
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303 |
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304 __externC void __handle_exception (void); |
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305 |
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306 __externC HAL_SavedRegisters *_hal_registers; |
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307 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
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308 __externC void* volatile __mem_fault_handler; |
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309 #endif |
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310 |
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311 void hal_deliver_exception( HAL_SavedRegisters *regs ) |
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312 { |
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313 // Special case handler for code which has chosen to take care |
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314 // of data exceptions (i.e. code which expects them to happen) |
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315 // This is common in discovery code, e.g. checking for a particular |
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316 // device which may generate an exception when probing if the |
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317 // device is not present |
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318 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
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319 if (__mem_fault_handler ) |
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320 { |
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321 regs->u.exception.pc = (unsigned long)__mem_fault_handler; |
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322 return; // Caught an exception inside stubs |
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323 } |
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324 #endif |
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325 |
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326 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) |
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327 |
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328 _hal_registers = regs; |
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329 __handle_exception(); |
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330 |
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331 #elif defined(CYGPKG_KERNEL_EXCEPTIONS) |
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332 |
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333 cyg_hal_deliver_exception( regs->u.exception.vector, (CYG_ADDRWORD)regs ); |
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334 |
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335 #else |
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336 |
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337 CYG_FAIL("Exception!!!"); |
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338 |
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339 #endif |
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340 } |
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341 |
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342 //========================================================================== |
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343 // Handle Interrupts |
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344 // |
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345 // Interrupts are passed here from the low-level VSR in vectors.S. We |
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346 // look up the ISR in the interrupt table, call it and if it requests |
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347 // it, post a DSR. If necessary we also then cause the pendable SVC to |
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348 // be requested. |
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349 // |
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350 // This function is also callable from ISR springboards that decode |
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351 // additional interrupts via external controllers to deliver an |
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352 // interrupt to a secondary vector. |
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353 |
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354 void hal_deliver_interrupt( cyg_uint32 vector ) |
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355 { |
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356 register cyg_uint32 isr_result; |
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357 register cyg_isr *isr; |
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358 cyg_bool pendsvc = false; |
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359 |
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360 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \ |
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361 defined(CYGDBG_KERNEL_INSTRUMENT_INTR) |
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362 CYG_INSTRUMENT_INTR(RAISE, vector, 0); |
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363 #endif |
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364 |
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365 isr = (cyg_isr *)hal_interrupt_handlers[vector]; |
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366 |
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367 // Call the ISR |
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368 isr_result = isr( vector, hal_interrupt_data[vector] ); |
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369 |
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370 |
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371 #if !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) |
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372 // If the ISR has returned the CALL_DSR bit, post the DSR and set |
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373 // the pendable SVC exception pending. |
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374 if( isr_result & CYG_ISR_CALL_DSR ) |
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375 { |
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376 cyg_interrupt_post_dsr( hal_interrupt_objects[vector] ); |
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377 |
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378 // Post the pendable SVC to call interrupt_end(). But only if |
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379 // the scheduler lock is currently zero. If it is non zero |
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380 // then interrupt_end will do nothing useful, so avoid calling |
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381 // it. |
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382 if( cyg_scheduler_sched_lock == 0 ) |
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383 pendsvc = true; |
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384 } |
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385 #else |
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386 // When chaining we don't know here whether the nested interrupt |
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387 // has posted a DSR, so we have to run interrupt_end() regardless. |
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388 // However, the same considerations as above regarding the |
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389 // scheduler lock still apply. |
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390 if( cyg_scheduler_sched_lock == 0 ) |
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391 pendsvc = true; |
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392 #endif |
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393 |
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394 // Post the pendable SVC if required. |
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395 if( pendsvc ) |
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396 { |
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397 cyg_uint32 icsr; |
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398 HAL_READ_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_ICSR, icsr ); |
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399 icsr |= CYGARC_REG_NVIC_ICSR_PENDSVSET; |
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400 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_ICSR, icsr ); |
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401 } |
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402 } |
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403 |
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404 //========================================================================== |
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405 // Call interrupt_end() |
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406 // |
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407 // This is called on the thread stack as a result of the pendable |
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408 // SVC. interrupt_end() decrements the scheduler lock, calls DSRs and |
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409 // optionally switches thread context. So before calling, we must |
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410 // increment the lock. The actual interrupt end processing has already |
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411 // been done above in hal_default_interrupt_vsr1(), so the arguments |
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412 // are zero. |
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413 |
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414 __externC void hal_interrupt_end( void ) |
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415 { |
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416 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT |
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417 cyg_scheduler_sched_lock++; |
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418 #endif |
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419 |
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420 interrupt_end(0,0,0); |
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421 } |
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422 |
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423 //========================================================================== |
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424 // Interrupt masking and configuration |
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425 |
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426 #ifndef HAL_VAR_INTERRUPT_MASK |
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427 #define HAL_VAR_INTERRUPT_MASK( __vector ) CYG_EMPTY_STATEMENT |
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428 #define HAL_VAR_INTERRUPT_UNMASK( __vector ) CYG_EMPTY_STATEMENT |
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429 #define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) CYG_EMPTY_STATEMENT |
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430 #define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) CYG_EMPTY_STATEMENT |
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431 #define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up ) CYG_EMPTY_STATEMENT |
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432 #endif |
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433 |
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434 //-------------------------------------------------------------------------- |
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435 |
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436 __externC void hal_interrupt_mask( cyg_uint32 vector ) |
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437 { |
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438 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL && |
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439 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX ) |
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440 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_CER(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL), |
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441 CYGARC_REG_NVIC_IBIT(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); |
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442 else if( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK ) |
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443 { |
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444 cyg_uint32 csr; |
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445 HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr ); |
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446 csr &= ~CYGARC_REG_SYSTICK_CSR_TICKINT; |
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447 HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr ); |
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448 } |
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449 HAL_VAR_INTERRUPT_MASK( vector ); |
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450 } |
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451 |
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452 //-------------------------------------------------------------------------- |
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453 |
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454 __externC void hal_interrupt_unmask( cyg_uint32 vector ) |
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455 { |
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456 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL && |
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457 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX ) |
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458 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL), |
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459 CYGARC_REG_NVIC_IBIT(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); |
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460 else if( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK ) |
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461 { |
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462 cyg_uint32 csr; |
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463 HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr ); |
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464 csr |= CYGARC_REG_SYSTICK_CSR_TICKINT; |
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465 HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr ); |
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466 } |
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467 HAL_VAR_INTERRUPT_UNMASK( vector ); |
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468 } |
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469 |
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470 //-------------------------------------------------------------------------- |
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471 |
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472 __externC void hal_interrupt_acknowledge( cyg_uint32 vector ) |
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473 { |
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474 HAL_VAR_INTERRUPT_ACKNOWLEDGE( vector ); |
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475 } |
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476 |
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477 //-------------------------------------------------------------------------- |
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478 |
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479 __externC void hal_interrupt_configure( cyg_uint32 vector, cyg_uint32 level, cyg_uint32 up ) |
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480 { |
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481 HAL_VAR_INTERRUPT_CONFIGURE( vector, level, up ); |
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482 } |
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483 |
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484 //-------------------------------------------------------------------------- |
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485 |
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486 __externC void hal_interrupt_set_level( cyg_uint32 vector, cyg_uint32 level ) |
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487 { |
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488 cyg_uint32 l = (level)+CYGNUM_HAL_CORTEXM_PRIORITY_MAX; |
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489 if( l > 0xFF ) l = 0xFF; /* clamp to 0xFF */ |
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490 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL && |
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491 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX ) |
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492 { |
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493 HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL), |
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494 l ); |
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495 } |
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496 else if ( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK ) |
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497 { |
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498 cyg_uint32 shpr2; |
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499 HAL_READ_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, shpr2 ); |
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500 shpr2 &= ~0xFF000000; |
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501 shpr2 |= (l)<<24; |
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502 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, shpr2 ); |
|
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503 } |
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504 HAL_VAR_INTERRUPT_SET_LEVEL( vector, level ); |
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505 } |
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506 |
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|
507 //========================================================================== |
|
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508 // Microsecond delay |
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|
509 // |
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510 // The system RTC is set up to tick at 1MHz so all we need to do here |
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511 // is count ticks. |
|
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|
512 |
|
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513 __externC void hal_delay_us( cyg_int32 us ) |
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514 { |
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515 cyg_uint32 t0, t1; |
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516 |
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|
517 HAL_CLOCK_READ( &t0 ); |
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518 while ( us > 0 ) |
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519 { |
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520 HAL_CLOCK_READ( &t1 ); |
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521 if( t1 < t0 ) |
| 2589 | 522 us -= (t1 + CYGNUM_HAL_RTC_PERIOD - t0); |
| 523 else | |
| 524 us -= t1 - t0; | |
|
2580
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525 t0 = t1; |
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526 } |
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527 } |
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528 |
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529 //========================================================================== |
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530 // C++ support - run initial constructors |
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|
531 |
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532 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG |
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533 cyg_bool cyg_hal_stop_constructors; |
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534 #endif |
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535 |
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536 typedef void (*pfunc) (void); |
|
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537 |
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538 extern pfunc __init_array_start__[]; |
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539 extern pfunc __init_array_end__[]; |
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540 #define CONSTRUCTORS_START (__init_array_start__[0]) |
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541 #define CONSTRUCTORS_END (__init_array_end__) |
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542 #define NEXT_CONSTRUCTOR(c) ((c)++) |
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|
543 |
|
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544 void |
|
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545 cyg_hal_invoke_constructors (void) |
|
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546 { |
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547 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG |
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548 static pfunc *p = &CONSTRUCTORS_START; |
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549 |
|
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550 cyg_hal_stop_constructors = 0; |
|
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551 for (; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p)) { |
|
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552 (*p)(); |
|
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|
553 if (cyg_hal_stop_constructors) { |
|
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554 NEXT_CONSTRUCTOR(p); |
|
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|
555 break; |
|
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|
556 } |
|
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|
557 } |
|
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|
558 #else |
|
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|
559 pfunc *p; |
|
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|
560 |
|
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|
561 for (p = &CONSTRUCTORS_START; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p)) |
|
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562 (*p)(); |
|
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|
563 #endif |
|
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|
564 } |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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|
565 |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff
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|
566 //========================================================================== |
|
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|
567 // Architecture default ISR |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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|
568 |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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|
569 __externC cyg_uint32 |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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|
570 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) |
|
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|
571 { |
|
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|
572 CYG_TRACE1(true, "Interrupt: %d", vector); |
|
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|
573 |
|
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nickg
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|
574 CYG_FAIL("Spurious Interrupt!!!"); |
|
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|
575 |
|
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|
576 return 0; |
|
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diff
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|
577 } |
|
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nickg
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diff
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|
578 |
|
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diff
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|
579 //========================================================================== |
|
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nickg
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|
580 // GDB support |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff
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|
581 // |
|
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|
582 // These functions translate between HAL saved contexts and GDB |
|
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|
583 // register dumps. |
|
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|
584 |
|
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|
585 __externC void hal_get_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs ) |
|
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|
586 { |
|
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|
587 int i; |
|
07fc475e1c28
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nickg
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changeset
|
588 cyg_uint32 *p = gdbreg->f0; |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff
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|
589 |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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parents:
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|
590 switch( regs->u.type ) |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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changeset
|
591 { |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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changeset
|
592 case HAL_SAVEDREGISTERS_THREAD: |
|
07fc475e1c28
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nickg
parents:
diff
changeset
|
593 for( i = 0; i < 13; i++ ) |
|
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nickg
parents:
diff
changeset
|
594 gdbreg->gpr[i] = regs->u.thread.r[i]; |
|
07fc475e1c28
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nickg
parents:
diff
changeset
|
595 gdbreg->gpr[13] = regs->u.thread.sp; |
|
07fc475e1c28
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diff
changeset
|
596 gdbreg->gpr[14] = regs->u.thread.pc; |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff
changeset
|
597 gdbreg->gpr[15] = regs->u.thread.pc; |
|
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changeset
|
598 gdbreg->ps = 0x01000000; |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
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|
599 break; |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff
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|
600 |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff
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|
601 case HAL_SAVEDREGISTERS_EXCEPTION: |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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|
602 gdbreg->gpr[0] = regs->u.exception.r0; |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff
changeset
|
603 gdbreg->gpr[1] = regs->u.exception.r1; |
|
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nickg
parents:
diff
changeset
|
604 gdbreg->gpr[2] = regs->u.exception.r2; |
|
07fc475e1c28
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nickg
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diff
changeset
|
605 gdbreg->gpr[3] = regs->u.exception.r3; |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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changeset
|
606 for( i = 0; i < 8; i++ ) |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff
changeset
|
607 gdbreg->gpr[i+4] = regs->u.exception.r4_11[i]; |
|
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nickg
parents:
diff
changeset
|
608 gdbreg->gpr[12] = regs->u.exception.r12; |
|
07fc475e1c28
Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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|
609 gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.exception); |
|
07fc475e1c28
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parents:
diff
changeset
|
610 gdbreg->gpr[14] = regs->u.exception.lr; |
|
07fc475e1c28
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parents:
diff
changeset
|
611 gdbreg->gpr[15] = regs->u.exception.pc; |
|
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parents:
diff
changeset
|
612 gdbreg->ps = regs->u.exception.psr; |
|
07fc475e1c28
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diff
changeset
|
613 break; |
|
07fc475e1c28
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changeset
|
614 |
|
07fc475e1c28
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diff
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|
615 case HAL_SAVEDREGISTERS_INTERRUPT: |
|
07fc475e1c28
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|
616 gdbreg->gpr[0] = regs->u.interrupt.r0; |
|
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diff
changeset
|
617 gdbreg->gpr[1] = regs->u.interrupt.r1; |
|
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|
618 gdbreg->gpr[2] = regs->u.interrupt.r2; |
|
07fc475e1c28
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|
619 gdbreg->gpr[3] = regs->u.interrupt.r3; |
|
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changeset
|
620 gdbreg->gpr[12] = regs->u.interrupt.r12; |
|
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diff
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|
621 gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.interrupt); |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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|
622 gdbreg->gpr[14] = regs->u.interrupt.lr; |
|
07fc475e1c28
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diff
changeset
|
623 gdbreg->gpr[15] = regs->u.interrupt.pc; |
|
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nickg
parents:
diff
changeset
|
624 gdbreg->ps = regs->u.interrupt.psr; |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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changeset
|
625 break; |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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parents:
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changeset
|
626 } |
|
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Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
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changeset
|
627 |
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628 // Clear FP state, which we don't use |
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629 for( i = 0; i < (8*3+1); i++ ) |
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630 p[i] = 0; |
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631 |
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632 } |
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633 |
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634 __externC void hal_set_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs ) |
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635 { |
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636 int i; |
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637 |
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638 switch( regs->u.type ) |
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639 { |
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640 case HAL_SAVEDREGISTERS_THREAD: |
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641 for( i = 0; i < 13; i++ ) |
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642 regs->u.thread.r[i] = gdbreg->gpr[i]; |
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643 regs->u.thread.sp = gdbreg->gpr[13]; |
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644 regs->u.thread.pc = gdbreg->gpr[14]; |
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645 regs->u.thread.pc = gdbreg->gpr[15]; |
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646 break; |
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647 |
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648 case HAL_SAVEDREGISTERS_EXCEPTION: |
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649 regs->u.exception.r0 = gdbreg->gpr[0]; |
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650 regs->u.exception.r1 = gdbreg->gpr[1]; |
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651 regs->u.exception.r2 = gdbreg->gpr[2]; |
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652 regs->u.exception.r3 = gdbreg->gpr[3]; |
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653 for( i = 0; i < 8; i++ ) |
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654 regs->u.exception.r4_11[i] = gdbreg->gpr[i+4]; |
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655 regs->u.exception.r12 = gdbreg->gpr[12]; |
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656 regs->u.exception.lr = gdbreg->gpr[14]; |
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657 regs->u.exception.pc = gdbreg->gpr[15]; |
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658 regs->u.exception.psr = gdbreg->ps; |
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659 break; |
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660 |
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661 case HAL_SAVEDREGISTERS_INTERRUPT: |
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662 regs->u.interrupt.r0 = gdbreg->gpr[0]; |
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663 regs->u.interrupt.r1 = gdbreg->gpr[1]; |
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664 regs->u.interrupt.r2 = gdbreg->gpr[2]; |
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665 regs->u.interrupt.r3 = gdbreg->gpr[3]; |
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666 regs->u.interrupt.r12 = gdbreg->gpr[12]; |
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667 regs->u.interrupt.lr = gdbreg->gpr[14]; |
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668 regs->u.interrupt.pc = gdbreg->gpr[15]; |
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669 regs->u.interrupt.psr = gdbreg->ps; |
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670 break; |
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671 } |
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672 } |
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673 |
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674 //========================================================================== |
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675 // When compiling C++ code with static objects the compiler |
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676 // inserts a call to __cxa_atexit() with __dso_handle as one of the |
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677 // arguments. __cxa_atexit() would normally be provided by glibc, and |
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678 // __dso_handle is part of crtstuff.c. eCos applications |
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679 // are linked rather differently, so either a differently-configured |
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680 // compiler is needed or dummy versions of these symbols should be |
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681 // provided. If these symbols are not actually used then providing |
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682 // them is still harmless, linker garbage collection will remove them. |
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683 |
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684 void |
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685 __cxa_atexit(void (*arg1)(void*), void* arg2, void* arg3) |
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686 { |
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687 } |
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688 |
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689 void* __dso_handle = (void*) &__dso_handle; |
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690 |
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691 //========================================================================== |
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692 // EOF hal_misc.c |
