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annotate packages/hal/sh/cq7750/current/cdl/hal_sh_sh7750_cq7750.cdl @ 136:a9ac27ec7abc ecos-sw-2000-11-17

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Merge from eCos master repository on 2000-11-17-18:24:25-GMT
author jlarmour
date Fri, 17 Nov 2000 23:16:43 +0000
parents d2f49caf9e38
children b939e9cada46
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1 # ====================================================================
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2 #
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3 # hal_sh_sh7750_cq7750.cdl
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4 #
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5 # CQ7750 board HAL package configuration data
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6 #
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7 # ====================================================================
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8 #####COPYRIGHTBEGIN####
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Red Hat eCos Public License
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12 # Version 1.1 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://www.redhat.com/
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15 #
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16 # Software distributed under the License is distributed on an "AS IS"
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Configurable Operating System,
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22 # released September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Red Hat.
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25 # Portions created by Red Hat are
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26 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 # All Rights Reserved.
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28 # -------------------------------------------
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29 #
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30 #####COPYRIGHTEND####
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31 # ====================================================================
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32 ######DESCRIPTIONBEGIN####
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33 #
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34 # Author(s): jskov
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35 # Original data: jskov
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36 # Contributors: Ryozaburo Suzuki
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37 # Date: 1999-10-29
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38 #
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39 #####DESCRIPTIONEND####
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40 #
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41 # ====================================================================
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42
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43 cdl_package CYGPKG_HAL_SH_SH7750_CQ7750 {
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44 display "CqREEK SH7750 board"
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45 parent CYGPKG_HAL_SH
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46 requires CYGPKG_HAL_SH_7750
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47 define_header hal_sh_sh7750_cq7750.h
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48 include_dir cyg/hal
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49 description "
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50 The cq HAL package provides the support needed to run
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51 eCos on a CqREEK SH7750 board."
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52
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53 compile hal_diag.c plf_misc.c
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54
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55 implements CYGINT_HAL_DEBUG_GDB_STUBS
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56 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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57 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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58 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED
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59
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60 define_proc {
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61 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
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62 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh7750_cq7750.h>"
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63
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64 puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1"
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65 puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x08000000"
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66 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x08000100"
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67 }
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68
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69 cdl_component CYG_HAL_STARTUP {
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70 display "Startup type"
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71 flavor data
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72 legal_values {"RAM" "ROM"}
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73 default_value {"RAM"}
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74 no_define
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75 define -file system.h CYG_HAL_STARTUP
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76 description "
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77 When targetting the CQ7750 board it is possible to build
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78 the system for either RAM bootstrap or ROM bootstrap.
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79 RAM bootstrap generally requires that the board
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80 is equipped with ROMs containing a suitable ROM monitor or
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81 equivalent software that allows GDB to download the eCos
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82 application on to the board. The ROM bootstrap typically
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83 requires that the eCos application be blown into EPROMs or
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84 equivalent technology."
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85 }
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86
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87
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88 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
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89 display "Number of communication channels on the board"
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90 flavor data
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91 calculated 1
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92 }
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93
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94 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
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95 display "Debug serial port"
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96 flavor data
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97 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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98 default_value 0
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99 description "
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100 The CQ/7750 board has only one serial port. This option
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101 chooses which port will be used to connect to a host
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102 running GDB."
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103 }
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104
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105 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
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106 display "Diagnostic serial port"
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107 flavor data
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108 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
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109 default_value 0
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110 description "
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111 The CQ/7750 board has only one serial port. This option
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112 chooses which port will be used for diagnostic output."
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113 }
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114
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115 cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
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116 display "SH on-chip platform clock controls"
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117 description "
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118 The various clocks used by the system are derived from
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119 these options."
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120 flavor none
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121 no_define
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122
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123 cdl_option CYGHWR_HAL_SH_OOC_XTAL {
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124 display "SH clock crystal"
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125 flavor data
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126 legal_values 9000000 to 66000000
136
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127 default_value 33333333
134
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128 no_define
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129 description "
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130 This option specifies the frequency of the crystal all
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131 other clocks are derived from."
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132 }
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133
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134 cdl_option CYGHWR_HAL_SH_OOC_CKIO {
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135 display "SH clock CKIO output enable"
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136 default_value 1
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137 description "
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138 This selects whether CKIO output is enabled."
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139 }
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140
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141 cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
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142 display "SH clock PLL circuit 1"
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143 flavor data
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144 default_value 6
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145 legal_values { 0 6 }
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146 description "
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147 This selects whether PLL1 is enabled."
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148 }
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149
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150 cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
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151 display "SH clock PLL circuit 2"
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152 flavor data
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153 default_value 1
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154 legal_values { 0 1 }
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155 description "
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156 This selects whether PLL2 is enabled."
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157 }
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158
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159 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC {
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160 display "SH clock divider, core"
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161 flavor data
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162 default_value 1
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163 legal_values { 1 2 3 4 6 8 }
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164 description "
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165 This divider option affects the CPU core clock."
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166 }
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167
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168 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC {
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169 display "SH clock divider, bus"
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170 flavor data
136
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171 default_value 3
134
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172 legal_values { 1 2 3 4 6 8 }
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173 description "
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174 This divider option affects the bus clock."
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175 }
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176
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177 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC {
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178 display "SH clock divider, peripheral"
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179 flavor data
136
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180 default_value 6
134
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181 legal_values { 1 2 3 4 6 8 }
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182 description "
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183 This divider option affects the peripheral clock."
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184 }
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185
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186 cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
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187 display "SH clock mode"
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188 flavor data
136
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189 default_value 5
134
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190 legal_values { 0 1 2 3 4 5 }
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191 description "
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192 This option must mirror the clock mode hardwired on
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193 the MD0-MD2 pins of the CPU in order to correctly
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194 initialize the FRQCR register."
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195 }
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196 }
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197
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198 cdl_component CYGBLD_GLOBAL_OPTIONS {
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199 display "Global build options"
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200 flavor none
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201 parent CYGPKG_NONE
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202 description "
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203 Global build options including control over
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204 compiler flags, linker flags and choice of toolchain."
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205
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206
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207 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
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208 display "Global command prefix"
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209 flavor data
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210 no_define
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211 default_value { "sh-elf" }
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212 description "
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213 This option specifies the command prefix used when
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214 invoking the build tools."
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215 }
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216
136
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217 # CPU flags should be -m4-nofpu
134
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218 cdl_option CYGBLD_GLOBAL_CFLAGS {
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219 display "Global compiler flags"
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220 flavor data
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221 no_define
136
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222 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
134
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223 description "
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224 This option controls the global compiler flags which
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225 are used to compile all packages by
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226 default. Individual packages may define
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227 options which override these global flags."
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228 }
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229
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230 cdl_option CYGBLD_GLOBAL_LDFLAGS {
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231 display "Global linker flags"
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232 flavor data
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233 no_define
136
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234 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
134
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235 description "
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236 This option controls the global linker flags. Individual
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237 packages may define options which override these global flags."
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238 }
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239
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240 cdl_option CYGBLD_BUILD_GDB_STUBS {
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241 display "Build GDB stub ROM image"
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242 default_value 0
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243 requires { CYG_HAL_STARTUP == "ROM" }
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244 requires CYGSEM_HAL_ROM_MONITOR
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245 requires CYGBLD_BUILD_COMMON_GDB_STUBS
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246 requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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247 requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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248 requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
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249 requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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250 requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
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251 no_define
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252 description "
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253 This option enables the building of the GDB stubs for the
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254 board. The common HAL controls takes care of most of the
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255 build process, but the final conversion from ELF image to
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256 binary data is handled by the platform CDL, allowing
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257 relocation of the data if necessary."
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258
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259 make -priority 320 {
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260 <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
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261 $(OBJCOPY) -O binary $< $@
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262 }
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263 }
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264 }
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265
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266 cdl_component CYGHWR_MEMORY_LAYOUT {
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267 display "Memory layout"
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268 flavor data
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269 no_define
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270 calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh7750_cq7750_ram" : \
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271 "sh_sh7750_cq7750_rom" }
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272
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273 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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274 display "Memory layout linker script fragment"
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275 flavor data
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276 no_define
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277 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
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278 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7750_cq7750_ram.ldi>" : \
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279 "<pkgconf/mlt_sh_sh7750_cq7750_rom.ldi>" }
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280 }
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281
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282 cdl_option CYGHWR_MEMORY_LAYOUT_H {
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283 display "Memory layout header file"
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284 flavor data
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285 no_define
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286 define -file system.h CYGHWR_MEMORY_LAYOUT_H
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287 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh7750_cq7750_ram.h>" : \
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288 "<pkgconf/mlt_sh_sh7750_cq7750_rom.h>" }
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289 }
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290 }
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291
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292 cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
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293 display "Work with a ROM monitor"
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294 flavor booldata
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295 legal_values { "GDB_stubs" }
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296 default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
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297 requires { CYG_HAL_STARTUP == "RAM" }
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298 parent CYGPKG_HAL_ROM_MONITOR
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299 requires !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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300 description "
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301 Support can be enabled for boot ROMs or ROM monitors which contain
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302 GDB stubs. This support changes various eCos semantics such as
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303 the encoding of diagnostic output, and the overriding of hardware
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304 interrupt vectors."
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305 }
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306
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307 cdl_option CYGSEM_HAL_ROM_MONITOR {
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308 display "Behave as a ROM monitor"
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309 flavor bool
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310 default_value 0
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311 parent CYGPKG_HAL_ROM_MONITOR
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312 requires { CYG_HAL_STARTUP == "ROM" }
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313 description "
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314 Enable this option if this program is to be used as a ROM monitor,
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315 i.e. applications will be loaded into RAM on the board, and this
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316 ROM monitor may process exceptions or interrupts generated from the
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317 application. This enables features such as utilizing a separate
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318 interrupt stack when exceptions are generated."
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319 }
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320 }