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annotate packages/devs/eth/cl/cs8900a/current/src/if_cs8900a.c @ 219:ae8511176102

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Fix CDL dependencies for stand-alone/system operation.
author gthomas
date Fri, 14 Jun 2002 22:00:56 +0000
parents 94b558c9fb67
children 01d8c3c977d9
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1 //==========================================================================
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2 //
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3 // dev/if_cs8900a.c
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4 //
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5 // Device driver for Cirrus Logic CS8900A ethernet controller
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license/
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
196
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40 //####BSDCOPYRIGHTBEGIN####
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41 //
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42 // -------------------------------------------
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43 //
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44 // Portions of this software may have been derived from OpenBSD or other sources,
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45 // and are covered by the appropriate copyright disclaimers included herein.
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46 //
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47 // -------------------------------------------
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48 //
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49 //####BSDCOPYRIGHTEND####
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50 //==========================================================================
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51 //#####DESCRIPTIONBEGIN####
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52 //
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53 // Author(s): gthomas
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54 // Contributors: gthomas, jskov
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55 // Date: 2001-11-02
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56 // Purpose:
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57 // Description: Driver for CS8900 ethernet controller
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58 //
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59 // Note: Platform can define CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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60 // to get a timer thread polling instead of interupt based
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61 // operation.
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62 //
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63 // Note: Driver will need some changes to support multiple instances
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64 //
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65 //####DESCRIPTIONEND####
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66 //
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67 //==========================================================================
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68
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69 #include <pkgconf/system.h>
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70 #ifdef CYGPKG_KERNEL
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71 #include <cyg/kernel/kapi.h>
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72 #endif
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73 #include <pkgconf/io_eth_drivers.h>
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74
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75 #include <cyg/infra/cyg_type.h>
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76 #include <cyg/hal/hal_arch.h>
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77 #include <cyg/hal/hal_intr.h>
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78 #include <cyg/infra/diag.h>
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79 #include <cyg/hal/drv_api.h>
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80 #undef __ECOS
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81 #define __ECOS
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82 #include <cyg/io/eth/eth_drv.h>
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83 #include <cyg/io/eth/netdev.h>
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84
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85 #include <cyg/io/cs8900.h>
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86
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87 #define __WANT_DEVS
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88 #include CYGDAT_DEVS_ETH_CL_CS8900A_INL
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89 #undef __WANT_DEVS
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90
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91 // NOINTS operation only relevant when the NET package is loaded
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92 #if !defined(CYGPKG_NET) || !defined(CYGPKG_KERNEL)
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93 # undef CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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94 #endif
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95
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96 #ifdef CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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97 #define STACK_SIZE CYGNUM_HAL_STACK_SIZE_MINIMUM
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98 static char cs8900a_fake_int_stack[STACK_SIZE];
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99 static cyg_thread cs8900a_fake_int_thread_data;
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100 static cyg_handle_t cs8900a_fake_int_thread_handle;
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101 static void cs8900a_fake_int(cyg_addrword_t);
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102 #endif
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103
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104 #ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
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105 extern int cyg_io_eth_net_debug;
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106 #endif
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107
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108 static void cs8900a_poll(struct eth_drv_sc *sc);
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109 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
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110 // This ISR is called when the ethernet interrupt occurs
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111 static int
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112 cs8900a_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
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113 {
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114 cs8900a_priv_data_t* cpd = (cs8900a_priv_data_t *)data;
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115 cyg_drv_interrupt_mask(cpd->interrupt);
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116 cyg_drv_interrupt_acknowledge(cpd->interrupt);
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117 return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
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118 }
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119
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120 static void
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121 cs8900a_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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122 {
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123 // This conditioning out is necessary because of explicit calls to this
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124 // DSR - which would not ever be called in the case of a polled mode
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125 // usage ie. in RedBoot.
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126 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
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127 cs8900a_priv_data_t* cpd = (cs8900a_priv_data_t *)data;
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128 struct cyg_netdevtab_entry *ndp = (struct cyg_netdevtab_entry *)(cpd->tab);
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129 struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
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130
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131 DEBUG_FUNCTION();
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132
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133 // but here, it must be a *sc:
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134 eth_drv_dsr( vector, count, (cyg_addrword_t)sc );
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135 #else
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136 # ifndef CYGPKG_REDBOOT
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137 # error Empty CS8900A ethernet DSR is compiled. Is this what you want?
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138 # endif
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139 #endif
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140 }
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141 #endif
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142
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143 // The deliver function (ex-DSR) handles the ethernet [logical] processing
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144 static void
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145 cs8900a_deliver(struct eth_drv_sc *sc)
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146 {
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147 cs8900a_poll(sc);
212
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148 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
196
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149 {
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150 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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151 // Allow interrupts to happen again
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152 cyg_drv_interrupt_unmask(cpd->interrupt);
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153 }
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154 #endif
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155 }
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156
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157 static int
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158 cs8900a_int_vector(struct eth_drv_sc *sc)
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159 {
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160 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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161 return (cpd->interrupt) ? 1 : 0;
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162 }
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163
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164 static bool
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165 cs8900a_init(struct cyg_netdevtab_entry *tab)
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166 {
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167 struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
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168 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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169 cyg_addrword_t base = cpd->base;
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170 cyg_uint16 chip_type, chip_rev, chip_status;
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171 int i;
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172 long timeout = 500000;
197
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173 cyg_bool esa_configured = false;
196
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174
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175 cpd->tab = tab;
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176
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177 CYGHWR_CL_CS8900A_PLF_INIT(cpd);
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178
212
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179 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
196
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180 // Initialize environment, setup interrupt handler
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181 cyg_drv_interrupt_create(cpd->interrupt,
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182 0, // Priority - what goes here?
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183 (cyg_addrword_t)cpd, // Data item passed to interrupt handler
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184 (cyg_ISR_t *)cs8900a_isr,
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185 (cyg_DSR_t *)cs8900a_dsr,
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186 &cpd->interrupt_handle,
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187 &cpd->interrupt_object);
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188 cyg_drv_interrupt_attach(cpd->interrupt_handle);
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189 cyg_drv_interrupt_acknowledge(cpd->interrupt);
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190 cyg_drv_interrupt_unmask(cpd->interrupt);
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191
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192 #ifdef CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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193 cyg_thread_create(1, // Priority
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194 cs8900a_fake_int, // entry
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195 (cyg_addrword_t)sc, // entry parameter
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196 "CS8900 int", // Name
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197 &cs8900a_fake_int_stack[0], // Stack
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198 STACK_SIZE, // Size
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199 &cs8900a_fake_int_thread_handle, // Handle
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200 &cs8900a_fake_int_thread_data // Thread data structure
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201 );
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202 cyg_thread_resume(cs8900a_fake_int_thread_handle); // Start it
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203 #endif
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204 #endif
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205
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206 // Read controller ID - the first is a dummy read, since (on some
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207 // platforms) the first access to the controller seems to skip the
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208 // MSB 8 bits.
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209 get_reg(base, PP_ChipID);
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210 chip_type = get_reg(base, PP_ChipID);
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211 chip_rev = get_reg(base, PP_ChipRev);
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212 #if DEBUG & 8
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213 diag_printf("CS8900A[%p] - type: 0x%04x, rev: 0x%04x\n", base, chip_type, chip_rev);
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214 #endif
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215 if (chip_type != 0x630e) {
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216 #if DEBUG & 8
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217 diag_printf("CS8900 - invalid type (0x%04x), must be 0x630e\n", chip_type);
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218 #endif
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219 return false;
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220 }
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221
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222 CYGHWR_CL_CS8900A_PLF_RESET(base);
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223 put_reg(base, PP_SelfCtl, PP_SelfCtl_Reset); // Reset chip
208
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224
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225 CYGHWR_CL_CS8900A_PLF_POST_RESET(base);
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226
196
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227 while ((get_reg(base, PP_SelfStat) & PP_SelfStat_InitD) == 0) {
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228 if (--timeout <= 0) {
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229 #if DEBUG & 8
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230 diag_printf("CS8900 didn't reset - abort!\n");
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231 #endif
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232 return false;
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233 }
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234 }
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235
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236 chip_status = get_reg(base, PP_SelfStat);
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237 #if DEBUG & 8
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238 diag_printf("CS8900 - status: 0x%04x (%sEEPROM present)\n", chip_status,
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239 chip_status & PP_SelfStat_EEPROM ? "" : "no ");
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240 #endif
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241
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242
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243 // Disable reception whilst finding the ESA
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244 put_reg(base, PP_LineCTL, 0 );
197
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245 // Find ESA - check possible sources in sequence and stop when
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246 // one provides the ESA:
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247 // RedBoot option (via provide_esa)
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248 // Compile-time configuration
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249 // EEPROM
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250 // <fail configuration of device>
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251 if (NULL != cpd->provide_esa) {
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252 esa_configured = cpd->provide_esa(cpd);
196
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253 # if DEBUG & 8
197
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254 if (esa_configured)
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255 diag_printf("Got ESA from RedBoot option\n");
196
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256 # endif
197
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257 }
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258 if (!esa_configured && cpd->hardwired_esa) {
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259 // ESA is already set in cpd->esa[]
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260 esa_configured = true;
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261 }
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262 if (!esa_configured && (chip_status & PP_SelfStat_EEPROM)) {
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263 // Get ESA from EEPROM - via the PP_IA registers
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264 cyg_uint16 esa_word;
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265 for (i = 0; i < sizeof(cpd->esa); i += 2) {
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266 esa_word = get_reg(base, PP_IA+i);
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267 cpd->esa[i] = (esa_word & 0xFF);
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268 cpd->esa[i+1] = (esa_word >> 8) & 0xFF;
196
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269 }
197
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270 esa_configured = true;
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271 }
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272 if (!esa_configured) {
196
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273 # if DEBUG & 8
197
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274 diag_printf("CS8900 - no EEPROM, static ESA or RedBoot config option.\n");
196
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275 # endif
197
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276 return false;
196
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277 }
197
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278
196
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279 // Tell the chip what ESA to use
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280 for (i = 0; i < sizeof(cpd->esa); i += 2) {
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281 put_reg(base, PP_IA+i, cpd->esa[i] | (cpd->esa[i+1] << 8));
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282 }
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283 // Set logical address mask
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284 for (i = 0; i < 8; i += 2) {
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285 put_reg(base, PP_LAF+i, 0xFFFF);
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286 }
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287 # if DEBUG & 8
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288 diag_printf("ESA %02x:%02x:%02x:%02x:%02x:%02x\n",
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289 cpd->esa[0], cpd->esa[1], cpd->esa[2],
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290 cpd->esa[3], cpd->esa[4], cpd->esa[5]);
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291 # endif
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292
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293 // Initialize upper level driver
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294 (sc->funs->eth_drv->init)(sc, cpd->esa);
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295
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296 return true;
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297 }
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298
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299 static void
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300 cs8900a_stop(struct eth_drv_sc *sc)
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301 {
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302 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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303 cyg_addrword_t base = cpd->base;
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304
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305 put_reg(base, PP_LineCTL, 0);
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306 }
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307
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308 // This function is called to "start up" the interface. It may be called
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309 // multiple times, even when the hardware is already running. It will be
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310 // called whenever something "hardware oriented" changes and should leave
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311 // the hardware ready to send/receive packets.
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312 static void
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313 cs8900a_start(struct eth_drv_sc *sc, cyg_uint8 *esa, int flags)
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314 {
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315 cyg_uint16 stat;
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316 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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317 cyg_addrword_t base = cpd->base;
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318
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319 put_reg(base, PP_BusCtl, PP_BusCtl_MemoryE); // Disable interrupts, memory mode
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320 put_reg(base, PP_IntReg, PP_IntReg_IRQ0); // Only possibility
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321 put_reg(base, PP_RxCFG, PP_RxCFG_RxOK | PP_RxCFG_CRC |
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322 PP_RxCFG_RUNT | PP_RxCFG_EXTRA);
208
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323 cpd->rxmode = PP_RxCTL_RxOK | PP_RxCTL_Broadcast | PP_RxCTL_IA;
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324 put_reg(base, PP_RxCTL, cpd->rxmode);
196
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325 put_reg(base, PP_TxCFG, PP_TxCFG_TxOK | PP_TxCFG_Collision |
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326 PP_TxCFG_CRS | PP_TxCFG_SQE | PP_TxCFG_Late |
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327 PP_TxCFG_Jabber | PP_TxCFG_16Collisions);
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328 put_reg(base, PP_BufCFG, PP_BufCFG_TxRDY | PP_BufCFG_TxUE | PP_BufCFG_RxMiss |
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329 PP_BufCFG_TxCol | PP_BufCFG_Miss | PP_BufCFG_SWI);
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330 put_reg(base, PP_IntReg, PP_IntReg_IRQ0); // Only possibility
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331 put_reg(base, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
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332 // Clear Interrupt Status Queue before enabling interrupts
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333 do {
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334 HAL_READ_UINT16(cpd->base+CS8900A_ISQ, stat);
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335 } while (stat != 0) ;
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336 cpd->txbusy = false;
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337 put_reg(base, PP_BusCtl, PP_BusCtl_EnableIRQ);
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338 }
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339
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340 // This routine is called to perform special "control" opertions
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341 static int
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342 cs8900a_control(struct eth_drv_sc *sc, unsigned long key, void *data, int data_length)
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343 {
208
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344 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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345 cyg_addrword_t base = cpd->base;
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346 struct eth_drv_mc_list *mc_list = data;
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347
196
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348 switch (key) {
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349 case ETH_DRV_SET_MAC_ADDRESS:
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350 return 0;
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351 break;
208
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352 case ETH_DRV_SET_MC_LIST:
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353 case ETH_DRV_SET_MC_ALL:
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354 // Note: this code always accepts all multicast addresses if any
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355 // are desired. It would be possible to accept a subset by adjusting
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356 // the Logical Address Filter (LAF), but that would require scanning
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357 // this list and building a suitable mask.
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358 if (mc_list->len) {
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359 cpd->rxmode |= PP_RxCTL_Multicast;
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360 } else {
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361 cpd->rxmode &= ~PP_RxCTL_Multicast;
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362 }
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363 put_reg(base, PP_RxCTL, cpd->rxmode); // When is it safe to do this?
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364 return 0;
196
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365 default:
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366 return 1;
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367 break;
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368 }
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369 }
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370
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371 // This routine is called to see if it is possible to send another packet.
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372 // It will return non-zero if a transmit is possible, zero otherwise.
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373 static int
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374 cs8900a_can_send(struct eth_drv_sc *sc)
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375 {
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376 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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377 cyg_addrword_t base = cpd->base;
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378 cyg_uint16 stat;
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379
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380 stat = get_reg(base, PP_LineStat);
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381 if ((stat & PP_LineStat_LinkOK) == 0) {
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382 return false; // Link not connected
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383 }
212
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384 #ifdef CYGPKG_KERNEL
196
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385 // Horrible hack!
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386 if (cpd->txbusy) {
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387 cyg_tick_count_t now = cyg_current_time();
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388 if ((now - cpd->txstart) > 25) {
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389 // 250ms is more than enough to transmit one frame
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390 #if DEBUG & 1
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391 diag_printf("CS8900: Tx interrupt lost\n");
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392 #endif
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393 cpd->txbusy = false;
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394 // Free up the buffer (with error indication)
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395 (sc->funs->eth_drv->tx_done)(sc, cpd->txkey, 1);
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396 }
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397 }
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398 #endif
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399 return (cpd->txbusy == false);
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400 }
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401
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402 // This routine is called to send data to the hardware.
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403 static void
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404 cs8900a_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
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405 int total_len, unsigned long key)
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406 {
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407 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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408 cyg_addrword_t base = cpd->base;
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409 int i;
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410 int len;
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411 cyg_uint8 *data;
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412 cyg_uint16 saved_data = 0, *sdata;
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413 cyg_uint16 stat;
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414 bool odd_byte = false;
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415
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416 // Mark xmitter busy
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417 cpd->txbusy = true;
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418 cpd->txkey = key;
212
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diff changeset
419 #ifdef CYGPKG_KERNEL
196
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420 cpd->txstart = cyg_current_time();
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421 #endif
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422 // Start the xmit sequence
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423
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424 // The hardware indicates that there are options as to when the actual
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425 // packet transmission will start wrt moving of data into the transmit
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426 // buffer. However, impirical results seem to indicate that if the
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diff changeset
427 // packet is large and transmission is allowed to start before the
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428 // entire packet has been pushed into the buffer, the hardware gets
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429 // confused and the packet is lost, along with a "lost" Tx interrupt.
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430 // This may be a case of the copy loop below being interrupted, e.g.
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431 // a system timer interrupt, and the hardware getting unhappy that
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432 // not all of the data was provided before the transmission should
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433 // have completed (i.e. buffer underrun).
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434 // For now, the solution is to not allow this overlap.
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435 //HAL_WRITE_UINT16(cpd->base+CS8900A_TxCMD, PP_TxCmd_TxStart_5)
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436
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437 // Start only when all data sent to chip
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438 HAL_WRITE_UINT16(cpd->base+CS8900A_TxCMD, PP_TxCmd_TxStart_Full);
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439
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440 HAL_WRITE_UINT16(cpd->base+CS8900A_TxLEN, total_len);
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441 // Wait for controller ready signal
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442 do {
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443 stat = get_reg(base, PP_BusStat);
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444 } while (!(stat & PP_BusStat_TxRDY));
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445
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446 // Put data into buffer
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447 for (i = 0; i < sg_len; i++) {
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448 data = (cyg_uint8 *)sg_list[i].buf;
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449 len = sg_list[i].len;
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450
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451 if (len > 0) {
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452 /* Finish the last word. */
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453 if (odd_byte) {
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454 saved_data |= ((cyg_uint16)*data++) << 8;
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455 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, saved_data);
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456 len--;
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457 odd_byte = false;
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458 }
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459 /* Output contiguous words. */
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460 sdata = (cyg_uint16 *)data;
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461 while (len > 1) {
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462 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, *sdata++);
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463 len -= sizeof(cyg_uint16);
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464 }
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465 /* Save last byte, if necessary. */
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466 if (len == 1) {
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467 data = (cyg_uint8 *)sdata;
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468 saved_data = (cyg_uint16)*data;
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469 odd_byte = true;
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470 }
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471 }
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472 }
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473 if (odd_byte) {
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474 HAL_WRITE_UINT16(cpd->base+CS8900A_RTDATA, saved_data);
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475 }
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476 }
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477
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478 // This function is called when a packet has been received. It's job is
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479 // to prepare to unload the packet from the hardware. Once the length of
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480 // the packet is known, the upper layer of the driver can be told. When
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481 // the upper layer is ready to unload the packet, the internal function
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482 // 'cs8900a_recv' will be called to actually fetch it from the hardware.
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483 static void
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484 cs8900a_RxEvent(struct eth_drv_sc *sc)
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485 {
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486 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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487 cyg_addrword_t base = cpd->base;
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488 cyg_uint16 stat, len;
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489
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490 HAL_READ_UINT16(base+CS8900A_RTDATA, stat);
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491 HAL_READ_UINT16(base+CS8900A_RTDATA, len);
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492 #ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
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493 if (cyg_io_eth_net_debug) {
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494 diag_printf("RxEvent - stat: %x, len: %d\n", stat, len);
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495 }
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496 #endif
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497 (sc->funs->eth_drv->recv)(sc, len);
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498 }
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499
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500 // This function is called as a result of the "eth_drv_recv()" call above.
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501 // It's job is to actually fetch data for a packet from the hardware once
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diff changeset
502 // memory buffers have been allocated for the packet. Note that the buffers
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diff changeset
503 // may come in pieces, using a scatter-gather list. This allows for more
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diff changeset
504 // efficient processing in the upper layers of the stack.
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505 static void
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diff changeset
506 cs8900a_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
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507 {
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508 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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509 cyg_addrword_t base = cpd->base;
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diff changeset
510 int i, mlen;
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511 cyg_uint16 *data, val;
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512 cyg_uint8 *cp, cval;
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diff changeset
513
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514 for (i = 0; i < sg_len; i++) {
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515 data = (cyg_uint16 *)sg_list[i].buf;
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516 mlen = sg_list[i].len;
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517 while (mlen >= sizeof(*data)) {
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518 HAL_READ_UINT16(base+CS8900A_RTDATA, val);
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519 if (data) {
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520 *data++ = val;
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521 }
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522 mlen -= sizeof(*data);
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523 }
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524 if (mlen) {
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525 // Fetch last odd byte
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526 HAL_READ_UINT16(base+CS8900A_RTDATA, cval);
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527 cval &= 0xFF;
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528 if ((cp = (cyg_uint8 *)data) != 0) {
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529 *cp = cval;
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530 }
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diff changeset
531 }
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532 }
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533 }
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534
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535 static void
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536 cs8900a_TxEvent(struct eth_drv_sc *sc, int stat)
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537 {
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538 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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539 cyg_addrword_t base = cpd->base;
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540
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541 stat = get_reg(base, PP_TER);
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542 #ifdef CYGDBG_IO_ETH_DRIVERS_DEBUG
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543 if (cyg_io_eth_net_debug) {
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544 diag_printf("Tx event: %x\n", stat);
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545 }
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546 #endif
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547 cpd->txbusy = false;
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548 (sc->funs->eth_drv->tx_done)(sc, cpd->txkey, 0);
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549 }
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550
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551 static void
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552 cs8900a_BufEvent(struct eth_drv_sc *sc, int stat)
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553 {
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554 if (stat & PP_BufCFG_RxMiss) {
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555 }
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556 if (stat & PP_BufCFG_TxUE) {
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557 }
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558 }
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559
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560 static void
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561 cs8900a_poll(struct eth_drv_sc *sc)
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562 {
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563 cyg_uint16 event;
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564 cs8900a_priv_data_t *cpd = (cs8900a_priv_data_t *)sc->driver_private;
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565 cyg_addrword_t base = cpd->base;
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566
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567 HAL_READ_UINT16(base+CS8900A_ISQ, event);
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568 while (event != 0) {
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569 switch (event & ISQ_EventMask) {
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570 case ISQ_RxEvent:
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571 cs8900a_RxEvent(sc);
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572 break;
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573 case ISQ_TxEvent:
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574 cs8900a_TxEvent(sc, event);
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575 break;
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576 case ISQ_BufEvent:
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577 cs8900a_BufEvent(sc, event);
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578 break;
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579 case ISQ_RxMissEvent:
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580 // Receive miss counter has overflowed
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581 break;
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582 case ISQ_TxColEvent:
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583 // Transmit collision counter has overflowed
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584 break;
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585 default:
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586 #if DEBUG & 1
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587 diag_printf("%s: Unknown event: %x\n", __FUNCTION__, event);
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588 #endif
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589 break;
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590 }
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591 HAL_READ_UINT16(base+CS8900A_ISQ, event);
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592 }
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593
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594 CYGHWR_CL_CS8900A_PLF_INT_CLEAR(cpd);
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595 }
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596
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597 #ifdef CYGSEM_DEVS_ETH_CL_CS8900A_NOINTS
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598 void
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599 cs8900a_fake_int(cyg_addrword_t param)
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600 {
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601 struct eth_drv_sc *sc = (struct eth_drv_sc *) param;
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602 int s;
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603
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604 #if DEBUG & 1
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605 diag_printf("cs8900a_fake_int()\n");
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606 #endif
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607
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608 while (true) {
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609 cyg_thread_delay(5);
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610 s = splnet();
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611 cs8900a_poll(sc);
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612 splx(s);
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613 }
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614 }
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615 #endif