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annotate packages/hal/mips/arch/current/include/mips-regs.h @ 64:c38311975d4f ecos-sw-2000-01-28

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Merge from eCos master repository on 2000-01-28-04:28:11-GMT
author jlarmour
date Fri, 28 Jan 2000 04:59:39 +0000
parents 4741a3c3496a
children bf00f99aec69
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64
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1 #ifndef CYGONCE_HAL_MIPS_REGS_H
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2 #define CYGONCE_HAL_MIPS_REGS_H
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3 //========================================================================
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4 //
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5 // mips-regs.h
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6 //
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7 // Register defines for MIPS processors
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8 //
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9 //========================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.0 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://sourceware.cygnus.com/ecos
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17 //
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18 // Software distributed under the License is distributed on an
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //========================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): Red Hat, nickg
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37 // Contributors: Red Hat, nickg
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38 // Date: 1998-06-08
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39 // Purpose:
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40 // Description: Register defines for MIPS processors
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41 // Usage:
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42 //
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43 //####DESCRIPTIONEND####
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44 //
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45 //========================================================================
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46
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47 #include <pkgconf/hal.h>
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48
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49 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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50
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51 /* This value must agree with NUMREGS in mips-stub.h. */
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52
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53 #define NUM_REGS 90
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54
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55 #ifdef __mips64
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56 #define REG_SIZE 8
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57 #else
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58 #define REG_SIZE 4
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59 #endif
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60
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61 /* General register names for assembly code. */
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62
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63 #define zero $0
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64 #define at $1 /* assembler temporary */
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65 #define v0 $2 /* value holders */
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66 #define v1 $3
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67 #define a0 $4 /* arguments */
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68 #define a1 $5
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69 #define a2 $6
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70 #define a3 $7
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71 #define t0 $8 /* temporaries */
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72 #define t1 $9
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73 #define t2 $10
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74 #define t3 $11
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75 #define t4 $12
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76 #define t5 $13
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77 #define t6 $14
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78 #define t7 $15
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79 #define s0 $16 /* saved registers */
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80 #define s1 $17
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81 #define s2 $18
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82 #define s3 $19
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83 #define s4 $20
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84 #define s5 $21
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85 #define s6 $22
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86 #define s7 $23
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87 #define t8 $24 /* temporaries */
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88 #define t9 $25
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89 #define k0 $26 /* kernel registers */
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90 #define k1 $27
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91 #define gp $28 /* global pointer */
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92 #define sp $29 /* stack pointer */
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93 #define s8 $30 /* saved register */
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94 #define fp $30 /* frame pointer (obsolete usage) */
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95 #define ra $31 /* return address */
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96
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97 /* MIPS registers, numbered in the order in which gdb expects to see them. */
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98 #define ZERO 0
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99 #define AT 1
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100 #define V0 2
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101 #define V1 3
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102 #define A0 4
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103 #define A1 5
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104 #define A2 6
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105 #define A3 7
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106
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107 #define T0 8
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108 #define T1 9
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109 #define T2 10
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110 #define T3 11
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111 #define T4 12
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112 #define T5 13
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113 #define T6 14
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114 #define T7 15
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115
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116 #define S0 16
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117 #define S1 17
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118 #define S2 18
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119 #define S3 19
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120 #define S4 20
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121 #define S5 21
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122 #define S6 22
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123 #define S7 23
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124
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125 #define T8 24
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126 #define T9 25
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127 #define K0 26
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128 #define K1 27
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129 #define GP 28
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130 #define SP 29
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131 #define S8 30
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132 #define RA 31
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133
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134 #define SR 32
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135 #define LO 33
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136 #define HI 34
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137 #define BAD_VA 35
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138 #define CAUSE 36
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139 #define PC 37
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140
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141 #define F0 38
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142 #define F1 39
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143 #define F2 40
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144 #define F3 41
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145 #define F4 42
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146 #define F5 43
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147 #define F6 44
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148 #define F7 45
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149 #define F8 46
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150 #define F9 47
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151 #define F10 48
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152 #define F11 49
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153 #define F12 50
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154 #define F13 51
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155 #define F14 52
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156 #define F15 53
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157 #define F16 54
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158 #define F17 55
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159 #define F18 56
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160 #define F19 57
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161 #define F20 58
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162 #define F21 59
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163 #define F22 60
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164 #define F23 61
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165 #define F24 62
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166 #define F25 63
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167 #define F26 64
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168 #define F27 65
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169 #define F28 66
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170 #define F29 67
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171 #define F30 68
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172 #define F31 69
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173
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174 #define FCR31 70
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175
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176 /* System Control Coprocessor (CP0) exception processing registers */
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177 #define C0_CONTEXT $4 /* Context */
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178 #define C0_BADVADDR $8 /* Bad Virtual Address */
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179 #define C0_COUNT $9 /* Count */
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180 #define C0_COMPARE $11 /* Compare */
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181 #define C0_STATUS $12 /* Processor Status */
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182 #define C0_CAUSE $13 /* Exception Cause */
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183 #define C0_EPC $14 /* Exception PC */
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184 #define C0_XCONTEXT $20 /* XContext */
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185 #define C0_ECC $26 /* ECC */
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186 #define C0_CACHEERR $27 /* CacheErr */
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187 #define C0_ERROREPC $30 /* ErrorEPC */
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188
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189 /* Status register fields */
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190 #define SR_CUMASK 0xf0000000 /* Coprocessor usable bits */
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191 #define SR_CU3 0x80000000 /* Coprocessor 3 usable */
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192 #define SR_CU2 0x40000000 /* coprocessor 2 usable */
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193 #define SR_CU1 0x20000000 /* Coprocessor 1 usable */
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194 #define SR_CU0 0x10000000 /* Coprocessor 0 usable */
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195
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196 #define SR_FR 0x04000000 /* Enable 32 floating-point registers */
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197 #define SR_RE 0x02000000 /* Reverse Endian in user mode */
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198
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199 #define SR_BEV 0x00400000 /* Bootstrap Exception Vector */
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200 #define SR_TS 0x00200000 /* TLB shutdown (reserved on R4600) */
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201 #define SR_SR 0x00100000 /* Soft Reset */
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202
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203 #define SR_CH 0x00040000 /* Cache Hit */
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204 #define SR_CE 0x00020000 /* ECC register modifies check bits */
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205 #define SR_DE 0x00010000 /* Disable cache errors */
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206
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207 #define SR_IMASK 0x0000ff00 /* Interrupt Mask */
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208 #define SR_IMASK8 0x00000000 /* Interrupt Mask level=8 */
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209 #define SR_IMASK7 0x00008000 /* Interrupt Mask level=7 */
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210 #define SR_IMASK6 0x0000c000 /* Interrupt Mask level=6 */
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211 #define SR_IMASK5 0x0000e000 /* Interrupt Mask level=5 */
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212 #define SR_IMASK4 0x0000f000 /* Interrupt Mask level=4 */
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213 #define SR_IMASK3 0x0000f800 /* Interrupt Mask level=3 */
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214 #define SR_IMASK2 0x0000fc00 /* Interrupt Mask level=2 */
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215 #define SR_IMASK1 0x0000fe00 /* Interrupt Mask level=1 */
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216 #define SR_IMASK0 0x0000ff00 /* Interrupt Mask level=0 */
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217
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218 #define SR_IBIT8 0x00008000 /* (Intr5) */
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219 #define SR_IBIT7 0x00004000 /* (Intr4) */
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220 #define SR_IBIT6 0x00002000 /* (Intr3) */
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221 #define SR_IBIT5 0x00001000 /* (Intr2) */
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222 #define SR_IBIT4 0x00000800 /* (Intr1) */
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223 #define SR_IBIT3 0x00000400 /* (Intr0) */
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224 #define SR_IBIT2 0x00000200 /* (Software Interrupt 1) */
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225 #define SR_IBIT1 0x00000100 /* (Software Interrupt 0) */
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226
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227 #define SR_KX 0x00000080 /* xtlb in kernel mode */
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228 #define SR_SX 0x00000040 /* mips3 & xtlb in supervisor mode */
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229 #define SR_UX 0x00000020 /* mips3 & xtlb in user mode */
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230
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231 #define SR_KSU_MASK 0x00000018 /* ksu mode mask */
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232 #define SR_KSU_USER 0x00000010 /* user mode */
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233 #define SR_KSU_SUPV 0x00000008 /* supervisor mode */
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234 #define SR_KSU_KERN 0x00000000 /* kernel mode */
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235
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236 #define SR_ERL 0x00000004 /* error level */
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237 #define SR_EXL 0x00000002 /* exception level */
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238 #define SR_IE 0x00000001 /* interrupt enable */
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239
26
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240 /* Floating-point unit control/status register (FCR31) */
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241 #define FCR31_FS 0x01000000 /* Flush denormalized to zero */
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242 #define FCR31_C 0x00800000 /* FP compare result */
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243
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244 #define FCR31_CAUSE_E 0x00020000 /* Cause - unimplemented operation */
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245 #define FCR31_CAUSE_V 0x00010000 /* Cause - invalid operation */
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246 #define FCR31_CAUSE_Z 0x00008000 /* Cause - division by zero */
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247 #define FCR31_CAUSE_O 0x00004000 /* Cause - overflow */
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248 #define FCR31_CAUSE_U 0x00002000 /* Cause - underflow */
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249 #define FCR31_CAUSE_I 0x00001000 /* Cause - inexact operation */
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250
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251 #define FCR31_ENABLES_V 0x00000800 /* Enables - invalid operation */
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252 #define FCR31_ENABLES_Z 0x00000400 /* Enables - division by zero */
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253 #define FCR31_ENABLES_O 0x00000200 /* Enables - overflow */
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254 #define FCR31_ENABLES_U 0x00000100 /* Enables - underflow */
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255 #define FCR31_ENABLES_I 0x00000080 /* Enables - inexact operation */
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256
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257 #define FCR31_FLAGS_V 0x00000040 /* Flags - invalid operation */
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258 #define FCR31_FLAGS_Z 0x00000020 /* Flags - division by zero */
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259 #define FCR31_FLAGS_O 0x00000010 /* Flags - overflow */
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260 #define FCR31_FLAGS_U 0x00000008 /* Flags - underflow */
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261 #define FCR31_FLAGS_I 0x00000004 /* Flags - inexact operation */
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262
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263 #define FCR31_RMMASK 0x00000002 /* Rounding mode mask */
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264 #define FCR31_RM_RN 0 /* Round to nearest */
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265 #define FCR31_RM_RZ 1 /* Round to zero */
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266 #define FCR31_RM_RP 2 /* Round to +infinity */
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267 #define FCR31_RM_RM 3 /* Round to -infinity */
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268
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269
0
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270 /* Cause register fields */
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271 #define CAUSE_BD 0x80000000 /* Branch Delay */
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272 #define CAUSE_CEMASK 0x30000000 /* Coprocessor Error */
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273 #define CAUSE_CESHIFT 28 /* Right justify CE */
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274 #define CAUSE_IPMASK 0x0000ff00 /* Interrupt Pending */
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275 #define CAUSE_IPSHIFT 8 /* Right justify IP */
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276 #define CAUSE_IP8 0x00008000 /* (Intr5) */
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277 #define CAUSE_IP7 0x00004000 /* (Intr4) */
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278 #define CAUSE_IP6 0x00002000 /* (Intr3) */
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279 #define CAUSE_IP5 0x00001000 /* (Intr2) */
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280 #define CAUSE_IP4 0x00000800 /* (Intr1) */
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281 #define CAUSE_IP3 0x00000400 /* (Intr0) */
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282 #define CAUSE_SW2 0x00000200 /* (Software Interrupt 1) */
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283 #define CAUSE_SW1 0x00000100 /* (Software Interrupt 0) */
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284 #define CAUSE_EXCMASK 0x0000007c /* Exception Code */
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285 #define CAUSE_EXCSHIFT 2 /* Right justify EXC */
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286
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287 /* Exception Codes */
2
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288 #define EXC_INT 0 /* External interrupt */
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289 #define EXC_MOD 1 /* TLB modification exception */
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290 #define EXC_TLBL 2 /* TLB miss (Load or Ifetch) */
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291 #define EXC_TLBS 3 /* TLB miss (Store) */
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292 #define EXC_ADEL 4 /* Address error (Load or Ifetch) */
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293 #define EXC_ADES 5 /* Address error (Store) */
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294 #define EXC_IBE 6 /* Bus error (Ifetch) */
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295 #define EXC_DBE 7 /* Bus error (data load or store) */
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296 #define EXC_SYS 8 /* System call */
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297 #define EXC_BP 9 /* Break point */
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298 #define EXC_RI 10 /* Reserved instruction */
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299 #define EXC_CPU 11 /* Coprocessor unusable */
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300 #define EXC_OVF 12 /* Arithmetic overflow */
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301 #define EXC_TRAP 13 /* Trap exception */
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302 #define EXC_FPE 15 /* Floating Point Exception */
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303
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304 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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305
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306 #endif // ifndef CYGONCE_HAL_MIPS_REGS_H