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annotate packages/hal/sh/sh3/current/src/var_misc.c @ 172:cd45958b28ff

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Merge from eCos master repository on 2001-07-20-10:24:43-BST
author jlarmour
date Fri, 20 Jul 2001 10:23:16 +0000
parents d63db767121d
children 022f1e506033
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1 //==========================================================================
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2 //
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3 // var_misc.c
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4 //
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5 // HAL miscellaneous functions
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors: jskov, jlarmour, nickg
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36 // Date: 1999-04-03
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37 // Purpose: HAL miscellaneous functions
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38 // Description: This file contains miscellaneous functions provided by the
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39 // HAL.
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40 //
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41 //####DESCRIPTIONEND####
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42 //
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43 //===========================================================================
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44
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45 #include <pkgconf/hal.h>
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46
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47 #include <cyg/infra/cyg_type.h>
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48 #include <cyg/infra/cyg_trac.h> // tracing macros
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49 #include <cyg/infra/cyg_ass.h> // assertion macros
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50 #include <cyg/infra/diag.h> // diag_printf
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51
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52 #include <cyg/hal/hal_arch.h> // HAL header
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53 #include <cyg/hal/hal_cache.h> // HAL cache
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54 #include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions
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55
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56 //---------------------------------------------------------------------------
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57 // Initial cache enabling
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58
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59 #ifdef CYGHWR_HAL_SH_CACHE_MODE_P0_WRITE_BACK
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60 # define CACHE_MODE_P0 0
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61 #else
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62 # define CACHE_MODE_P0 CYGARC_REG_CCR_WT
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63 #endif
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64
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65 #ifdef CYGHWR_HAL_SH_CACHE_MODE_P1_WRITE_BACK
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66 # define CACHE_MODE_P1 CYGARC_REG_CCR_CB
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67 #else
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68 # define CACHE_MODE_P1 0
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69 #endif
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70
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71 externC void
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72 cyg_var_enable_caches(void)
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73 {
172
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74 // If relying on a ROM monitor do not invalidate the caches as the
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75 // ROM monitor may have (non-synced) state in the caches.
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76 #if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
134
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77 // Initialize cache.
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78 HAL_UCACHE_INVALIDATE_ALL();
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79
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80 // Set cache modes
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81 HAL_UCACHE_WRITE_MODE_SH(CACHE_MODE_P0|CACHE_MODE_P1);
172
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82 #endif
134
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83 #ifdef CYGHWR_HAL_SH_CACHE_ENABLE
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84 // Enable cache.
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85 HAL_UCACHE_ENABLE();
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86 #endif
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87 }
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88
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89 //---------------------------------------------------------------------------
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90 void
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91 hal_variant_init(void)
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92 {
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93 }
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94
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95 //---------------------------------------------------------------------------
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96 // Interrupt function support
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97
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98 externC cyg_uint8 cyg_hal_ILVL_table[];
149
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99 externC cyg_uint8 cyg_hal_IMASK_table[];
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100
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101 static void
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102 hal_interrupt_update_level(int vector)
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103 {
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104 cyg_uint16 iprX;
149
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105 int level;
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106
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107 level = cyg_hal_IMASK_table[vector] ? cyg_hal_ILVL_table[vector] : 0;
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108
134
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109 switch( (vector) ) {
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110 case CYGNUM_HAL_INTERRUPT_NMI:
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111 /* fall through */
136
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112 case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:
134
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113 /* Cannot change levels */
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114 break;
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115
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116 /* IPRA */
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117 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0:
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118 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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119 iprX &= ~CYGARC_REG_IPRA_TMU0_MASK;
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120 iprX |= (level)*CYGARC_REG_IPRA_TMU0_PRI1;
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121 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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122 break;
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123 case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1:
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124 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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125 iprX &= ~CYGARC_REG_IPRA_TMU1_MASK;
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126 iprX |= (level)*CYGARC_REG_IPRA_TMU1_PRI1;
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127 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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128 break;
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129 case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2:
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130 case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2:
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131 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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132 iprX &= ~CYGARC_REG_IPRA_TMU2_MASK;
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133 iprX |= (level)*CYGARC_REG_IPRA_TMU2_PRI1;
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134 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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135 break;
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136 case CYGNUM_HAL_INTERRUPT_RTC_ATI:
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jlarmour
parents:
diff changeset
137 case CYGNUM_HAL_INTERRUPT_RTC_PRI:
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jlarmour
parents:
diff changeset
138 case CYGNUM_HAL_INTERRUPT_RTC_CUI:
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jlarmour
parents:
diff changeset
139 HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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jlarmour
parents:
diff changeset
140 iprX &= ~CYGARC_REG_IPRA_RTC_MASK;
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jlarmour
parents:
diff changeset
141 iprX |= (level)*CYGARC_REG_IPRA_RTC_PRI1;
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jlarmour
parents:
diff changeset
142 HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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jlarmour
parents:
diff changeset
143 break;
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jlarmour
parents:
diff changeset
144
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jlarmour
parents:
diff changeset
145 /* IPRB */
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jlarmour
parents:
diff changeset
146 case CYGNUM_HAL_INTERRUPT_SCI_ERI:
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jlarmour
parents:
diff changeset
147 case CYGNUM_HAL_INTERRUPT_SCI_RXI:
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jlarmour
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diff changeset
148 case CYGNUM_HAL_INTERRUPT_SCI_TXI:
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jlarmour
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diff changeset
149 case CYGNUM_HAL_INTERRUPT_SCI_TEI:
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jlarmour
parents:
diff changeset
150 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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jlarmour
parents:
diff changeset
151 iprX &= ~CYGARC_REG_IPRB_SCI_MASK;
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jlarmour
parents:
diff changeset
152 iprX |= (level)*CYGARC_REG_IPRB_SCI_PRI1;
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jlarmour
parents:
diff changeset
153 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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jlarmour
parents:
diff changeset
154 break;
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jlarmour
parents:
diff changeset
155 case CYGNUM_HAL_INTERRUPT_WDT_ITI:
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jlarmour
parents:
diff changeset
156 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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jlarmour
parents:
diff changeset
157 iprX &= ~CYGARC_REG_IPRB_WDT_MASK;
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jlarmour
parents:
diff changeset
158 iprX |= (level)*CYGARC_REG_IPRB_WDT_PRI1;
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jlarmour
parents:
diff changeset
159 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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jlarmour
parents:
diff changeset
160 break;
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jlarmour
parents:
diff changeset
161 case CYGNUM_HAL_INTERRUPT_REF_RCMI:
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jlarmour
parents:
diff changeset
162 case CYGNUM_HAL_INTERRUPT_REF_ROVI:
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jlarmour
parents:
diff changeset
163 HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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jlarmour
parents:
diff changeset
164 iprX &= ~CYGARC_REG_IPRB_REF_MASK;
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jlarmour
parents:
diff changeset
165 iprX |= (level)*CYGARC_REG_IPRB_REF_PRI1;
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jlarmour
parents:
diff changeset
166 HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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jlarmour
parents:
diff changeset
167 break;
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jlarmour
parents:
diff changeset
168
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jlarmour
parents:
diff changeset
169 #if (CYGARC_SH_MOD_INTC >= 2)
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jlarmour
parents:
diff changeset
170 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
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jlarmour
parents:
diff changeset
171 /* IPRC */
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jlarmour
parents:
diff changeset
172 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
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jlarmour
parents:
diff changeset
173 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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jlarmour
parents:
diff changeset
174 iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK;
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jlarmour
parents:
diff changeset
175 iprX |= (level)*CYGARC_REG_IPRC_IRQ0_PRI1;
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jlarmour
parents:
diff changeset
176 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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jlarmour
parents:
diff changeset
177 break;
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jlarmour
parents:
diff changeset
178 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
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jlarmour
parents:
diff changeset
179 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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jlarmour
parents:
diff changeset
180 iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK;
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jlarmour
parents:
diff changeset
181 iprX |= (level)*CYGARC_REG_IPRC_IRQ1_PRI1;
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jlarmour
parents:
diff changeset
182 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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jlarmour
parents:
diff changeset
183 break;
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jlarmour
parents:
diff changeset
184 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
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jlarmour
parents:
diff changeset
185 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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jlarmour
parents:
diff changeset
186 iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK;
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jlarmour
parents:
diff changeset
187 iprX |= (level)*CYGARC_REG_IPRC_IRQ2_PRI1;
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jlarmour
parents:
diff changeset
188 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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jlarmour
parents:
diff changeset
189 break;
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jlarmour
parents:
diff changeset
190 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
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jlarmour
parents:
diff changeset
191 HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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jlarmour
parents:
diff changeset
192 iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK;
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jlarmour
parents:
diff changeset
193 iprX |= (level)*CYGARC_REG_IPRC_IRQ3_PRI1;
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jlarmour
parents:
diff changeset
194 HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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jlarmour
parents:
diff changeset
195 break;
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jlarmour
parents:
diff changeset
196 #endif
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diff changeset
197 /* IPRD */
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jlarmour
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diff changeset
198 case CYGNUM_HAL_INTERRUPT_PINT_PINT07:
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parents:
diff changeset
199 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents:
diff changeset
200 iprX &= ~CYGARC_REG_IPRD_PINT07_MASK;
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jlarmour
parents:
diff changeset
201 iprX |= (level)*CYGARC_REG_IPRD_PINT07_PRI1;
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jlarmour
parents:
diff changeset
202 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents:
diff changeset
203 break;
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jlarmour
parents:
diff changeset
204 case CYGNUM_HAL_INTERRUPT_PINT_PINT8F:
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jlarmour
parents:
diff changeset
205 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents:
diff changeset
206 iprX &= ~CYGARC_REG_IPRD_PINT8F_MASK;
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jlarmour
parents:
diff changeset
207 iprX |= (level)*CYGARC_REG_IPRD_PINT8F_PRI1;
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jlarmour
parents:
diff changeset
208 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents:
diff changeset
209 break;
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jlarmour
parents:
diff changeset
210 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
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jlarmour
parents:
diff changeset
211 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents:
diff changeset
212 iprX &= ~CYGARC_REG_IPRD_IRQ5_MASK;
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jlarmour
parents:
diff changeset
213 iprX |= (level)*CYGARC_REG_IPRD_IRQ5_PRI1;
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jlarmour
parents:
diff changeset
214 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents:
diff changeset
215 break;
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jlarmour
parents:
diff changeset
216 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
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jlarmour
parents:
diff changeset
217 HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents:
diff changeset
218 iprX &= ~CYGARC_REG_IPRD_IRQ4_MASK;
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jlarmour
parents:
diff changeset
219 iprX |= (level)*CYGARC_REG_IPRD_IRQ4_PRI1;
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jlarmour
parents:
diff changeset
220 HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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jlarmour
parents:
diff changeset
221 break;
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jlarmour
parents:
diff changeset
222
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jlarmour
parents:
diff changeset
223 /* IPRE */
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jlarmour
parents:
diff changeset
224 case CYGNUM_HAL_INTERRUPT_DMAC_DEI0:
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jlarmour
parents:
diff changeset
225 case CYGNUM_HAL_INTERRUPT_DMAC_DEI1:
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jlarmour
parents:
diff changeset
226 case CYGNUM_HAL_INTERRUPT_DMAC_DEI2:
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jlarmour
parents:
diff changeset
227 case CYGNUM_HAL_INTERRUPT_DMAC_DEI3:
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jlarmour
parents:
diff changeset
228 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents:
diff changeset
229 iprX &= ~CYGARC_REG_IPRE_DMAC_MASK;
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jlarmour
parents:
diff changeset
230 iprX |= (level)*CYGARC_REG_IPRE_DMAC_PRI1;
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jlarmour
parents:
diff changeset
231 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents:
diff changeset
232 break;
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jlarmour
parents:
diff changeset
233 case CYGNUM_HAL_INTERRUPT_IRDA_ERI1:
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jlarmour
parents:
diff changeset
234 case CYGNUM_HAL_INTERRUPT_IRDA_RXI1:
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jlarmour
parents:
diff changeset
235 case CYGNUM_HAL_INTERRUPT_IRDA_BRI1:
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jlarmour
parents:
diff changeset
236 case CYGNUM_HAL_INTERRUPT_IRDA_TXI1:
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jlarmour
parents:
diff changeset
237 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents:
diff changeset
238 iprX &= ~CYGARC_REG_IPRE_IRDA_MASK;
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jlarmour
parents:
diff changeset
239 iprX |= (level)*CYGARC_REG_IPRE_IRDA_PRI1;
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jlarmour
parents:
diff changeset
240 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents:
diff changeset
241 break;
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jlarmour
parents:
diff changeset
242 case CYGNUM_HAL_INTERRUPT_SCIF_ERI2:
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jlarmour
parents:
diff changeset
243 case CYGNUM_HAL_INTERRUPT_SCIF_RXI2:
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jlarmour
parents:
diff changeset
244 case CYGNUM_HAL_INTERRUPT_SCIF_BRI2:
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jlarmour
parents:
diff changeset
245 case CYGNUM_HAL_INTERRUPT_SCIF_TXI2:
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jlarmour
parents:
diff changeset
246 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents:
diff changeset
247 iprX &= ~CYGARC_REG_IPRE_SCIF_MASK;
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jlarmour
parents:
diff changeset
248 iprX |= (level)*CYGARC_REG_IPRE_SCIF_PRI1;
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jlarmour
parents:
diff changeset
249 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents:
diff changeset
250 break;
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jlarmour
parents:
diff changeset
251 case CYGNUM_HAL_INTERRUPT_ADC_ADI:
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jlarmour
parents:
diff changeset
252 HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents:
diff changeset
253 iprX &= ~CYGARC_REG_IPRE_ADC_MASK;
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jlarmour
parents:
diff changeset
254 iprX |= (level)*CYGARC_REG_IPRE_ADC_PRI1;
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jlarmour
parents:
diff changeset
255 HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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jlarmour
parents:
diff changeset
256 break;
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jlarmour
parents:
diff changeset
257 #endif // (CYGARC_SH_MOD_INTC >= 2)
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jlarmour
parents:
diff changeset
258
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jlarmour
parents:
diff changeset
259 #if (CYGARC_SH_MOD_INTC >= 3)
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jlarmour
parents:
diff changeset
260 /* IPRF */
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261 case CYGNUM_HAL_INTERRUPT_LCDC_LCDI:
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262 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
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263 iprX &= ~CYGARC_REG_IPRF_LCDI_MASK;
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264 iprX |= (level)*CYGARC_REG_IPRF_LCDI_PRI1;
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265 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
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266 break;
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267 case CYGNUM_HAL_INTERRUPT_PCC_PCC0:
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268 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
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269 iprX &= ~CYGARC_REG_IPRF_PCC0_MASK;
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270 iprX |= (level)*CYGARC_REG_IPRF_PCC0_PRI1;
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271 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
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272 break;
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273 case CYGNUM_HAL_INTERRUPT_PCC_PCC1:
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274 HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
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275 iprX &= ~CYGARC_REG_IPRF_PCC1_MASK;
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276 iprX |= (level)*CYGARC_REG_IPRF_PCC1_PRI1;
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277 HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
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278 break;
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279 #endif // (CYGARC_SH_MOD_INTC >= 3)
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280
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281 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
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282 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
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283 /* Do nothing for these reserved vectors. */
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284 break;
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285
165
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286 // Platform extensions
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287 CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vector, level)
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diff changeset
288
134
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289 default:
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290 CYG_FAIL("Unknown interrupt vector");
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291 break;
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292 }
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293 }
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294
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295 void
149
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diff changeset
296 hal_interrupt_set_level(int vector, int level)
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diff changeset
297 {
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298 CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level");
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299 CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)
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300 && CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector");
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diff changeset
301
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302 cyg_hal_ILVL_table[vector] = level;
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diff changeset
303
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304 hal_interrupt_update_level(vector);
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305 }
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diff changeset
306
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diff changeset
307 void
134
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308 hal_interrupt_mask(int vector)
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309 {
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310 switch( (vector) ) {
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311 case CYGNUM_HAL_INTERRUPT_NMI:
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312 /* fall through */
136
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313 case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:
134
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314 /* Can only be masked by fiddling Imask in SR. */
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315 break;
136
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316 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 ... CYGNUM_HAL_ISR_MAX:
149
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317 cyg_hal_IMASK_table[vector] = 0;
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318 hal_interrupt_update_level(vector);
134
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319 break;
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320 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
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321 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
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322 /* Do nothing for these reserved vectors. */
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323 break;
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324 default:
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325 CYG_FAIL("Unknown interrupt vector");
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326 break;
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327 }
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328 }
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329
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330 void
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331 hal_interrupt_unmask(int vector)
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332 {
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333 switch( (vector) ) {
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334 case CYGNUM_HAL_INTERRUPT_NMI:
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335 /* fall through */
136
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336 case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:
134
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337 /* Can only be unmasked by fiddling Imask in SR. */
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338 break;
136
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339 case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 ... CYGNUM_HAL_ISR_MAX:
149
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340 cyg_hal_IMASK_table[vector] = 1;
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341 hal_interrupt_update_level(vector);
134
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342 break;
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343 case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
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344 case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
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345 /* Do nothing for these reserved vectors. */
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346 break;
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347 default:
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348 CYG_FAIL("Unknown interrupt vector");
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349 break;
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350 }
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351 }
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352
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353 void
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354 hal_interrupt_acknowledge(int vector)
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355 {
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356 #if (CYGARC_SH_MOD_INTC >= 2)
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357 if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
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358 && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
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359
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360 cyg_uint8 irr0;
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361
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362 HAL_READ_UINT8(CYGARC_REG_IRR0, irr0);
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363 switch ( vector ) {
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364 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
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365 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
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366 irr0 &= ~CYGARC_REG_IRR0_IRQ0;
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367 break;
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368 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
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369 irr0 &= ~CYGARC_REG_IRR0_IRQ1;
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370 break;
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371 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
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372 irr0 &= ~CYGARC_REG_IRR0_IRQ2;
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373 break;
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374 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
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375 irr0 &= ~CYGARC_REG_IRR0_IRQ3;
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376 break;
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377 #endif
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378 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
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379 irr0 &= ~CYGARC_REG_IRR0_IRQ4;
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380 break;
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381 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
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382 irr0 &= ~CYGARC_REG_IRR0_IRQ5;
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383 break;
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384 default:
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385 CYG_FAIL("Unhandled interrupt vector");
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386 }
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387 HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0);
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388 }
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389 #endif
165
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diff changeset
390
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391 CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vector);
134
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392 }
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393
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394 // Note: The PINTs can be masked and configured individually, even
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395 // though there are only two vectors. Maybe add some fake vectors just
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396 // for masking/configuring?
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397 void
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398 hal_interrupt_configure(int vector, int level, int up)
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399 {
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400 #if (CYGARC_SH_MOD_INTC >= 2)
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401 if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
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402 && (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
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403
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404 cyg_uint16 icr1, ss, mask;
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405 ss = 0;
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406 mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL;
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407 if (up) ss |= CYGARC_REG_ICR1_SENSE_UP;
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408 if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL;
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409 CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
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410
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411 switch( (vector) ) {
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412 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
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413 ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
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414 mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
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415 break;
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416 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
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417 ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
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418 mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
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419 break;
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420 #ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
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421 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
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422 ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
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423 mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
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424 break;
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425 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
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426 ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
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427 mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
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428 break;
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429 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
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430 ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
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431 mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
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432 break;
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433 case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
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434 ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
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435 mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
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436 break;
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437 #endif
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438 default:
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439 CYG_FAIL("Unhandled interrupt vector");
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440 }
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441
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442 HAL_READ_UINT16(CYGARC_REG_ICR1, icr1);
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443 icr1 &= ~mask;
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444 icr1 |= ss;
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445 HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1);
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446 }
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447 #endif
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448 }
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449
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450 //---------------------------------------------------------------------------
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451 // End of hal_misc.c