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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children dbcfe4e0dbd2
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3 //=============================================================================
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4 //
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5 // var_cache.h
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6 //
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7 // Variant HAL cache control API
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8 //
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9 //=============================================================================
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10 //####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later version.
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18 //
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19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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22 // for more details.
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23 //
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24 // You should have received a copy of the GNU General Public License along
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25 // with eCos; if not, write to the Free Software Foundation, Inc.,
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 //
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28 // As a special exception, if other files instantiate templates or use macros
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29 // or inline functions from this file, or you compile this file and link it
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30 // with other works to produce a work based on this file, this file does not
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31 // by itself cause the resulting work to be covered by the GNU General Public
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32 // License. However the source code for this file must still be made available
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33 // in accordance with section (3) of the GNU General Public License.
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34 //
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35 // This exception does not invalidate any other reasons why a work based on
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36 // this file might be covered by the GNU General Public License.
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37 //
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38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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39 // at http://sources.redhat.com/ecos/ecos-license/
208
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40 // -------------------------------------------
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41 //####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors:nickg, jskov
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47 // Date: 2000-04-02
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48 // Purpose: Variant cache control API
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // cache control operations on the PPC60x variant CPUs.
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51 // Usage: Is included via the architecture cache header:
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52 // #include <cyg/hal/hal_cache.h>
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53 // ...
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54 //
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55 //####DESCRIPTIONEND####
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56 //
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57 //=============================================================================
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58
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59 #include <pkgconf/hal.h>
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60 #include <cyg/infra/cyg_type.h>
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61
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62 #include <cyg/hal/ppc_regs.h>
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63
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64 #include <cyg/hal/plf_cache.h>
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65
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66
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67 //-----------------------------------------------------------------------------
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68 // Cache dimensions
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69
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70 // Data cache
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71 #define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes
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72 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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73 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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74
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75 // Instruction cache
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76 #define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
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77 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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78 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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79
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80 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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81 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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82
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83 //-----------------------------------------------------------------------------
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84 // Global control of data cache
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85
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86 // Enable the data cache - this is implicit whenever the MMU is turned on
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87 #define HAL_DCACHE_ENABLE()
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88
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89 // Disable the data cache
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90 #define HAL_DCACHE_DISABLE()
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91
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92 // Invalidate the entire cache
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93 #define HAL_DCACHE_INVALIDATE_ALL() \
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94 CYG_MACRO_START \
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95 int _i_, _ix_, _indx_; \
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96 _indx_ = 0; \
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97 _ix_ = HAL_DCACHE_SIZE/2; \
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98 for (_i_ = 0; _i_ < HAL_DCACHE_SETS; _i_++) { \
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99 /* asm volatile ("dcbf 0,%0;" :: "r"(_indx_)); */ \
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100 /* asm volatile ("dcbf %1,%0;" :: "r"(_indx_), "r"(_ix_)); */\
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101 asm volatile ("dccci 0,%0;" :: "r"(_indx_)); \
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102 _indx_ += HAL_DCACHE_LINE_SIZE; \
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103 } \
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104 CYG_MACRO_END
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105
136
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106 // Synchronize the contents of the cache with memory.
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107 #define HAL_DCACHE_SYNC() \
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108 CYG_MACRO_START \
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109 int _indx_; \
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110 for (_indx_ = 0; _indx_ < HAL_DCACHE_SIZE; _indx_ += HAL_DCACHE_LINE_SIZE) { \
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111 asm volatile ("dcbf 0,%0;" :: "r"(_indx_)); \
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112 } \
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113 CYG_MACRO_END
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114
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115 // Query the state of the data cache
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116 #define HAL_DCACHE_IS_ENABLED(_state_) \
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117 CYG_MACRO_START \
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118 (_state_) = 1; \
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119 CYG_MACRO_END
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120
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121 // Set the data cache refill burst size
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122 //#define HAL_DCACHE_BURST_SIZE(_size_)
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123
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124 // Set the data cache write mode
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125 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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126
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127 //#define HAL_DCACHE_WRITETHRU_MODE 0
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128 //#define HAL_DCACHE_WRITEBACK_MODE 1
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129
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130 // Load the contents of the given address range into the data cache
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131 // and then lock the cache so that it stays there.
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132 //#define HAL_DCACHE_LOCK(_base_, _size_)
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133
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134 // Undo a previous lock operation
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135 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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136
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137 // Unlock entire cache
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138 #define HAL_DCACHE_UNLOCK_ALL()
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139
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140 //-----------------------------------------------------------------------------
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141 // Data cache line control
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142
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143 // Allocate cache lines for the given address range without reading its
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144 // contents from memory.
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145 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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146
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147 // Write dirty cache lines to memory and invalidate the cache entries
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148 // for the given address range.
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149 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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150
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151 // Invalidate cache lines in the given range without writing to memory.
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152 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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153
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154 // Write dirty cache lines to memory for the given address range.
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155 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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156
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157 // Preread the given range into the cache with the intention of reading
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158 // from it later.
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159 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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160
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161 // Preread the given range into the cache with the intention of writing
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162 // to it later.
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163 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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164
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165 // Allocate and zero the cache lines associated with the given range.
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166 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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167
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168 //-----------------------------------------------------------------------------
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169 // Global control of Instruction cache
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170
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171 // Enable the instruction cache
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172 #define HAL_ICACHE_ENABLE()
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173
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174 // Disable the instruction cache
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175 #define HAL_ICACHE_DISABLE()
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176
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177 // Invalidate the entire cache
136
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178 #define HAL_ICACHE_INVALIDATE_ALL() \
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179 CYG_MACRO_START \
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180 int _i_, _indx_; \
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181 _indx_ = 0; \
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182 for (_i_ = 0; _i_ < HAL_ICACHE_SETS; _i_++) { \
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183 asm volatile ("iccci 0,%0;" :: "r"(_indx_)); \
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184 _indx_ += HAL_ICACHE_LINE_SIZE; \
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185 } \
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186 CYG_MACRO_END
134
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187
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188 // Synchronize the contents of the cache with memory.
136
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189 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
134
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190
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191 // Query the state of the instruction cache
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192 #define HAL_ICACHE_IS_ENABLED(_state_) \
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193 CYG_MACRO_START \
136
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194 (_state_) = 1; \
134
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195 CYG_MACRO_END
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196
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197 // Set the instruction cache refill burst size
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198 //#define HAL_ICACHE_BURST_SIZE(_size_)
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199
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200 // Load the contents of the given address range into the instruction cache
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201 // and then lock the cache so that it stays there.
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202 //#define HAL_ICACHE_LOCK(_base_, _size_)
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203
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204 // Undo a previous lock operation
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205 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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206
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207 // Unlock entire cache
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208 #define HAL_ICACHE_UNLOCK_ALL()
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209
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210 //-----------------------------------------------------------------------------
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211 // Instruction cache line control
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212
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213 // Invalidate cache lines in the given range without writing to memory.
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214 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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215
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216 //-----------------------------------------------------------------------------
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217 #endif // ifndef CYGONCE_VAR_CACHE_H
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218 // End of var_cache.h