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annotate packages/hal/mips/tx49/current/include/variant.inc @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children e0c0827131d1
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1 #ifndef CYGONCE_HAL_VARIANT_INC
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2 #define CYGONCE_HAL_VARIANT_INC
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3 ##=============================================================================
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4 ##
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5 ## variant.inc
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6 ##
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7 ## TX49 family assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.1 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://www.redhat.com/
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17 #
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18 # Software distributed under the License is distributed on an "AS IS"
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): nickg
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37 ## Contributors:nickg, jskov
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38 ## Date: 2000-05-10
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39 ## Purpose: TX49 family definitions.
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40 ## Description: This file contains various definitions and macros that are
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41 ## useful for writing assembly code for the TX49 CPU family.
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42 ## Usage:
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43 ## #include <cyg/hal/variant.inc>
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44 ## ...
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45 ##
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46 ##
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47 ######DESCRIPTIONEND####
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48 ##
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49 ##=============================================================================
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50
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51 #include <pkgconf/hal.h>
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52
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53 #include <cyg/hal/platform.inc>
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54
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55 ##-----------------------------------------------------------------------------
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56 ## Define CPU variant for architecture HAL.
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57
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58 #define CYG_HAL_MIPS_R4900
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59
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60 #------------------------------------------------------------------------------
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61 # Set up initial value for config register. Sets endian mode and
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62 # enable the cache on kseg0.
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63
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64 #if defined(CYGPKG_HAL_MIPS_MSBFIRST)
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65 # define INITIAL_CONFIG0 0x00008000
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66 #elif defined(CYGPKG_HAL_MIPS_LSBFIRST)
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67 # define INITIAL_CONFIG0 0x00000000
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68 #else
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69 # error MIPS endianness not set by configuration
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70 #endif
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71
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72 #------------------------------------------------------------------------------
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73 # Set up initial value for FPU FCR31 register. We set the FS bit to flush
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74 # denormalized results to zero and enable div-by-zero exceptions.
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75
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76 #ifndef CYG_HAL_MIPS_FCSR_INIT
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77 #define CYG_HAL_MIPS_FCSR_INIT 0x01000400
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78 #endif
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79
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80 #------------------------------------------------------------------------------
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81 # Cache macros.
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82
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83 #ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
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84
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85 .macro hal_cache_init
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86
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87 mfc0 v0,config0 # disable caches, but allow caching
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88 nop # on kseg0 so cache macros can just
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89 nop # fiddle ICE/IDE later on.
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90 la v1,0xfffffff8
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91 and v0,v0,v1
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92 ori v0,v0,3 # kseg0 is writeback cache enabled
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93 lui v1,3
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94 or v0,v0,v1 # set ICE&IDE (disables caches)
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95 mtc0 v0,config0
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96 nop
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97 nop
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98 nop
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99
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100 .set mips3 # Set ISA to MIPS 3 to allow cache insns
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101
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102 # Now ensure the caches are invalidated. The caches are NOT cleared or
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103 # invalidated on non-power-up resets and may come up in a random state
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104 # on power-up. Hence they may contain stale or randomly bogus data.
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105 # Here we use the index-store-tag cache operation to clear all the
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106 # cache tags and states to zero. This will render them all invalid on
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107 # the TX49.
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108
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109 # D-cache:
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110 la t0,0x80000000
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111 ori t1,t0,0x8000
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112 1:
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113 mtc0 zero,$28
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114 mtc0 zero,$29
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115 cache 0x09,0(t0)
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116 cache 0x09,1(t0)
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117 cache 0x09,2(t0)
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118 cache 0x09,3(t0)
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119 addi t0,t0,0x20
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120 sub v0,t1,t0
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121 bgez v0,1b
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122 nop # delay slot
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123
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124 # I-cache:
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125 la a0,0x80000000
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126 ori a1,a0,0x8000
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127 1:
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128 mtc0 zero,$28
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129 mtc0 zero,$29
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130 cache 0x08,0(a0)
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131 cache 0x08,1(a0)
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132 cache 0x08,2(a0)
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133 cache 0x08,3(a0)
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134 addi a0,a0,0x20
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135 sub v0,a1,a0
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136 bgez v0,1b
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137 nop # delay slot
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138
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139 .set mips0 # reset ISA to default
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140
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141 # Now enable caches
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142 mfc0 v0,config0
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143 nop
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144 nop
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145 la v1,0xfffcffff # clear ICE&IDE (enables caches)
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146 and v0,v0,v1
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147 mtc0 v0,config0
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148 nop
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149 nop
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150 nop
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151
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152 .endm
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153
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154 #define CYGPKG_HAL_MIPS_CACHE_DEFINED
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155
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156 #endif
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157
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158 #------------------------------------------------------------------------------
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159 #endif // ifndef CYGONCE_HAL_VARIANT_INC
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160 # end of variant.inc