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annotate packages/hal/powerpc/ppc40x/current/include/variant.inc @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children a9ac27ec7abc
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1 #ifndef CYGONCE_HAL_VARIANT_INC
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2 #define CYGONCE_HAL_VARIANT_INC
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3 ##=============================================================================
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4 ##
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5 ## variant.inc
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6 ##
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7 ## PPC40x family assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.1 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://www.redhat.com/
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17 #
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18 # Software distributed under the License is distributed on an "AS IS"
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): jskov
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37 ## Contributors:jskov, gthomas
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38 ## Date: 2000-08-27
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39 ## Purpose: MPCxxx family definitions.
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40 ## Description: This file contains various definitions and macros that are
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41 ## useful for writing assembly code for the PPC40x CPU family.
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42 ## Usage:
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43 ## #include <cyg/hal/variant.inc>
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44 ## ...
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45 ##
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46 ##
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47 ######DESCRIPTIONEND####
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48 ##
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49 ##=============================================================================
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50
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51 #include <pkgconf/hal.h>
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52
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53 #undef CYG_MSR_COMMON
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54 #define CYG_MSR_COMMON (MSR_ME | MSR_RI)
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55
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56 #include <cyg/hal/arch.inc>
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57
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58 ##-----------------------------------------------------------------------------
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59 ## PPC40x defined vectors
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60
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61 .macro hal_extra_vectors
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62 .endm
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63
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64 ##-----------------------------------------------------------------------------
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65 ## PPC40x CPU initialization
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66 ##
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67 ## Initialize CPU to a post-reset state, ensuring the ground doesn''t
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68 ## shift under us while we try to set things up.
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69
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70 .macro hal_cpu_init
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71 # Set up MSR (disable MMU for now)
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72 lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR))
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73 sync
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74 mfmsr r4
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75 mtmsr r3
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76 sync
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77 .endm
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78
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79 ##-----------------------------------------------------------------------------
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80 ## PPC40x monitor initialization
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81
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82 #ifndef CYGPKG_HAL_PPC_MON_DEFINED
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83
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84 #if defined(CYG_HAL_STARTUP_ROM) || \
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85 ( defined(CYG_HAL_STARTUP_RAM) && \
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86 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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87
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88 .macro hal_mon_init
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89 #ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS
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90 # If we are starting up from ROM and want vectors in RAM
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91 # or we are starting in RAM and NOT using a ROM monitor,
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92 # copy exception handler code to 0.
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93 lwi r3,rom_vectors # r3 = rom start
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94 lwi r4,0 # r4 = ram start
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95 lwi r5,rom_vectors_end # r5 = rom end
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96 cmplw r3,r5 # skip if no vectors
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97 beq 2f
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98
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99 subi r3,r3,4
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100 subi r4,r4,4
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101 subi r5,r5,4
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102 1:
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103 lwzu r0,4(r3) # get word from ROM
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104 stwu r0,4(r4) # store in RAM
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105 cmplw r3,r5 # compare
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106 blt 1b # loop if not yet done
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107 2:
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108
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109 # Ensure that the vectors will come from 0x0000
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110 lwi r4,0
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111 mtspr EVPR,r4
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112 #endif
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113
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114 # Next initialize the VSR table. This happens whether the
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115 # vectors were copied to RAM or not.
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116
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117 # First fill with exception handlers
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118 lwi r3,cyg_hal_default_exception_vsr
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119 lwi r4,hal_vsr_table
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120 subi r4,r4,4
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121 li r5,CYGNUM_HAL_VSR_COUNT
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122 1: stwu r3,4(r4)
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123 subi r5,r5,1
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124 cmpwi r5,0
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125 bne 1b
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126
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127 # Then fill in the special vectors
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128 lwi r3,cyg_hal_default_interrupt_vsr
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129 lwi r4,hal_vsr_table
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130 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
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131 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
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132 .endm
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133
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134 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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135
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136 # Initialize the VSR table entries
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137 # We only take control of the interrupt vectors,
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138 # the rest are left to the ROM for now...
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139
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140 .macro hal_mon_init
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141 lwi r3,cyg_hal_default_interrupt_vsr
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142 lwi r4,hal_vsr_table
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143 stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
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144 stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
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145 .endm
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146
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147
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148 #else
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149
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150 .macro hal_mon_init
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151
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152 .endm
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153
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154 #endif
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155
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156
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157 #define CYGPKG_HAL_PPC_MON_DEFINED
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158
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159 #endif // CYGPKG_HAL_PPC_MON_DEFINED
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160
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161 ##-----------------------------------------------------------------------------
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162 ## PPC40x exception state handling
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163 .macro hal_variant_save regs
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164 .endm
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165
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166 .macro hal_variant_load regs
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167 .endm
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168
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169 ##-----------------------------------------------------------------------------
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170 ## Indicate that the ISR tables are defined in variant.S
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171
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172 #define CYG_HAL_PPC_ISR_TABLES_DEFINED
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173
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174 #------------------------------------------------------------------------------
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175 #endif // ifndef CYGONCE_HAL_VARIANT_INC
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176 # end of variant.inc