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annotate packages/hal/sh/cq7750/current/include/platform.inc @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
parents
children a9ac27ec7abc
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1 #ifndef CYGONCE_HAL_PLATFORM_INC
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2 #define CYGONCE_HAL_PLATFORM_INC
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3 ##=============================================================================
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4 ##
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5 ## platform.inc
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6 ##
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7 ## SH/CQ7750 board assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.0 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://sourceware.cygnus.com/ecos
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17 #
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18 # Software distributed under the License is distributed on an
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): jskov
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37 ## Contributors:Ryozaburo Suzuki
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38 ## Date: 2000-04-18
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39 ## Purpose: SH/CQ7750 board definitions.
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40 ## Description: This file contains various definitions and macros that are
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41 ## useful for writing assembly code for the SH/CQ7750 board.
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42 ## Usage:
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43 ## #include <cyg/hal/platform.inc>
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44 ## ...
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45 ##
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46 ##
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47 ######DESCRIPTIONEND####
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48 ##
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49 ##=============================================================================
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50
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51 #include <pkgconf/hal.h>
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52
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53 #include <cyg/hal/sh_offsets.inc>
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54 #include <cyg/hal/sh_regs.h>
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55
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56 #------------------------------------------------------------------------------
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57 # Hardware initialization.
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58
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59 .macro hal_hardware_init
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60 // Set up the Bus State Controller
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61 mova BSC_settings_table,r0
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62 mov r0,r3
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63 1: mov.l @r3+,r0 // Address (or zero)
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64 mov r0,r2
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65 cmp/eq #0,r0
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66 bt 4f
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67 mov.l @r3+,r1 // data
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68 mov.l @r3+,r0 // byte or word or long?
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69
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70 cmp/eq #0,r0 // byte
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71 bt 2f
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72
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73 cmp/eq #1,r0 // word
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74 bt 3f
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75
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76 bra 1b // long
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77 mov.l r1,@r2 // delay slot
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78
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79 2: bra 1b
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80 mov.b r1,@r2 // delay slot
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81
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82 3: bra 1b
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83 mov.w r1,@r2 // delay slot
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84
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85 .align 2
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86
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87 BSC_settings_table:
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88 # BCR1:
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89 .long CYGARC_REG_BCR1
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90 .long 0x0020000c
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91 .long 2
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92 # BCR2:
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93 .long CYGARC_REG_BCR2
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94 .long 0x35F8
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95 .long 1
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96 # WCR1:
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97 .long CYGARC_REG_WCR1
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98 .long 0x77117121
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99 .long 2
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100 # WCR2:
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101 .long CYGARC_REG_WCR2
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102 .long 0xFC8AE520
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103 .long 2
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104 # WCR3:
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105 .long CYGARC_REG_WCR3
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106 .long 0x07117101
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107 .long 2
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108 # PCR:
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109 .long CYGARC_REG_PCR
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110 .long 0x0000
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111 .long 1
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112 # RTCNT:
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113 .long CYGARC_REG_RTCNT
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114 .long 0xa500
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115 .long 1
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116 # RTCOR:
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117 .long CYGARC_REG_RTCOR
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118 .long 0xa53b
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119 .long 1
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120 # RFCR:
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121 .long CYGARC_REG_RFCR
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122 .long 0xa400
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123 .long 1
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124 # RTCSR:
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125 .long CYGARC_REG_RTCSR
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126 .long 0xa508
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127 .long 1
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128 # MCR:
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129 .long CYGARC_REG_MCR
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130 .long 0x10192194
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131 .long 2
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132 # SDMR2:
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133 .long CYGARC_REG_SDMR2
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134 .long 0xaa
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135 .long 0
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136 # MCR:
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137 .long CYGARC_REG_MCR
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138 .long 0x50192194
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139 .long 2
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140 # SDMR2:
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141 .long CYGARC_REG_SDMR2
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142 .long 0xaa
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143 .long 0
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144 # Table end
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145 .long 0
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146
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147 .align 2
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148 4:
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149 .endm
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150
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151 #------------------------------------------------------------------------------
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152 # Monitor initialization.
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153
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154 #ifndef CYGPKG_HAL_SH_MON_DEFINED
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155
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156 #if defined(CYG_HAL_STARTUP_ROM) || \
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157 ( defined(CYG_HAL_STARTUP_RAM) && \
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158 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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159
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160 # If we are starting up from ROM, or we are starting in
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161 # RAM and NOT using a ROM monitor, initialize the VSR table.
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162
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163 .macro hal_mon_init
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164 mov.l $_hal_vsr_table_p,r3
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165 # Write exception vectors
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166 mov.l $_cyg_hal_default_exception_vsr_p,r4
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167 mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
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168 1: mov.l r4,@r3
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169 add #4,r3
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170 dt r5
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171 bf 1b
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172 # Write interrupt vector
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173 mov.l $_cyg_hal_default_interrupt_vsr_p,r4
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174 mov.l r4,@r3
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175 bra 2f
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176 nop
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177 .align 2
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178
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179 $_cyg_hal_default_exception_vsr_p:
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180 .long _cyg_hal_default_exception_vsr
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181 $_cyg_hal_default_interrupt_vsr_p:
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182 .long _cyg_hal_default_interrupt_vsr
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183
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184 .extern _hal_vsr_table
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185 $_hal_vsr_table_p:
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186 .long _hal_vsr_table
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187
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188 2:
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189 .endm
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190
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191 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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192
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193 # Initialize the VSR table entries
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194 # We only take control of the interrupt vector,
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195 # the rest are left to the ROM for now...
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196
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197 .macro hal_mon_init
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198 # Write interrupt vector
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199 mov.l $_hal_vsr_table_p,r3
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200 mov.l $_cyg_hal_default_interrupt_vsr_p,r4
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201 mov.l r4,@r3
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202 bra 2f
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203 nop
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204 .align 2
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205
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206 $_cyg_hal_default_interrupt_vsr_p:
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207 .long _cyg_hal_default_interrupt_vsr
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208
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209 .extern _hal_vsr_table
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210 $_hal_vsr_table_p:
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211 .long _hal_vsr_table+CYGNUM_HAL_VECTOR_INTERRUPT*4
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212
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213 2:
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214 .endm
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215
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216 #else
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217
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218 .macro hal_mon_init
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219 .endm
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220
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221 #endif
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222
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223
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224 #define CYGPKG_HAL_SH_MON_DEFINED
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225
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226 #endif // CYGPKG_HAL_SH_MON_DEFINED
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227
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228 #endif // CYGONCE_HAL_PLATFORM_INC