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annotate packages/hal/sh/sh3/current/include/mod_regs_ubc.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children 0d2b193a635f
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1 //=============================================================================
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2 //
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3 // mod_regs_ubc.h
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4 //
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5 // UBC (user break controller) Module register definitions
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6 //
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7 //=============================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //=============================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors:jskov
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36 // Date: 2000-10-30
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37 //
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38 //####DESCRIPTIONEND####
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39 //
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40 //=============================================================================
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41
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42 //--------------------------------------------------------------------------
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43 // User Break Control
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44 #define CYGARC_REG_BRCR 0xffffff98 // 16 bit
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45
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46 #define CYGARC_REG_BARA 0xffffffb0 // 32 bit
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47 #define CYGARC_REG_BAMRA 0xffffffb4 // 8 bit (v1) / 32 bit
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48 #define CYGARC_REG_BBRA 0xffffffb8 // 16 bit
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49 #define CYGARC_REG_BASRA 0xffffffe4 // 8 bit
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50
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51 #define CYGARC_REG_BARB 0xffffffa0 // 32 bit
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52 #define CYGARC_REG_BAMRB 0xffffffa4 // 8 bit (v1) / 32 bit
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53 #define CYGARC_REG_BASRB 0xffffffe8 // 8 bit
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54 #define CYGARC_REG_BBRB 0xffffffa8 // 16 bit
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55 #define CYGARC_REG_BDRB 0xffffff90 // 32 bit
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56 #define CYGARC_REG_BDMRB 0xffffff94 // 32 bit
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57
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58
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59 #define CYGARC_REG_BRCR_CMFA 0x8000 // condition match flag A
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60 #define CYGARC_REG_BRCR_CMFB 0x4000 // condition match flag B
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61 #define CYGARC_REG_BRCR_PCBA 0x0400 // post execute channel A
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62 #define CYGARC_REG_BRCR_DBEB 0x0080 // data break enable B
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63 #define CYGARC_REG_BRCR_PCBB 0x0040 // post execute channel B
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64 #define CYGARC_REG_BRCR_SEQ 0x0008 // sequence condition select
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65
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66 #if (CYGARC_SH_MOD_UBC == 1)
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67 #define CYGARC_REG_BAMRA_BASMA 0x04 // BASRA masked
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68 #define CYGARC_REG_BAMRA_BARA_UNMASKED 0x00 // BARA not masked
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69 #define CYGARC_REG_BAMRA_BARA_10BIT 0x01 // Lowest 10 bit masked
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70 #define CYGARC_REG_BAMRA_BARA_12BIT 0x02 // Lowest 12 bit masked
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71 #define CYGARC_REG_BAMRA_BARA_MASKED 0x03 // All bits masked
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72 #else
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73 // mask is fully configurable in other versions of the UBC
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74 #endif
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75
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76 #define CYGARC_REG_BBRA_DFETCH 0x0020 // Break on DFETCH
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77 #define CYGARC_REG_BBRA_IFETCH 0x0010 // Break on IFETCH
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78 #define CYGARC_REG_BBRA_WRITE 0x0008 // Break on WRITE
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79 #define CYGARC_REG_BBRA_READ 0x0004 // Break on READ
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80 #define CYGARC_REG_BBRA_SIZE_LONG 0x0003 // Break on long access
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81 #define CYGARC_REG_BBRA_SIZE_WORD 0x0002 // Break on word access
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82 #define CYGARC_REG_BBRA_SIZE_BYTE 0x0001 // Break on byte access
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83 #define CYGARC_REG_BBRA_SIZE_ANY 0x0000 // Break on any size
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84
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85
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86 //----------------------------------------------------------------------------
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87 // Other types
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88 #if (CYGARC_SH_MOD_UBC >= 3)
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89 #define CYGARC_REG_BETR 0xffffff9c // 16 bit
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90 #define CYGARC_REG_BRSR 0xffffffac // 32 bit
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91 #define CYGARC_REG_BRDR 0xffffffbc // 32 bit
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92
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93 #define CYGARC_REG_BBRA_DMA 0x0080 // Break on DMAC cycle
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94 #define CYGARC_REG_BBRA_CPU 0x0040 // Break on CPU cycle
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95 #endif