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annotate packages/hal/sh/sh4/current/src/sh4_scif.c @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
parents
children 25e238959bae
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1 //=============================================================================
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2 //
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3 // sh4_scif.c
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4 //
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5 // Simple driver for the SH4 Serial Communication Interface with FIFO
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6 //
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7 //=============================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //=============================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors:Haruki Kashiwaya
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36 // Date: 2000-08-09
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37 // Description: Simple driver for the SH Serial Communication Interface
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38 // The driver can be used for the SCIF modules.
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39 // Clients of this file can configure the behavior with:
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40 // CYGNUM_SCIF_PORTS: number of SCI ports
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41 //
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42 //####DESCRIPTIONEND####
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43 //
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44 //=============================================================================
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45
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46 #include <pkgconf/hal.h>
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47
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48 #ifdef CYGNUM_HAL_SH_SH4_SCIF_PORTS
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49
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50 #include <cyg/hal/hal_io.h> // IO macros
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51 #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
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52 #include <cyg/hal/hal_misc.h> // Helper functions
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53 #include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
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54 #include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP
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55 #include <cyg/hal/hal_if.h> // Calling-if API
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56 #include <cyg/hal/sh_regs.h> // serial register definitions
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57 #include <cyg/hal/sh_stub.h> // target_register_t
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58
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59 #include <cyg/hal/sh4_scif.h> // our header
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60
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61 //--------------------------------------------------------------------------
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62
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63 void
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64 cyg_hal_plf_scif_init_channel(const channel_data_t* chan)
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65 {
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66 cyg_uint8* base = chan->base;
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67 cyg_uint16 tmp;
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68 cyg_uint16 sr;
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69
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70 // Disable everything.
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71 HAL_WRITE_UINT16(base+_REG_SCSCR, 0);
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72
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73 // Reset FIFO.
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74 HAL_WRITE_UINT16(base+_REG_SCFCR,
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75 CYGARC_REG_SCFCR2_TFRST|CYGARC_REG_SCFCR2_RFRST);
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76
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77 // 8-1-no parity.
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78 HAL_WRITE_UINT16(base+_REG_SCSMR, 0);
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79
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80 // Set speed to 38400
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81 HAL_READ_UINT16(base+_REG_SCSMR, tmp);
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82 tmp &= ~CYGARC_REG_SCSMR2_CKSx_MASK;
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83 tmp |= CYGARC_SCBRR_CKSx(38400);
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84 HAL_WRITE_UINT16(base+_REG_SCSMR, tmp);
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85 HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(38400));
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86
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87 // Let things settle: Here we should should wait the equivalent of
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88 // one bit interval, i.e. 1/38400 second, but until we have
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89 // something like the Linux delay loop, it's hard to do reliably. So
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90 // just move on and hope for the best (this is unlikely to cause
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91 // problems since the CPU has just come out of reset anyway).
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92
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93 // Clear status register (read back first).
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94 HAL_READ_UINT16(base+_REG_SCFSR, sr);
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95 HAL_WRITE_UINT16(base+_REG_SCFSR, 0);
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96
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97 // Bring FIFO out of reset and set to trigger on every char in
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98 // FIFO (or C-c input would not be processed).
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99 HAL_WRITE_UINT16(base+_REG_SCFCR,
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100 CYGARC_REG_SCFCR2_RTRG_1|CYGARC_REG_SCFCR2_TTRG_1);
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101
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102 // Leave Tx/Rx interrupts disabled, but enable Tx/Rx
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103 HAL_WRITE_UINT16(base+_REG_SCSCR,
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104 CYGARC_REG_SCSCR2_TE|CYGARC_REG_SCSCR2_RE);
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105 }
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106
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107 static cyg_bool
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108 cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch)
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109 {
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110 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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111 cyg_uint16 fdr, sr;
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112
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113 HAL_READ_UINT16(base+_REG_SCFDR, fdr);
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114 if ((fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK) == 0)
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115 return false;
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116
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117 HAL_READ_UINT8(base+_REG_SCFRDR, *ch);
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118
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119 // Clear FIFO full flag (read before clearing)
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120 HAL_READ_UINT16(base+_REG_SCFSR, sr);
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121 HAL_WRITE_UINT16(base+_REG_SCFSR,
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122 CYGARC_REG_SCSSR2_CLEARMASK & ~CYGARC_REG_SCSSR2_RDF);
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123
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124 return true;
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125 }
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126
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127 cyg_uint8
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128 cyg_hal_plf_scif_getc(void* __ch_data)
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129 {
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130 cyg_uint8 ch;
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131 CYGARC_HAL_SAVE_GP();
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132
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133 while(!cyg_hal_plf_scif_getc_nonblock(__ch_data, &ch));
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134
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135 CYGARC_HAL_RESTORE_GP();
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136 return ch;
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137 }
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138
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139 void
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140 cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c)
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141 {
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142 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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143 cyg_uint16 fdr, sr;
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144 CYGARC_HAL_SAVE_GP();
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145
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146 do {
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147 HAL_READ_UINT16(base+_REG_SCFDR, fdr);
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148 } while (((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) >> CYGARC_REG_SCFDR2_TCOUNT_shift) == 16);
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149
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150 HAL_WRITE_UINT8(base+_REG_SCFTDR, c);
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151
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152 // Clear FIFO-empty/transmit end flags (read back SR first)
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153 HAL_READ_UINT16(base+_REG_SCFSR, sr);
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154 HAL_WRITE_UINT16(base+_REG_SCFSR, CYGARC_REG_SCSSR2_CLEARMASK
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155 & ~(CYGARC_REG_SCSSR2_TDFE | CYGARC_REG_SCSSR2_TEND ));
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156
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157 // Hang around until the character has been safely sent.
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158 do {
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159 HAL_READ_UINT16(base+_REG_SCFDR, fdr);
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160 } while ((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) != 0);
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161
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162 CYGARC_HAL_RESTORE_GP();
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163 }
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164
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165 #if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
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166 || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)
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167
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168 static channel_data_t channels[CYGNUM_HAL_SH_SH4_SCIF_PORTS];
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169
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170 static void
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171 cyg_hal_plf_scif_write(void* __ch_data, const cyg_uint8* __buf,
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172 cyg_uint32 __len)
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173 {
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174 CYGARC_HAL_SAVE_GP();
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175
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176 while(__len-- > 0)
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177 cyg_hal_plf_scif_putc(__ch_data, *__buf++);
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178
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179 CYGARC_HAL_RESTORE_GP();
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180 }
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181
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182 static void
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183 cyg_hal_plf_scif_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
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184 {
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185 CYGARC_HAL_SAVE_GP();
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186
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187 while(__len-- > 0)
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188 *__buf++ = cyg_hal_plf_scif_getc(__ch_data);
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189
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190 CYGARC_HAL_RESTORE_GP();
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191 }
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192
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193 cyg_bool
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194 cyg_hal_plf_scif_getc_timeout(void* __ch_data, cyg_uint8* ch)
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195 {
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196 channel_data_t* chan = (channel_data_t*)__ch_data;
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197 int delay_count;
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198 cyg_bool res;
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199 CYGARC_HAL_SAVE_GP();
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200
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201 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
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202
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203 for(;;) {
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204 res = cyg_hal_plf_scif_getc_nonblock(__ch_data, ch);
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205 if (res || 0 == delay_count--)
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206 break;
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207
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208 CYGACC_CALL_IF_DELAY_US(100);
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209 }
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210
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211 CYGARC_HAL_RESTORE_GP();
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212 return res;
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213 }
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214
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215 static int
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216 cyg_hal_plf_scif_control(void *__ch_data, __comm_control_cmd_t __func, ...)
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217 {
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218 static int irq_state = 0;
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219 channel_data_t* chan = (channel_data_t*)__ch_data;
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220 cyg_uint8 scr;
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221 int ret = 0;
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222 CYGARC_HAL_SAVE_GP();
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223
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224 switch (__func) {
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225 case __COMMCTL_IRQ_ENABLE:
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226 irq_state = 1;
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227 HAL_INTERRUPT_UNMASK(chan->isr_vector);
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228 HAL_READ_UINT16(chan->base+_REG_SCSCR, scr);
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229 scr |= CYGARC_REG_SCSCR2_RIE;
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230 HAL_WRITE_UINT16(chan->base+_REG_SCSCR, scr);
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231 break;
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232 case __COMMCTL_IRQ_DISABLE:
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233 ret = irq_state;
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234 irq_state = 0;
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235 HAL_INTERRUPT_UNMASK(chan->isr_vector);
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236 HAL_READ_UINT16(chan->base+_REG_SCSCR, scr);
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237 scr &= ~CYGARC_REG_SCSCR2_RIE;
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238 HAL_WRITE_UINT16(chan->base+_REG_SCSCR, scr);
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239 break;
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240 case __COMMCTL_DBG_ISR_VECTOR:
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241 ret = chan->isr_vector;
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242 break;
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243 case __COMMCTL_SET_TIMEOUT:
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244 {
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245 va_list ap;
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246
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247 va_start(ap, __func);
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248
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249 ret = chan->msec_timeout;
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250 chan->msec_timeout = va_arg(ap, cyg_uint32);
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251
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252 va_end(ap);
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253 }
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254 default:
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255 break;
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256 }
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257 CYGARC_HAL_RESTORE_GP();
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258 return ret;
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259 }
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260
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261 static int
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262 cyg_hal_plf_scif_isr(void *__ch_data, int* __ctrlc,
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263 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
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264 {
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265 cyg_uint8 c;
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266 cyg_uint16 fdr, sr;
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267 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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268 int res = 0;
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269 CYGARC_HAL_SAVE_GP();
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270
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271 *__ctrlc = 0;
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272 HAL_READ_UINT16(base+_REG_SCFDR, fdr);
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273 if ((fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK) != 0) {
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274 HAL_READ_UINT8(base+_REG_SCFRDR, c);
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275
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276 // Clear buffer full flag (read back first).
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277 HAL_READ_UINT16(base+_REG_SCFSR, sr);
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278 HAL_WRITE_UINT16(base+_REG_SCFSR,
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279 CYGARC_REG_SCSSR2_CLEARMASK & ~CYGARC_REG_SCSSR2_RDF);
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280
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281 if( cyg_hal_is_break( &c , 1 ) )
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282 *__ctrlc = 1;
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283
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284 res = CYG_ISR_HANDLED;
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285 }
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286
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287 CYGARC_HAL_RESTORE_GP();
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288 return res;
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289 }
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290
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291 void
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292 cyg_hal_plf_scif_init(int scif_index, int comm_index,
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293 int rcv_vect, cyg_uint8* base)
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294 {
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295 channel_data_t* chan = &channels[scif_index];
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296 hal_virtual_comm_table_t* comm;
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297 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
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298
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299 // Initialize channel table
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300 chan->base = base;
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301 chan->isr_vector = rcv_vect;
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302 chan->msec_timeout = 1000;
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303
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304 // Disable interrupts.
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305 HAL_INTERRUPT_MASK(chan->isr_vector);
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306
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307 // Init channel
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308 cyg_hal_plf_scif_init_channel(chan);
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309
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310 // Setup procs in the vector table
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311
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312 // Initialize channel procs
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313 CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index);
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314 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
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315 CYGACC_COMM_IF_CH_DATA_SET(*comm, chan);
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316 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_scif_write);
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317 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_scif_read);
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318 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_scif_putc);
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319 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_scif_getc);
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320 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_scif_control);
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321 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_scif_isr);
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322 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_scif_getc_timeout);
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323
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324 // Restore original console
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325 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
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326 }
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327
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328 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES
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329
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330 #endif // CYGNUM_HAL_SH_SH4_SCIF_PORTS
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331
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332 //-----------------------------------------------------------------------------
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333 // end of sh4_scif.c