Mercurial > ecos
annotate packages/hal/mips/arch/current/include/hal_intr.h @ 10:d3fbcdfa1b2f ecos-sw-1999-05-29
Merge from eCos master repository on 1999-05-29-00:13:11-BST
| author | jlarmour |
|---|---|
| date | Fri, 28 May 1999 16:43:09 +0000 |
| parents | ece80412419a |
| children | 7253dcc42a09 |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_HAL_INTR_H |
| 2 #define CYGONCE_HAL_HAL_INTR_H | |
| 3 | |
| 2 | 4 //========================================================================== |
| 0 | 5 // |
| 2 | 6 // hal_intr.h |
| 0 | 7 // |
| 2 | 8 // HAL Interrupt and clock support |
| 0 | 9 // |
| 2 | 10 //========================================================================== |
| 0 | 11 //####COPYRIGHTBEGIN#### |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 29 // ------------------------------------------- |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 2 | 32 //========================================================================== |
| 0 | 33 //#####DESCRIPTIONBEGIN#### |
| 34 // | |
| 2 | 35 // Author(s): nickg |
| 36 // Contributors: nickg, jskov, | |
| 37 // gthomas, jlarmour | |
| 38 // Date: 1999-02-16 | |
| 39 // Purpose: Define Interrupt support | |
| 40 // Description: The macros defined here provide the HAL APIs for handling | |
| 41 // interrupts and the clock. | |
| 0 | 42 // |
| 43 // Usage: | |
| 2 | 44 // #include <cyg/hal/hal_intr.h> |
| 45 // ... | |
| 46 // | |
| 0 | 47 // |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 2 | 50 //========================================================================== |
| 0 | 51 |
| 52 #include <pkgconf/hal.h> | |
| 53 | |
| 54 #include <cyg/infra/cyg_type.h> | |
| 55 #include <cyg/hal/hal_io.h> | |
| 56 | |
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57 #include <cyg/hal/var_intr.h> |
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58 |
| 2 | 59 //-------------------------------------------------------------------------- |
| 60 // MIPS vectors. | |
| 0 | 61 |
| 2 | 62 // These are the exception codes presented in the Cause register and |
| 63 // correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET | |
| 0 | 64 |
| 2 | 65 // External interrupt |
| 66 #define CYGNUM_HAL_VECTOR_INTERRUPT 0 | |
| 67 // TLB modification exception | |
| 68 #define CYGNUM_HAL_VECTOR_TLB_MOD 1 | |
| 69 // TLB miss (Load or IFetch) | |
| 70 #define CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL 2 | |
| 71 // TLB miss (Store) | |
| 72 #define CYGNUM_HAL_VECTOR_TLB_STORE_REFILL 3 | |
| 73 // Address error (Load or Ifetch) | |
| 74 #define CYGNUM_HAL_VECTOR_LOAD_ADDRESS 4 | |
| 75 // Address error (store) | |
| 76 #define CYGNUM_HAL_VECTOR_STORE_ADDRESS 5 | |
| 77 // Bus error (Ifetch) | |
| 78 #define CYGNUM_HAL_VECTOR_IBE 6 | |
| 79 // Bus error (data load or store) | |
| 80 #define CYGNUM_HAL_VECTOR_DBE 7 | |
| 81 // System call | |
| 82 #define CYGNUM_HAL_VECTOR_SYSTEM_CALL 8 | |
| 83 // Break point | |
| 84 #define CYGNUM_HAL_VECTOR_BREAKPOINT 9 | |
| 85 // Reserved instruction | |
| 86 #define CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION 10 | |
| 87 // Coprocessor unusable | |
| 88 #define CYGNUM_HAL_VECTOR_COPROCESSOR 11 | |
| 89 // Arithmetic overflow | |
| 90 #define CYGNUM_HAL_VECTOR_OVERFLOW 12 | |
| 91 // Reserved | |
| 92 #define CYGNUM_HAL_VECTOR_RESERVED_13 13 | |
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93 // Floating point exception |
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94 #ifdef CYGHWR_HAL_MIPS_FPU |
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95 #define CYGNUM_HAL_VECTOR_FPE 15 |
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96 #endif |
| 0 | 97 |
| 2 | 98 #define CYGNUM_HAL_VSR_MIN 0 |
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99 #define CYGNUM_HAL_VSR_MAX 15 |
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100 #define CYGNUM_HAL_VSR_COUNT 16 |
| 2 | 101 |
| 102 // Exception vectors. These are the values used when passed out to an | |
| 103 // external exception handler using cyg_hal_deliver_exception() | |
| 0 | 104 |
| 2 | 105 #define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_TLB_MOD |
| 106 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \ | |
| 107 CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL | |
| 108 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_WRITE \ | |
| 109 CYGNUM_HAL_VECTOR_TLB_STORE_REFILL | |
| 110 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ | |
| 111 CYGNUM_HAL_VECTOR_LOAD_ADDRESS | |
| 112 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_WRITE \ | |
| 113 CYGNUM_HAL_VECTOR_STORE_ADDRESS | |
| 114 #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_IBE | |
| 115 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DBE | |
| 116 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL | |
| 117 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_BREAKPOINT | |
| 118 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \ | |
| 119 CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION | |
| 120 #define CYGNUM_HAL_EXCEPTION_COPROCESSOR CYGNUM_HAL_VECTOR_COPROCESSOR | |
| 121 #define CYGNUM_HAL_EXCEPTION_OVERFLOW CYGNUM_HAL_VECTOR_OVERFLOW | |
| 122 | |
| 123 // Min/Max exception numbers and how many there are | |
| 124 #define CYGNUM_HAL_EXCEPTION_MIN 1 | |
| 125 #define CYGNUM_HAL_EXCEPTION_MAX 13 | |
| 126 #define CYGNUM_HAL_EXCEPTION_COUNT 13 | |
| 0 | 127 |
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128 |
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129 #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED |
| 0 | 130 |
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131 // the default for all MIPS variants is to use the 6 bits |
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132 // in the cause register. |
| 0 | 133 |
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134 #define CYGNUM_HAL_INTERRUPT_0 0 |
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135 #define CYGNUM_HAL_INTERRUPT_1 1 |
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136 #define CYGNUM_HAL_INTERRUPT_2 2 |
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137 #define CYGNUM_HAL_INTERRUPT_3 3 |
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138 #define CYGNUM_HAL_INTERRUPT_4 4 |
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139 #define CYGNUM_HAL_INTERRUPT_5 5 |
| 0 | 140 |
| 2 | 141 // Min/Max ISR numbers and how many there are |
| 142 #define CYGNUM_HAL_ISR_MIN 0 | |
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143 #define CYGNUM_HAL_ISR_MAX 5 |
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144 #define CYGNUM_HAL_ISR_COUNT 6 |
| 0 | 145 |
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146 // The vector used by the Real time clock. The default here is to use |
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147 // interrupt 5, which is connected to the counter/comparator registers |
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148 // in many MIPS variants. |
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149 |
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150 #ifndef CYGNUM_HAL_INTERRUPT_RTC |
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151 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_5 |
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152 #endif |
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153 |
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154 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED |
| 0 | 155 |
| 156 #endif | |
| 157 | |
| 2 | 158 //-------------------------------------------------------------------------- |
| 0 | 159 // Static data used by HAL |
| 160 | |
| 161 // ISR tables | |
| 2 | 162 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; |
| 163 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; | |
| 164 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; | |
| 0 | 165 |
| 166 // VSR table | |
| 2 | 167 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1]; |
| 0 | 168 |
| 2 | 169 //-------------------------------------------------------------------------- |
| 0 | 170 // Default ISR |
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171 // The #define is used to test whether this routine exists, and to allow |
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172 // us to call it. |
| 0 | 173 |
| 174 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); | |
| 175 | |
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176 #define HAL_DEFAULT_ISR hal_default_isr |
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177 |
| 2 | 178 //-------------------------------------------------------------------------- |
| 0 | 179 // Interrupt state storage |
| 180 | |
| 181 typedef cyg_uint32 CYG_INTERRUPT_STATE; | |
| 182 | |
| 2 | 183 //-------------------------------------------------------------------------- |
| 0 | 184 // Interrupt control macros |
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185 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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186 // that might otherwise cause following code to run in the wrong state or |
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187 // cause a resource conflict. |
| 0 | 188 |
| 189 #define HAL_DISABLE_INTERRUPTS(_old_) \ | |
| 190 { \ | |
| 191 asm volatile ( \ | |
| 192 "mfc0 $8,$12; nop;" \ | |
| 193 "move %0,$8;" \ | |
| 194 "and $8,$8,0XFFFFFFFE;" \ | |
| 195 "mtc0 $8,$12;" \ | |
| 196 "nop; nop; nop;" \ | |
| 197 "and %0,%0,0X1;" \ | |
| 198 : "=r"(_old_) \ | |
| 199 : \ | |
| 200 : "$8" \ | |
| 201 ); \ | |
| 202 } | |
| 203 | |
| 204 #define HAL_ENABLE_INTERRUPTS() \ | |
| 205 { \ | |
| 206 asm volatile ( \ | |
| 207 "mfc0 $8,$12; nop;" \ | |
| 208 "or $8,$8,1;" \ | |
| 209 "mtc0 $8,$12;" \ | |
| 210 "nop; nop; nop;" \ | |
| 211 : \ | |
| 212 : \ | |
| 213 : "$8" \ | |
| 214 ); \ | |
| 215 } | |
| 216 | |
| 217 #define HAL_RESTORE_INTERRUPTS(_old_) \ | |
| 218 { \ | |
| 219 asm volatile ( \ | |
| 220 "mfc0 $8,$12; nop;" \ | |
| 221 "and %0,%0,0x1;" \ | |
| 222 "or $8,$8,%0;" \ | |
| 223 "mtc0 $8,$12;" \ | |
| 224 "nop; nop; nop;" \ | |
| 225 : \ | |
| 226 : "r"(_old_) \ | |
| 227 : "$8" \ | |
| 228 ); \ | |
| 229 } | |
| 230 | |
| 231 #define HAL_QUERY_INTERRUPTS( _state_ ) \ | |
| 232 { \ | |
| 233 asm volatile ( \ | |
| 234 "mfc0 %0,$12; nop;" \ | |
| 235 "and %0,%0,0x1;" \ | |
| 236 : "=r"(_state_) \ | |
| 237 : \ | |
| 238 : "$8" \ | |
| 239 ); \ | |
| 240 } | |
| 241 | |
| 2 | 242 //-------------------------------------------------------------------------- |
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243 // Routine to execute DSRs using separate interrupt stack |
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244 |
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245 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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246 externC void hal_interrupt_stack_call_pending_DSRs(void); |
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247 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ |
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248 hal_interrupt_stack_call_pending_DSRs() |
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249 |
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250 // these are offered solely for stack usage testing |
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251 // if they are not defined, then there is no interrupt stack. |
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252 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base |
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253 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack |
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254 // use them to declare these extern however you want: |
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255 // extern char HAL_INTERRUPT_STACK_BASE[]; |
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256 // extern char HAL_INTERRUPT_STACK_TOP[]; |
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257 // is recommended |
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258 #endif |
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259 |
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260 //-------------------------------------------------------------------------- |
| 0 | 261 // Vector translation. |
| 262 // For chained interrupts we only have a single vector though which all | |
| 263 // are passed. For unchained interrupts we have a vector per interrupt. | |
| 264 | |
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265 #ifndef HAL_TRANSLATE_VECTOR |
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266 |
| 0 | 267 #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) |
| 268 | |
| 269 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0 | |
| 270 | |
| 271 #else | |
| 272 | |
| 273 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_) | |
| 274 | |
| 275 #endif | |
| 276 | |
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277 #endif |
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278 |
| 2 | 279 //-------------------------------------------------------------------------- |
| 0 | 280 // Interrupt and VSR attachment macros |
| 281 | |
| 2 | 282 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ |
| 283 CYG_MACRO_START \ | |
| 284 cyg_uint32 _index_; \ | |
| 285 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ | |
| 286 \ | |
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287 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ |
| 2 | 288 (_state_) = 0; \ |
| 289 else \ | |
| 290 (_state_) = 1; \ | |
| 291 CYG_MACRO_END | |
| 292 | |
| 293 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ | |
| 294 { \ | |
| 295 cyg_uint32 _index_; \ | |
| 296 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ | |
| 297 \ | |
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298 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ |
| 2 | 299 { \ |
| 300 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ | |
| 301 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ | |
| 302 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ | |
| 303 } \ | |
| 0 | 304 } |
| 305 | |
| 306 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ | |
| 307 { \ | |
| 308 cyg_uint32 _index_; \ | |
| 309 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ | |
| 310 \ | |
| 311 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ | |
| 312 { \ | |
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313 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \ |
| 0 | 314 hal_interrupt_data[_index_] = 0; \ |
| 315 hal_interrupt_objects[_index_] = 0; \ | |
| 316 } \ | |
| 317 } | |
| 318 | |
| 319 #define HAL_VSR_GET( _vector_, _pvsr_ ) \ | |
| 320 *(_pvsr_) = (void (*)())hal_vsr_table[_vector_]; | |
| 321 | |
| 322 | |
| 2 | 323 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \ |
| 324 if( _poldvsr_ != NULL) \ | |
| 325 *(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \ | |
| 326 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ | |
| 327 CYG_MACRO_END | |
| 328 | |
| 329 // This is an ugly name, but what it means is: grab the VSR back to eCos | |
| 330 // internal handling, or if you like, the default handler. But if | |
| 331 // cooperating with GDB and CygMon, the default behaviour is to pass most | |
| 332 // exceptions to CygMon. This macro undoes that so that eCos handles the | |
| 333 // exception. So use it with care. | |
| 0 | 334 |
| 2 | 335 externC void __default_exception_vsr(void); |
| 336 externC void __default_interrupt_vsr(void); | |
| 337 | |
| 338 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \ | |
| 339 HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \ | |
| 340 ? (CYG_ADDRESS)__default_interrupt_vsr \ | |
| 341 : (CYG_ADDRESS)__default_exception_vsr, \ | |
| 342 _poldvsr_ ); \ | |
| 343 CYG_MACRO_END | |
| 344 | |
| 345 //-------------------------------------------------------------------------- | |
| 0 | 346 // Interrupt controller access |
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347 // The default code here simply uses the fields present in the CP0 status |
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348 // and cause registers to implement this functionality. |
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349 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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350 // that might otherwise cause following code to run in the wrong state or |
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351 // cause a resource conflict. |
| 0 | 352 |
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353 #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED |
| 0 | 354 |
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355 #define HAL_INTERRUPT_MASK( _vector_ ) \ |
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356 CYG_MACRO_START \ |
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357 asm volatile ( \ |
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358 "mfc0 $3,$12\n" \ |
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359 "la $2,0x00000400\n" \ |
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360 "sllv $2,$2,%0\n" \ |
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361 "nor $2,$2,$0\n" \ |
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362 "and $3,$3,$2\n" \ |
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363 "mtc0 $3,$12\n" \ |
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364 "nop; nop; nop\n" \ |
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365 : \ |
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366 : "r"(_vector_) \ |
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367 : "$2", "$3" \ |
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368 ); \ |
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369 CYG_MACRO_END |
| 0 | 370 |
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371 #define HAL_INTERRUPT_UNMASK( _vector_ ) \ |
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372 CYG_MACRO_START \ |
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373 asm volatile ( \ |
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374 "mfc0 $3,$12\n" \ |
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375 "la $2,0x00000400\n" \ |
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376 "sllv $2,$2,%0\n" \ |
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377 "or $3,$3,$2\n" \ |
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378 "mtc0 $3,$12\n" \ |
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379 "nop; nop; nop\n" \ |
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380 : \ |
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381 : "r"(_vector_) \ |
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382 : "$2", "$3" \ |
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383 ); \ |
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384 CYG_MACRO_END |
| 0 | 385 |
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386 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ |
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387 CYG_MACRO_START \ |
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388 asm volatile ( \ |
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389 "mfc0 $3,$13\n" \ |
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390 "la $2,0x00000400\n" \ |
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391 "sllv $2,$2,%0\n" \ |
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392 "nor $2,$2,$0\n" \ |
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393 "and $3,$3,$2\n" \ |
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394 "mtc0 $3,$13\n" \ |
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395 "nop; nop; nop\n" \ |
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396 : \ |
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397 : "r"(_vector_) \ |
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398 : "$2", "$3" \ |
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399 ); \ |
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400 CYG_MACRO_END |
| 0 | 401 |
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402 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) |
| 0 | 403 |
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404 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) |
| 0 | 405 |
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406 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED |
| 0 | 407 |
| 408 #endif | |
| 409 | |
| 2 | 410 //-------------------------------------------------------------------------- |
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411 // Clock control. |
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412 // This code uses the count and compare registers that are present in many |
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413 // MIPS variants. |
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414 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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415 // that might otherwise cause following code to run in the wrong state or |
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416 // cause a resource conflict. |
| 0 | 417 |
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418 #ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED |
| 2 | 419 |
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420 #define HAL_CLOCK_INITIALIZE( _period_ ) \ |
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421 CYG_MACRO_START \ |
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422 asm volatile ( \ |
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423 "mtc0 $0,$9\n" \ |
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424 "nop; nop; nop\n" \ |
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425 "mtc0 %0,$11\n" \ |
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426 "nop; nop; nop\n" \ |
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427 : \ |
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428 : "r"(_period_) \ |
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429 ); \ |
| 2 | 430 CYG_MACRO_END |
| 431 | |
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432 #define HAL_CLOCK_RESET( _vector_, _period_ ) \ |
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433 CYG_MACRO_START \ |
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434 asm volatile ( \ |
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435 "mtc0 $0,$9\n" \ |
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436 "nop; nop; nop\n" \ |
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437 "mtc0 %0,$11\n" \ |
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438 "nop; nop; nop\n" \ |
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439 : \ |
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440 : "r"(_period_) \ |
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441 ); \ |
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442 CYG_MACRO_END |
| 2 | 443 |
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444 #define HAL_CLOCK_READ( _pvalue_ ) \ |
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445 CYG_MACRO_START \ |
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446 register CYG_WORD32 result; \ |
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447 asm volatile ( \ |
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448 "mfc0 %0,$9\n" \ |
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449 : "=r"(result) \ |
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450 ); \ |
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451 *(_pvalue_) = result; \ |
| 2 | 452 CYG_MACRO_END |
| 453 | |
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454 #define CYGHWR_HAL_CLOCK_CONTROL_DEFINED |
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455 |
| 2 | 456 #endif |
| 457 | |
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458 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \ |
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459 !defined(HAL_CLOCK_LATENCY) |
| 2 | 460 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_) |
| 461 #endif | |
| 0 | 462 |
| 2 | 463 //-------------------------------------------------------------------------- |
| 0 | 464 #endif // ifndef CYGONCE_HAL_HAL_INTR_H |
| 465 // End of hal_intr.h |
