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annotate packages/devs/serial/sh/sci/current/src/sh_sci_serial.c @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents e2d866e32dac
children d2c90368aeef
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1 //==========================================================================
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2 //
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3 // io/serial/sh/sh_sci_serial.c
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4 //
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5 // SH Serial SCI I/O Interface Module (interrupt driven)
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6 //
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7 //==========================================================================
208
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): jskov
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44 // Contributors:gthomas, jskov
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45 // Date: 1999-05-24
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46 // Purpose: SH Serial I/O module (interrupt driven version)
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47 // Description:
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48 //
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49 // Note: Since interrupt sources from the same SCI channel share the same
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50 // interrupt level, there is no risk of races when altering the
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51 // channel's control register from ISRs and DSRs. However, when
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52 // altering the control register from user-level code, interrupts
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53 // must be disabled while the register is being accessed.
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54 //
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55 // FIXME: Receiving in polled mode prevents duplex transfers from working for
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56 // some reason.
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57 //####DESCRIPTIONEND####
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58 //==========================================================================
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59
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60 #include <pkgconf/io_serial.h>
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61 #include <pkgconf/io.h>
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62
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63 // FIXME: This is necessary since the SCIF driver may be overriding
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64 // CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two
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65 // different drivers.
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66 #include <pkgconf/io_serial_sh_sci.h>
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67
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68 #include <cyg/io/io.h>
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69 #include <cyg/hal/hal_intr.h>
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70 #include <cyg/io/devtab.h>
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71 #include <cyg/infra/diag.h>
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72 #include <cyg/io/serial.h>
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73
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74 #include <cyg/hal/sh_regs.h>
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75
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76 // Only compile driver if an inline file with driver details was selected.
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77 #ifdef CYGDAT_IO_SERIAL_SH_SCI_INL
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78
208
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79 // Find the SCI controller register layout from the SCI0 definitions
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80 #if defined(CYGARC_REG_SCI_SCSMR0)
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81 # define SCI_SCSMR (CYGARC_REG_SCI_SCSMR0-CYGARC_REG_SCI_SCSMR0) // serial mode register
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82 # define SCI_SCBRR (CYGARC_REG_SCI_SCBRR0-CYGARC_REG_SCI_SCSMR0) // bit rate register
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83 # define SCI_SCSCR (CYGARC_REG_SCI_SCSCR0-CYGARC_REG_SCI_SCSMR0) // serial control register
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84 # define SCI_SCTDR (CYGARC_REG_SCI_SCTDR0-CYGARC_REG_SCI_SCSMR0) // transmit data register
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85 # define SCI_SCSSR (CYGARC_REG_SCI_SCSSR0-CYGARC_REG_SCI_SCSMR0) // serial status register
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86 # define SCI_SCRDR (CYGARC_REG_SCI_SCRDR0-CYGARC_REG_SCI_SCSMR0) // receive data register
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87 # define SCI_SCSPTR (CYGARC_REG_SCI_SCSPTR0-CYGARC_REG_SCI_SCSMR0)// serial port register
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88 #elif defined(CYGARC_REG_SCI_SCSMR)
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89 # define SCI_SCSMR (CYGARC_REG_SCI_SCSMR-CYGARC_REG_SCI_SCSMR) // serial mode register
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90 # define SCI_SCBRR (CYGARC_REG_SCI_SCBRR-CYGARC_REG_SCI_SCSMR) // bit rate register
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91 # define SCI_SCSCR (CYGARC_REG_SCI_SCSCR-CYGARC_REG_SCI_SCSMR) // serial control register
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92 # define SCI_SCTDR (CYGARC_REG_SCI_SCTDR-CYGARC_REG_SCI_SCSMR) // transmit data register
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93 # define SCI_SCSSR (CYGARC_REG_SCI_SCSSR-CYGARC_REG_SCI_SCSMR) // serial status register
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94 # define SCI_SCRDR (CYGARC_REG_SCI_SCRDR-CYGARC_REG_SCI_SCSMR) // receive data register
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95 # define SCI_SCSPTR (CYGARC_REG_SCI_SCSPTR-CYGARC_REG_SCI_SCSMR) // serial port register
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96 #else
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97 # error "Missing register offsets"
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98 #endif
124
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99
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100 static short select_word_length[] = {
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101 -1,
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102 -1,
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103 CYGARC_REG_SCI_SCSMR_CHR, // 7 bits
124
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104 0 // 8 bits
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105 };
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106
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107 static short select_stop_bits[] = {
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108 -1,
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109 0, // 1 stop bit
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110 -1,
208
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111 CYGARC_REG_SCI_SCSMR_STOP // 2 stop bits
124
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112 };
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113
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114 static short select_parity[] = {
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115 0, // No parity
208
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116 CYGARC_REG_SCI_SCSMR_PE, // Even parity
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117 CYGARC_REG_SCI_SCSMR_PE|CYGARC_REG_SCI_SCSMR_OE, // Odd parity
124
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118 -1,
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119 -1
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120 };
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121
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122 static unsigned short select_baud[] = {
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123 0, // Unused
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124 CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50),
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125 CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75),
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126 CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110),
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127 CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134),
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128 CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150),
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129 CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200),
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130 CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300),
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131 CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600),
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132 CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200),
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133 CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800),
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134 CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400),
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135 CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600),
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136 CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800),
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137 CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200),
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138 CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600),
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139 CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400),
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140 CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200),
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141 CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400),
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142 CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600),
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143 CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200),
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144 CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400)
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145 };
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146
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147
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148 typedef struct sh_sci_info {
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149 CYG_ADDRWORD data; // Pointer to data register
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150
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151 CYG_WORD er_int_num, // Error interrupt number
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152 rx_int_num, // Receive interrupt number
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153 tx_int_num; // Transmit interrupt number
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154
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155 CYG_ADDRWORD ctrl_base; // Base address of SCI controller
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156
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157 cyg_interrupt serial_er_interrupt,
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158 serial_rx_interrupt,
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159 serial_tx_interrupt;
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160 cyg_handle_t serial_er_interrupt_handle,
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161 serial_rx_interrupt_handle,
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162 serial_tx_interrupt_handle;
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163
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164 bool tx_enabled;
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165 } sh_sci_info;
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166
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167 static bool sh_serial_init(struct cyg_devtab_entry *tab);
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168 static bool sh_serial_putc(serial_channel *chan, unsigned char c);
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169 static Cyg_ErrNo sh_serial_lookup(struct cyg_devtab_entry **tab,
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170 struct cyg_devtab_entry *sub_tab,
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171 const char *name);
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172 static unsigned char sh_serial_getc(serial_channel *chan);
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173 static Cyg_ErrNo sh_serial_set_config(serial_channel *chan, cyg_uint32 key,
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174 const void *xbuf, cyg_uint32 *len);
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175 static void sh_serial_start_xmit(serial_channel *chan);
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176 static void sh_serial_stop_xmit(serial_channel *chan);
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177
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178 static cyg_uint32 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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179 static void sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count,
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180 cyg_addrword_t data);
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181 static cyg_uint32 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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182 static void sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count,
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183 cyg_addrword_t data);
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184 static cyg_uint32 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data);
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185 static void sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count,
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186 cyg_addrword_t data);
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187
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188 static SERIAL_FUNS(sh_serial_funs,
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189 sh_serial_putc,
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190 sh_serial_getc,
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191 sh_serial_set_config,
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192 sh_serial_start_xmit,
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193 sh_serial_stop_xmit
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194 );
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195
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196 #include CYGDAT_IO_SERIAL_SH_SCI_INL
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197
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198 // Internal function to actually configure the hardware to desired baud rate,
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199 // etc.
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200 static bool
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201 sh_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config,
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202 bool init)
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203 {
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204 cyg_uint16 baud_divisor = select_baud[new_config->baud];
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205 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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206 cyg_uint8 _scr, _smr;
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207
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208 // Check configuration request
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209 if ((-1 == select_word_length[(new_config->word_length -
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210 CYGNUM_SERIAL_WORD_LENGTH_5)])
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211 || -1 == select_stop_bits[new_config->stop]
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212 || -1 == select_parity[new_config->parity]
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213 || baud_divisor == 0)
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214 return false;
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215
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216 // Disable SCI interrupts while changing hardware
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217 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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218 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, 0);
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219
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220 // Set databits, stopbits and parity.
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221 _smr = select_word_length[(new_config->word_length -
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222 CYGNUM_SERIAL_WORD_LENGTH_5)] |
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223 select_stop_bits[new_config->stop] |
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224 select_parity[new_config->parity];
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225 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr);
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226
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227 // Set baud rate.
208
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228 _smr &= ~CYGARC_REG_SCI_SCSMR_CKSx_MASK;
124
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229 _smr |= baud_divisor >> 8;
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230 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr);
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231 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCBRR, baud_divisor & 0xff);
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232
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233 // Clear the status register.
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234 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, 0);
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235
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236 if (init) {
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237 // Always enable transmitter and receiver.
208
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238 _scr = CYGARC_REG_SCI_SCSCR_TE | CYGARC_REG_SCI_SCSCR_RE;
124
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239
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240 if (chan->out_cbuf.len != 0)
208
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241 _scr |= CYGARC_REG_SCI_SCSCR_TIE; // enable tx interrupts
124
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242
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243 if (chan->in_cbuf.len != 0)
208
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244 _scr |= CYGARC_REG_SCI_SCSCR_RIE; // enable rx interrupts
124
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245 }
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246
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247 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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248
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249 if (new_config != &chan->config) {
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250 chan->config = *new_config;
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251 }
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252 return true;
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253 }
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254
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255 // Function to initialize the device. Called at bootstrap time.
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256 static bool
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257 sh_serial_init(struct cyg_devtab_entry *tab)
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258 {
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259 serial_channel *chan = (serial_channel *)tab->priv;
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260 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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261 #ifdef CYGDBG_IO_INIT
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262 diag_printf("SH SERIAL init - dev: %x.%d\n",
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263 sh_chan->data, sh_chan->rx_int_num);
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264 #endif
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265 // Really only required for interrupt driven devices
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266 (chan->callbacks->serial_init)(chan);
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267
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268 if (chan->out_cbuf.len != 0) {
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269 cyg_drv_interrupt_create(sh_chan->tx_int_num,
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270 3,
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271 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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272 sh_serial_tx_ISR,
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273 sh_serial_tx_DSR,
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274 &sh_chan->serial_tx_interrupt_handle,
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275 &sh_chan->serial_tx_interrupt);
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276 cyg_drv_interrupt_attach(sh_chan->serial_tx_interrupt_handle);
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277 cyg_drv_interrupt_unmask(sh_chan->tx_int_num);
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278 sh_chan->tx_enabled = false;
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279 }
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280 if (chan->in_cbuf.len != 0) {
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281 // Receive interrupt
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282 cyg_drv_interrupt_create(sh_chan->rx_int_num,
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283 3,
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284 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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285 sh_serial_rx_ISR,
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286 sh_serial_rx_DSR,
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287 &sh_chan->serial_rx_interrupt_handle,
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288 &sh_chan->serial_rx_interrupt);
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289 cyg_drv_interrupt_attach(sh_chan->serial_rx_interrupt_handle);
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290 // Receive error interrupt
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291 cyg_drv_interrupt_create(sh_chan->er_int_num,
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292 3,
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293 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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294 sh_serial_er_ISR,
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295 sh_serial_er_DSR,
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296 &sh_chan->serial_er_interrupt_handle,
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297 &sh_chan->serial_er_interrupt);
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298 cyg_drv_interrupt_attach(sh_chan->serial_er_interrupt_handle);
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299 // This unmasks both interrupt sources.
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300 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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301 }
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302 sh_serial_config_port(chan, &chan->config, true);
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303 return true;
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304 }
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305
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306 // This routine is called when the device is "looked" up (i.e. attached)
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307 static Cyg_ErrNo
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308 sh_serial_lookup(struct cyg_devtab_entry **tab,
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309 struct cyg_devtab_entry *sub_tab,
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310 const char *name)
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311 {
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312 serial_channel *chan = (serial_channel *)(*tab)->priv;
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313
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314 // Really only required for interrupt driven devices
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315 (chan->callbacks->serial_init)(chan);
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316 return ENOERR;
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317 }
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318
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319 // Send a character to the device output buffer.
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320 // Return 'true' if character is sent to device
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321 static bool
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322 sh_serial_putc(serial_channel *chan, unsigned char c)
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323 {
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324 cyg_uint8 _ssr;
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325 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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326
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327 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
208
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328 if (_ssr & CYGARC_REG_SCI_SCSSR_TDRE) {
124
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329 // Transmit buffer is empty
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330 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCTDR, c);
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331 // Clear empty flag.
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332 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
208
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333 CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_TDRE);
124
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334 return true;
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335 } else {
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336 // No space
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337 return false;
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338 }
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339 }
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340
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341 // Fetch a character from the device input buffer, waiting if necessary
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342 static unsigned char
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343 sh_serial_getc(serial_channel *chan)
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344 {
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345 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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346 unsigned char c;
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347 cyg_uint8 _ssr;
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348
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349 do {
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350 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
208
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351 } while ((_ssr & CYGARC_REG_SCI_SCSSR_RDRF) == 0);
124
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352
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353 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, c);
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354
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355 // Clear buffer full flag.
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356 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
208
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357 CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF);
124
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358
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359 return c;
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360 }
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361
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362 // Set up the device characteristics; baud rate, etc.
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363 static Cyg_ErrNo
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364 sh_serial_set_config(serial_channel *chan, cyg_uint32 key,
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365 const void *xbuf, cyg_uint32 *len)
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366 {
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367 switch (key) {
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368 case CYG_IO_SET_CONFIG_SERIAL_INFO:
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369 {
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370 cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
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371 if ( *len < sizeof(cyg_serial_info_t) ) {
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372 return -EINVAL;
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373 }
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374 *len = sizeof(cyg_serial_info_t);
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375 if ( true != sh_serial_config_port(chan, config, false) )
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376 return -EINVAL;
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377 }
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378 break;
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379 default:
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380 return -EINVAL;
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381 }
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382 return ENOERR;
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383 }
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384
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385 // Enable the transmitter on the device
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386 static void
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387 sh_serial_start_xmit(serial_channel *chan)
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388 {
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389 cyg_uint8 _scr;
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390 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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391
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392 sh_chan->tx_enabled = true;
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393
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394 // Mask the interrupts (all sources of the unit) while changing
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395 // the CR since a rx interrupt in the middle of this would result
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396 // in a bad CR state.
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397 cyg_drv_interrupt_mask(sh_chan->rx_int_num);
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398
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399 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
208
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400 _scr |= CYGARC_REG_SCI_SCSCR_TIE; // Enable xmit interrupt
124
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401 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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402
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403 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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404 }
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405
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406 // Disable the transmitter on the device
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407 static void
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408 sh_serial_stop_xmit(serial_channel *chan)
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409 {
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410 cyg_uint8 _scr;
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411 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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412
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413 sh_chan->tx_enabled = false;
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414
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415 // Mask the interrupts (all sources of the unit) while changing
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416 // the CR since a rx interrupt in the middle of this would result
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417 // in a bad CR state.
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418 cyg_drv_interrupt_mask(sh_chan->rx_int_num);
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419
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420 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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421 _scr &= ~CYGARC_REG_SCI_SCSCR_TIE; // Disable xmit interrupt
124
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422 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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423
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424 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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425 }
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426
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427 // Serial I/O - low level tx interrupt handler (ISR)
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428 static cyg_uint32
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429 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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430 {
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431 serial_channel *chan = (serial_channel *)data;
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432 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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433 cyg_uint8 _scr;
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434
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435 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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436 _scr &= ~CYGARC_REG_SCI_SCSCR_TIE; // mask out tx interrupts
124
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437 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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438
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439 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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440 }
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441
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442 // Serial I/O - high level tx interrupt handler (DSR)
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443 static void
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444 sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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445 {
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446 serial_channel *chan = (serial_channel *)data;
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447 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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448
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449 (chan->callbacks->xmt_char)(chan);
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450
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451 if (sh_chan->tx_enabled) {
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452 cyg_uint8 _scr;
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453
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454 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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455 _scr |= CYGARC_REG_SCI_SCSCR_TIE; // unmask tx interrupts
124
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456 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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457 }
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458 }
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459
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460 // Serial I/O - low level RX interrupt handler (ISR)
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461 static cyg_uint32
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462 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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463 {
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464 serial_channel *chan = (serial_channel *)data;
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465 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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466 cyg_uint8 _scr;
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467
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468 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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469 _scr &= ~CYGARC_REG_SCI_SCSCR_RIE; // mask rx interrupts
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470 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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471 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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472 }
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473
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474 // Serial I/O - high level rx interrupt handler (DSR)
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475 static void
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476 sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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477 {
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478 serial_channel *chan = (serial_channel *)data;
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479 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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480 cyg_uint8 _ssr, _scr;
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481
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482 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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483 if (_ssr & CYGARC_REG_SCI_SCSSR_RDRF) {
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484 cyg_uint8 _c;
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485 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, _c);
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486 // Clear buffer full flag.
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487 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
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488 CYGARC_REG_SCI_SCSSR_CLEARMASK & ~CYGARC_REG_SCI_SCSSR_RDRF);
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489
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490 (chan->callbacks->rcv_char)(chan, _c);
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491 }
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492
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493 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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494 _scr |= CYGARC_REG_SCI_SCSCR_RIE; // unmask rx interrupts
124
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495 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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496 }
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497
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498 static volatile int sh_serial_error_orer = 0;
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499 static volatile int sh_serial_error_fer = 0;
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500 static volatile int sh_serial_error_per = 0;
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501
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502 // Serial I/O - low level error interrupt handler (ISR)
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503 static cyg_uint32
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504 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data)
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505 {
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506 serial_channel *chan = (serial_channel *)data;
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507 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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508 cyg_uint8 _scr;
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509
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510 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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511 _scr &= ~CYGARC_REG_SCI_SCSCR_RIE; // mask rx interrupts
124
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512 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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513 return CYG_ISR_CALL_DSR; // Cause DSR to be run
124
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514 }
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515
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516 // Serial I/O - high level error interrupt handler (DSR)
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517 static void
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518 sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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519 {
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520 serial_channel *chan = (serial_channel *)data;
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521 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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522 cyg_uint8 _ssr, _ssr2, _scr;
124
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523
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524 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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525 _ssr2 = CYGARC_REG_SCI_SCSSR_CLEARMASK;
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526
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527 if (_ssr & CYGARC_REG_SCI_SCSSR_ORER) {
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528 _ssr2 &= ~CYGARC_REG_SCI_SCSSR_ORER;
124
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529 sh_serial_error_orer++;
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530 }
208
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531 if (_ssr & CYGARC_REG_SCI_SCSSR_FER) {
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532 _ssr2 &= ~CYGARC_REG_SCI_SCSSR_FER;
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533 sh_serial_error_fer++;
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534 }
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535 if (_ssr & CYGARC_REG_SCI_SCSSR_PER) {
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536 _ssr2 &= ~CYGARC_REG_SCI_SCSSR_PER;
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537 sh_serial_error_per++;
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538 }
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539 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr2);
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540
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541 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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542 _scr |= CYGARC_REG_SCI_SCSCR_RIE; // unmask rx interrupts
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543 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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544 }
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545
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546 #endif // ifdef CYGDAT_IO_SERIAL_SH_SCI_INL