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annotate packages/hal/powerpc/arch/current/include/arch.inc @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents 435cced73e2f
children d2c90368aeef
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 ##=============================================================================
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2 ##
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3 ## arch.inc
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4 ##
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5 ## PowerPC architecture assembler header file
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6 ##
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7 ##=============================================================================
208
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8 #####ECOSGPLCOPYRIGHTBEGIN####
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9 # -------------------------------------------
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10 # This file is part of eCos, the Embedded Configurable Operating System.
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11 # Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 #
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13 # eCos is free software; you can redistribute it and/or modify it under
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14 # the terms of the GNU General Public License as published by the Free
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15 # Software Foundation; either version 2 or (at your option) any later version.
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16 #
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17 # eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 # WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 # for more details.
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21 #
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22 # You should have received a copy of the GNU General Public License along
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23 # with eCos; if not, write to the Free Software Foundation, Inc.,
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24 # 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 #
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26 # As a special exception, if other files instantiate templates or use macros
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27 # or inline functions from this file, or you compile this file and link it
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28 # with other works to produce a work based on this file, this file does not
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29 # by itself cause the resulting work to be covered by the GNU General Public
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30 # License. However the source code for this file must still be made available
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31 # in accordance with section (3) of the GNU General Public License.
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32 #
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33 # This exception does not invalidate any other reasons why a work based on
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34 # this file might be covered by the GNU General Public License.
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35 #
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36 # Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 # at http://sources.redhat.com/ecos/ecos-license
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38 # -------------------------------------------
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39 #####ECOSGPLCOPYRIGHTEND####
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40 ##=============================================================================
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41 #######DESCRIPTIONBEGIN####
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42 ##
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43 ## Author(s): nickg
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44 ## Contributors:nickg
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45 ## Date: 1997-10-16
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46 ## Purpose: PowerPC definitions.
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47 ## Description: This file contains various definitions and macros that are
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48 ## useful for writing assembly code for the PowerPC
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49 ## It also includes the variant assembly header file.
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50 ## Usage:
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51 ## #include <cyg/hal/arch.inc>
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52 ## ...
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53 ##
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54 ##
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55 ######DESCRIPTIONEND####
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56 ##
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57 ##=============================================================================
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58
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59 #include <cyg/hal/variant.inc>
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60 #include <cyg/hal/ppc_offsets.inc>
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61
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62 #------------------------------------------------------------------------------
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63 # Easier to read names for the registers
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64
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65 .equ r0, 0
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66 .equ r1, 1
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67 .equ r2, 2
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68 .equ r3, 3
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69 .equ r4, 4
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70 .equ r5, 5
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71 .equ r6, 6
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72 .equ r7, 7
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73 .equ r8, 8
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74 .equ r9, 9
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75 .equ r10, 10
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76 .equ r11, 11
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77 .equ r12, 12
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78 .equ r13, 13
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79 .equ r14, 14
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80 .equ r15, 15
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81 .equ r16, 16
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82 .equ r17, 17
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83 .equ r18, 18
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84 .equ r19, 19
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85 .equ r20, 20
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86 .equ r21, 21
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87 .equ r22, 22
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88 .equ r23, 23
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89 .equ r24, 24
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90 .equ r25, 25
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91 .equ r26, 26
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92 .equ r27, 27
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93 .equ r28, 28
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94 .equ r29, 29
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95 .equ r30, 30
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96 .equ r31, 31
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97
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98 .equ sp, r1
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99
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100 #ifdef CYGHWR_HAL_POWERPC_FPU
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101 .equ f0, 0
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102 .equ f1, 1
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103 .equ f2, 2
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104 .equ f3, 3
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105 .equ f4, 4
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106 .equ f5, 5
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107 .equ f6, 6
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108 .equ f7, 7
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109 .equ f8, 8
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110 .equ f9, 9
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111 .equ f10, 10
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112 .equ f11, 11
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113 .equ f12, 12
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114 .equ f13, 13
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115 .equ f14, 14
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116 .equ f15, 15
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117 .equ f16, 16
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118 .equ f17, 17
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119 .equ f18, 18
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120 .equ f19, 19
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121 .equ f20, 20
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122 .equ f21, 21
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123 .equ f22, 22
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124 .equ f23, 23
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125 .equ f24, 24
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126 .equ f25, 25
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127 .equ f26, 26
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128 .equ f27, 27
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129 .equ f28, 28
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130 .equ f29, 29
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131 .equ f30, 30
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132 .equ f31, 31
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133 #endif
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134
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135
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136 #------------------------------------------------------------------------------
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137 # Some useful coding macros
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138
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139 # Load immediate word, has to be done with 2 instructions
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140 .macro lwi reg,val
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141 lis \reg,\val@H
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142 ori \reg,\reg,\val@L
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143 .endm
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144
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145 #ifdef CYGPKG_HAL_POWERPC_PPC603
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146 # Move from HID0 hw control register
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147 .macro mfhid0 reg
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148 mfspr \reg,HID0
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149 .endm
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150 #endif
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151
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152 #define FUNC_START(name) \
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153 .type name,@function; \
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154 .globl name; \
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155 name:
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156
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157 #define FUNC_END(name) \
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158 /* nothing for now */
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159
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160 ##-----------------------------------------------------------------------------
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161 ## PowerPC FPU state handling
208
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162 ## The PowerPC ABI defines f14-f31 as callee saved. There is thus no need to
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163 ## save them when calling C functions
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164
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165 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
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166 # define MAX_SAVE_FREG 13
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167 #else
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168 # define MAX_SAVE_FREG 31
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169 #endif
76
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170
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171 .macro hal_fpu_save regs
208
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172 #ifdef CYGHWR_HAL_POWERPC_FPU
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173 .set _freg, 0
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174 .rept MAX_SAVE_FREG+1
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175 stfd _freg,(CYGARC_PPCREG_FREGS+_freg*8)(\regs)
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176 .set _freg, _freg+1
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177 .endr
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178 #endif
76
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179 .endm
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180
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181 .macro hal_fpu_load regs
208
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182 #ifdef CYGHWR_HAL_POWERPC_FPU
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183 .set _freg, 0
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184 .rept MAX_SAVE_FREG+1
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185 stfd _freg,(CYGARC_PPCREG_FREGS+_freg*8)(\regs)
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186 .set _freg, _freg+1
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187 .endr
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188 #endif
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189 .endm
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190
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191 ##-----------------------------------------------------------------------------
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192 ## CPU specific macros. These provide a common assembler interface to
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193 ## operations that may have CPU specific implementations on different
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194 ## variants of the architecture.
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195
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196 # Enable interrupts
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197 .macro hal_cpu_int_enable
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198 mfmsr r0
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199 ori r3,r3,0x8000
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200 rlwimi r0,r3,0,16,16
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201 sync
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202 mtmsr r0
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203 sync
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204 .endm
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205
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206 # Disable interrupts
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207 .macro hal_cpu_int_disable
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208 mfmsr r0
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209 li r3,0
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210 rlwimi r0,r3,0,16,16
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211 sync
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212 mtmsr r0
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213 sync
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214 .endm
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215
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216 # Merge the interrupt enable state of the status register in
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217 # \sr with the current sr.
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218 .macro hal_cpu_int_merge sr
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219 mfmsr r0
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220 rlwimi r0,\sr,0,16,16
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221 sync
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222 mtmsr r0
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223 sync
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224 .endm
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225
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226 #------------------------------------------------------------------------------
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227 # end of arch.inc