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annotate packages/hal/sh/cq7708/current/include/platform.inc @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents b939e9cada46
children d2c90368aeef
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1 #ifndef CYGONCE_HAL_PLATFORM_INC
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2 #define CYGONCE_HAL_PLATFORM_INC
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3 ##=============================================================================
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4 ##
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5 ## platform.inc
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6 ##
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7 ## SH/CQ7708 board assembler header file
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8 ##
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9 ##=============================================================================
208
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10 #####ECOSGPLCOPYRIGHTBEGIN####
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11 # -------------------------------------------
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12 # This file is part of eCos, the Embedded Configurable Operating System.
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13 # Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 #
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15 # eCos is free software; you can redistribute it and/or modify it under
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16 # the terms of the GNU General Public License as published by the Free
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17 # Software Foundation; either version 2 or (at your option) any later version.
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18 #
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19 # eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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20 # WARRANTY; without even the implied warranty of MERCHANTABILITY or
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21 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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22 # for more details.
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23 #
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24 # You should have received a copy of the GNU General Public License along
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25 # with eCos; if not, write to the Free Software Foundation, Inc.,
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26 # 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 #
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28 # As a special exception, if other files instantiate templates or use macros
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29 # or inline functions from this file, or you compile this file and link it
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30 # with other works to produce a work based on this file, this file does not
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31 # by itself cause the resulting work to be covered by the GNU General Public
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32 # License. However the source code for this file must still be made available
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33 # in accordance with section (3) of the GNU General Public License.
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34 #
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35 # This exception does not invalidate any other reasons why a work based on
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36 # this file might be covered by the GNU General Public License.
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37 #
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38 # Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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39 # at http://sources.redhat.com/ecos/ecos-license
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40 # -------------------------------------------
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41 #####ECOSGPLCOPYRIGHTEND####
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42 ##=============================================================================
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43 #######DESCRIPTIONBEGIN####
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44 ##
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45 ## Author(s): jskov
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46 ## Contributors:jskov
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47 ## Date: 2000-02-02
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48 ## Purpose: SH/CQ7708 board definitions.
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49 ## Description: This file contains various definitions and macros that are
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50 ## useful for writing assembly code for the SH/CQ7708 board.
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51 ## Usage:
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52 ## #include <cyg/hal/platform.inc>
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53 ## ...
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54 ##
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55 ##
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56 ######DESCRIPTIONEND####
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57 ##
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58 ##=============================================================================
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59
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60 #include <pkgconf/hal.h>
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61
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62 #include <cyg/hal/sh_offsets.inc>
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63 #include <cyg/hal/sh_regs.h>
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64
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65 #------------------------------------------------------------------------------
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66 # Hardware initialization.
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67
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68 .macro hal_hardware_init
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69 // Set up the Bus State Controller
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70 mova BSC_settings_table,r0
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71 mov r0,r3
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72 1: mov.w @r3+,r0 // Address (or zero)
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73 cmp/eq #0,r0
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74 bt 2f
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75 mov.w @r3+,r1 // data
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76 bra 1b
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77 mov.w r1,@r0 // delay slot
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78
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79 .align 2
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80
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81 BSC_settings_table:
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82 # These are the settings set by the ROM Monitor.
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83
128
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84 .word CYGARC_REG_FRQCR
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85 .word CYGARC_REG_FRQCR_INIT
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86
94
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87 # BCR1: Areas 3 are SDRAM
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88 .word CYGARC_REG_BCR1
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89 .word 0x0010
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90 # BCR2: Bus size of areas 2,4 are 8 bits
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91 .word CYGARC_REG_BCR2
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92 .word 0x3ddc
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93 # WCR1: 3 wait-state cycles inserted for all areas
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94 .word CYGARC_REG_WCR1
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95 .word 0x3fff
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96 # WCR2: cs0=8wait cs1=0wait cs2=0wait cs3=2wait cs4=4wait */
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97 .word CYGARC_REG_WCR2
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98 .word 0x0246
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99 # MCR: dram setting 10 bit
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100 .word CYGARC_REG_MCR
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101 .word 0x0074
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102 # RTCSR: refresh timer control
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103 .word CYGARC_REG_RTCSR
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104 .word (0xa500 | 0x0010)
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105 # RTCOR: refresh time constant
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106 .word CYGARC_REG_RTCOR
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107 .word (0xa500 | 0x003a)
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108
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109 # Table end
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110 .word 0
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111
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112 .align 2
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113 2:
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114 .endm
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115
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116 #------------------------------------------------------------------------------
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117 # Monitor initialization.
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118
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119 #ifndef CYGPKG_HAL_SH_MON_DEFINED
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120
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121 #if defined(CYG_HAL_STARTUP_ROM) || \
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122 ( defined(CYG_HAL_STARTUP_RAM) && \
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123 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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124
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125 # If we are starting up from ROM, or we are starting in
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126 # RAM and NOT using a ROM monitor, initialize the VSR table.
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127
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128 .macro hal_mon_init
138
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129 mov.l $hal_vsr_table,r3
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130 # Write exception vectors
138
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131 mov.l $cyg_hal_default_exception_vsr,r4
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132 mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
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133 1: mov.l r4,@r3
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134 add #4,r3
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135 dt r5
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136 bf 1b
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137 # Write interrupt vector
138
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138 mov.l $cyg_hal_default_interrupt_vsr,r4
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139 mov.l $hal_vsr_table,r3
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140 add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
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141 mov.l r4,@r3
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142 bra 2f
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143 nop
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144 .align 2
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145
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146 SYM_PTR_REF(cyg_hal_default_exception_vsr)
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147 SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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148 SYM_PTR_REF(hal_vsr_table)
94
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149 2:
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150 .endm
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151
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152 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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153
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154 # Initialize the VSR table entries
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155 # We only take control of the interrupt vector,
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156 # the rest are left to the ROM for now...
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157
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158 .macro hal_mon_init
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159 # Write interrupt vector
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160 mov.l $hal_vsr_table,r3
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161 mov.l $cyg_hal_default_interrupt_vsr,r4
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162 add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
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163 mov.l r4,@r3
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164 bra 2f
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165 nop
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166 .align 2
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167
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168 SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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169 SYM_PTR_REF(hal_vsr_table)
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170 2:
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171 .endm
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172
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173 #else
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174
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175 .macro hal_mon_init
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176 .endm
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177
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178 #endif
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179
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180
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181 #define CYGPKG_HAL_SH_MON_DEFINED
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182
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183 #endif // CYGPKG_HAL_SH_MON_DEFINED
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184
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185 #endif // CYGONCE_HAL_PLATFORM_INC