Mercurial > ecos
annotate packages/hal/mn10300/arch/current/include/hal_cache.h @ 36:e97d78785e2d ecos-sw-1999-09-12
Merge from eCos master repository on 1999-09-12-15:40:34-BST
| author | jlarmour |
|---|---|
| date | Sun, 12 Sep 1999 15:26:05 +0000 |
| parents | 641b639be825 |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 2 | 6 // hal_cache.h |
| 0 | 7 // |
| 2 | 8 // HAL cache control API |
| 0 | 9 // |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 29 // ------------------------------------------- |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 32 //============================================================================= | |
| 33 //#####DESCRIPTIONBEGIN#### | |
| 34 // | |
| 2 | 35 // Author(s): nickg |
| 36 // Contributors: nickg | |
| 37 // Date: 1998-02-17 | |
| 38 // Purpose: Cache control API | |
| 39 // Description: The macros defined here provide the HAL APIs for handling | |
| 0 | 40 // cache control operations. |
| 41 // Usage: | |
| 2 | 42 // #include <cyg/hal/hal_cache.h> |
| 43 // ... | |
| 44 // | |
| 0 | 45 // |
| 46 //####DESCRIPTIONEND#### | |
| 47 // | |
| 48 //============================================================================= | |
| 49 | |
| 2 | 50 #include <pkgconf/hal.h> |
| 0 | 51 #include <cyg/infra/cyg_type.h> |
| 52 | |
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53 #if !defined(CYG_HAL_MN10300_AM31_SIM) |
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54 |
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55 #include <cyg/hal/var_cache.h> |
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56 |
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57 #else |
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58 |
| 0 | 59 //============================================================================= |
| 60 // MN10300 Simulator | |
| 61 | |
| 62 //----------------------------------------------------------------------------- | |
| 63 // Cache dimensions | |
| 64 | |
| 65 // Data cache | |
| 66 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 67 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 68 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 69 | |
| 70 // Instruction cache | |
| 71 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 72 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 73 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 74 | |
| 75 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 76 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 77 | |
| 78 //----------------------------------------------------------------------------- | |
| 79 // Global control of data cache | |
| 80 | |
| 81 // Enable the data cache | |
| 82 #define HAL_DCACHE_ENABLE() | |
| 83 | |
| 84 // Disable the data cache | |
| 85 #define HAL_DCACHE_DISABLE() | |
| 86 | |
| 87 // Invalidate the entire cache | |
| 88 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 89 | |
| 90 // Synchronize the contents of the cache with memory. | |
| 91 #define HAL_DCACHE_SYNC() | |
| 92 | |
| 93 // Set the data cache refill burst size | |
| 94 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 95 | |
| 96 // Set the data cache write mode | |
| 97 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 98 | |
| 99 // Load the contents of the given address range into the data cache | |
| 100 // and then lock the cache so that it stays there. | |
| 101 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 102 | |
| 103 // Undo a previous lock operation | |
| 104 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 105 | |
| 2 | 106 // Unlock entire cache |
| 107 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 108 | |
| 0 | 109 //----------------------------------------------------------------------------- |
| 110 // Data cache line control | |
| 111 | |
| 112 // Allocate cache lines for the given address range without reading its | |
| 113 // contents from memory. | |
| 114 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 115 | |
| 116 // Write dirty cache lines to memory and invalidate the cache entries | |
| 117 // for the given address range. | |
| 118 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 119 | |
| 120 // Invalidate cache lines in the given range without writing to memory. | |
| 121 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 122 | |
| 123 // Write dirty cache lines to memory for the given address range. | |
| 124 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 125 | |
| 126 // Preread the given range into the cache with the intention of reading | |
| 127 // from it later. | |
| 128 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 129 | |
| 130 // Preread the given range into the cache with the intention of writing | |
| 131 // to it later. | |
| 132 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 133 | |
| 134 // Allocate and zero the cache lines associated with the given range. | |
| 135 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 136 | |
| 137 //----------------------------------------------------------------------------- | |
| 138 // Global control of Instruction cache | |
| 139 | |
| 140 // Enable the instruction cache | |
| 141 #define HAL_ICACHE_ENABLE() | |
| 142 | |
| 143 // Disable the instruction cache | |
| 144 #define HAL_ICACHE_DISABLE() | |
| 145 | |
| 146 // Invalidate the entire cache | |
| 147 #define HAL_ICACHE_INVALIDATE_ALL() | |
| 148 | |
| 149 // Synchronize the contents of the cache with memory. | |
| 150 #define HAL_ICACHE_SYNC() | |
| 151 | |
| 152 // Set the instruction cache refill burst size | |
| 153 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 154 | |
| 155 // Load the contents of the given address range into the instruction cache | |
| 156 // and then lock the cache so that it stays there. | |
| 157 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 158 | |
| 159 // Undo a previous lock operation | |
| 160 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 161 | |
| 2 | 162 // Unlock entire cache |
| 163 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 164 | |
| 0 | 165 //----------------------------------------------------------------------------- |
| 166 // Instruction cache line control | |
| 167 | |
| 168 // Invalidate cache lines in the given range without writing to memory. | |
| 169 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 170 | |
| 171 #endif | |
| 172 | |
| 173 | |
| 2 | 174 //----------------------------------------------------------------------------- |
| 175 // Check that a supported configuration has actually defined some macros. | |
| 176 | |
| 177 #ifndef HAL_DCACHE_ENABLE | |
| 178 | |
| 179 #error Unsupported MN10300 configuration | |
| 180 | |
| 181 #endif | |
| 0 | 182 |
| 183 //----------------------------------------------------------------------------- | |
| 184 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 185 // End of hal_cache.h |