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annotate packages/hal/mips/tx39/current/include/var_cache.h @ 3292:7f8e529b4d82 default tip

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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 74dbf4c3f2e1
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #ifndef CYGONCE_IMP_CACHE_H
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2 #define CYGONCE_IMP_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // imp_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
208
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
208
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
208
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors: nickg
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47 // Date: 1998-02-17
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48 // Purpose: Cache control API
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // cache control operations.
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51 // Usage:
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52 // #include <cyg/hal/imp_cache.h>
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53 // ...
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54 //
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //=============================================================================
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59
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60 #include <pkgconf/hal.h>
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61 #include <cyg/infra/cyg_type.h>
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62
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63 #include <cyg/hal/plf_cache.h>
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64
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65 //=============================================================================
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66 // Toshiba TX3904
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67
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68 #ifdef CYGPKG_HAL_MIPS_TX3904
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69
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70 //-----------------------------------------------------------------------------
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71 // Cache dimensions
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72
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73 // Data cache
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74 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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75 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
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76 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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77
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78 // Instruction cache
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79 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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80 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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81 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
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82
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83 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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84 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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85
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86 //-----------------------------------------------------------------------------
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87 // Global control of data cache
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88
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89 // Enable the data cache
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90 // This uses a bit in the config register, which is TX39 specific.
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91 #define HAL_DCACHE_ENABLE_DEFINED
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92 #define HAL_DCACHE_ENABLE() \
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93 { \
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94 asm volatile ("mfc0 $2,$3;" \
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95 "ori $2,$2,0x0010;" \
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96 "mtc0 $2,$3;" \
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97 : \
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98 : \
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99 : "$2" \
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100 ); \
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101 \
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102 }
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103
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104 // Disable the data cache
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105 #define HAL_DCACHE_DISABLE_DEFINED
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106 #define HAL_DCACHE_DISABLE() \
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107 { \
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108 asm volatile ("mfc0 $2,$3;" \
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109 "la $3,0xFFFFFFEF;" \
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110 "and $2,$2,$3;" \
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111 "mtc0 $2,$3;" \
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112 : \
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113 : \
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114 : "$2", "$3" \
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115 ); \
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116 \
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117 }
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118
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119
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120 // Invalidate the entire cache
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121 // The TX39 only has hit-invalidate on the DCACHE, not
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122 // index-invalidate, so we cannot just empty the cache out without
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123 // knowing what is in it. This is annoying. So, the best we can do is
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124 // fill the cache with data that is unlikely to be there
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125 // otherwise. Hence we read bytes from the ROM space since this is
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126 // most likely to be code, and will not get out of sync even if it is not.
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127 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
130
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128 #define HAL_DCACHE_INVALIDATE_ALL() \
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129 { \
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130 volatile CYG_BYTE *addr = (CYG_BYTE *)(0x9fc00000); \
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131 volatile CYG_BYTE tmp = 0; \
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132 int i; \
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133 for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \
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134 { \
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135 tmp = addr[i]; \
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136 } \
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137 }
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138
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139 // Synchronize the contents of the cache with memory.
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140 #define HAL_DCACHE_SYNC_DEFINED
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141 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
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142
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143 // Set the data cache refill burst size
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144 //#define HAL_DCACHE_BURST_SIZE(_size_)
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145
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146 // Set the data cache write mode
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147 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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148
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149 //#define HAL_DCACHE_WRITETHRU_MODE 0
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150 //#define HAL_DCACHE_WRITEBACK_MODE 1
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151
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152 // Load the contents of the given address range into the data cache
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153 // and then lock the cache so that it stays there.
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154 #define HAL_DCACHE_LOCK_DEFINED
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155 #define HAL_DCACHE_LOCK(_base_, _size_) \
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156 { \
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157 asm volatile ("mfc0 $2,$7;" \
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158 "ori $2,$2,0x0100;" \
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159 "mtc0 $2,$7;" \
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160 : \
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161 : \
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162 : "$2" \
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163 ); \
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164 }
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165
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166 // Undo a previous lock operation
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167 #define HAL_DCACHE_UNLOCK_DEFINED
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168 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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169 { \
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170 asm volatile ("mfc0 $2,$7;" \
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171 "la $3,0xFFFFFEFF;" \
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172 "and $2,$2,$3;" \
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173 "mtc0 $2,$7;" \
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174 : \
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175 : \
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176 : "$2", "$3" \
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177 ); \
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178 }
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179
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180 // Unlock entire cache
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181 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
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182 #define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
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183
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184
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185 //-----------------------------------------------------------------------------
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186 // Data cache line control
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187
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188 // Allocate cache lines for the given address range without reading its
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189 // contents from memory.
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190 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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191
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192 // Write dirty cache lines to memory and invalidate the cache entries
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193 // for the given address range.
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194 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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195 #define HAL_DCACHE_FLUSH_DEFINED // Ensure no default definition
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196
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197 // Write dirty cache lines to memory for the given address range.
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198 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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199 #define HAL_DCACHE_STORE_DEFINED // Disable default definition
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200
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201 //-----------------------------------------------------------------------------
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202 // Global control of Instruction cache
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203
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204 // Enable the instruction cache
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205 // This uses a bit in the config register, which is TX39 specific.
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206 #define HAL_ICACHE_ENABLE_DEFINED
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207 #define HAL_ICACHE_ENABLE() \
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208 { \
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209 asm volatile ("mfc0 $2,$3;" \
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210 "ori $2,$2,0x0020;" \
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211 "mtc0 $2,$3;" \
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212 : \
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213 : \
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214 : "$2" \
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215 ); \
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216 \
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217 }
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218
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219 // Disable the instruction cache
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220 #define HAL_ICACHE_DISABLE_DEFINED
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221 #define HAL_ICACHE_DISABLE() \
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222 { \
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223 asm volatile ("mfc0 $2,$3;" \
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224 "la $3,0xFFFFFFDF;" \
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225 "and $2,$2,$3;" \
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226 "mtc0 $2,$3;" \
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227 "j 1f;" \
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228 "nop;" \
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229 ".balign 16,0;" \
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230 "1:;" \
6
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231 : \
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232 : \
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233 : "$2", "$3" \
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234 ); \
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235 \
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236 }
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237
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238 // Load the contents of the given address range into the instruction cache
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239 // and then lock the cache so that it stays there.
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240 #define HAL_ICACHE_LOCK_DEFINED
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241 #define HAL_ICACHE_LOCK(_base_, _size_) \
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242 { \
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243 asm volatile ("mfc0 $2,$7;" \
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244 "ori $2,$2,0x0200;" \
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245 "mtc0 $2,$7;" \
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246 : \
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247 : \
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248 : "$2" \
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249 ); \
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250 }
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251
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252 // Undo a previous lock operation
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253 #define HAL_ICACHE_UNLOCK_DEFINED
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254 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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255 { \
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256 asm volatile ("mfc0 $2,$7;" \
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257 "la $3,0xFFFFFDFF;" \
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258 "and $2,$2,$3;" \
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259 "mtc0 $2,$7;" \
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260 : \
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261 : \
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262 : "$2", "$3" \
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263 ); \
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264 }
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265
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266 // Unlock entire cache
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267 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
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268 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE)
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269
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270 //-----------------------------------------------------------------------------
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271 // Instruction cache line control
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272 // On the TX39, the instruction cache must be disabled to use the index-invalidate
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273 // cache operation.
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274
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275 // Invalidate the entire cache
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276 // This uses the index-invalidate cache operation.
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277 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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278 #define HAL_ICACHE_INVALIDATE_ALL() \
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279 { \
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280 register CYG_ADDRESS _baddr_ = 0x80000000; \
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281 register CYG_ADDRESS _addr_ = 0x80000000; \
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282 register CYG_WORD _state_; \
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283 HAL_ICACHE_IS_ENABLED(_state_); \
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284 HAL_ICACHE_DISABLE(); \
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285 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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286 { \
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287 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
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288 } \
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289 if( _state_ ) HAL_ICACHE_ENABLE(); \
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290 }
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291
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292 // Invalidate cache lines in the given range without writing to memory.
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293 // This uses the index-invalidate cache operation since the TX39 does not
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294 // have hit-invalidate on the instruction cache.
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295 #define HAL_ICACHE_INVALIDATE_DEFINED
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296 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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297 { \
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298 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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299 register CYG_WORD _size_ = (_asize_); \
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300 register CYG_WORD _state_; \
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301 HAL_ICACHE_IS_ENABLED(_state_); \
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302 HAL_ICACHE_DISABLE(); \
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303 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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304 { \
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305 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
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306 } \
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307 if( _state_ ) HAL_ICACHE_ENABLE(); \
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308 }
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309
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310 #endif // CYGPKG_HAL_MIPS_TX3904
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311
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312 //-----------------------------------------------------------------------------
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313 #endif // ifndef CYGONCE_IMP_CACHE_H
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314 // End of imp_cache.h