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annotate packages/kernel/current/tests/kcache1.c @ 3292:7f8e529b4d82 default tip

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Fix FREESCALE_EDMA_NBYTES_MLOFFYES_MLOFF() so it works with negative offsets.
author vae
date Wed, 29 Apr 2015 23:31:48 +0000
parents 283b2c38b413
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*=================================================================
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2 //
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3 // kcache1.c
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4 //
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5 // Cache timing test
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6 //
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7 //==========================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
208
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //==========================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): dsm
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43 // Contributors: dsm, nickg
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44 // Date: 1998-06-18
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45 //####DESCRIPTIONEND####
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46 */
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47
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48 #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL
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49
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50 #include <cyg/kernel/kapi.h>
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51
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52 #include <cyg/infra/testcase.h>
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53
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54 #include <cyg/hal/hal_cache.h>
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55
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56 #if defined(HAL_DCACHE_SIZE) || defined(HAL_UCACHE_SIZE)
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57 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK
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58 #ifdef CYGFUN_KERNEL_API_C
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59
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60 #include <cyg/infra/diag.h>
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61 #include <cyg/hal/hal_intr.h>
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62
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63 // -------------------------------------------------------------------------
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64 // If the HAL does not supply this, we supply our own version
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65
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66 #ifndef HAL_DCACHE_PURGE_ALL
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67 # ifdef HAL_DCACHE_SYNC
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69 #define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_SYNC()
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71 # else
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72
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73 static cyg_uint8 dca[HAL_DCACHE_SIZE + HAL_DCACHE_LINE_SIZE*2];
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74
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75 #define HAL_DCACHE_PURGE_ALL() \
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76 CYG_MACRO_START \
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77 volatile cyg_uint8 *addr = &dca[HAL_DCACHE_LINE_SIZE]; \
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78 volatile cyg_uint8 tmp = 0; \
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79 int i; \
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80 for( i = 0; i < HAL_DCACHE_SIZE; i += HAL_DCACHE_LINE_SIZE ) \
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81 { \
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82 tmp = addr[i]; \
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83 } \
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84 CYG_MACRO_END
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85
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86 # endif
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87 #endif
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88
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89 // -------------------------------------------------------------------------
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90
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91 #define NTHREADS 1
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92 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
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93
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94 static cyg_handle_t thread[NTHREADS];
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95
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96 static cyg_thread thread_obj[NTHREADS];
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97 static char stack[NTHREADS][STACKSIZE];
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98
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99 #ifndef MAX_STRIDE
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100 #define MAX_STRIDE 64
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101 #endif
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102
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103 volatile char m[(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE)*MAX_STRIDE];
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104
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105 // -------------------------------------------------------------------------
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106
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107 static void time0(register cyg_uint32 stride)
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108 {
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109 register cyg_uint32 j,k;
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110 cyg_tick_count_t count0, count1;
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111 cyg_ucount32 t;
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112 register char c CYGBLD_ATTRIB_UNUSED;
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113
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114 count0 = cyg_current_time();
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115
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116 k = 0;
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117 if ( cyg_test_is_simulator )
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118 k = 3960;
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119
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120 for(; k<4000;k++) {
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121 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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122 c=m[stride*j];
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123 }
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124 }
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125
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126 count1 = cyg_current_time();
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127 t = count1 - count0;
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128 diag_printf("stride=%d, time=%d\n", stride, t);
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129 }
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130
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131 // -------------------------------------------------------------------------
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132
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133 void time1(void)
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134 {
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135 cyg_uint32 i;
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136
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137 for(i=1; i<=MAX_STRIDE; i+=i) {
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138 time0(i);
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139 }
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140 }
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141
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142 // -------------------------------------------------------------------------
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143 // With an ICache invalidate in the middle:
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144 #ifdef HAL_ICACHE_INVALIDATE_ALL
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145 static void time0II(register cyg_uint32 stride)
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146 {
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147 register cyg_uint32 j,k;
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148 cyg_tick_count_t count0, count1;
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149 cyg_ucount32 t;
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150 register char c CYGBLD_ATTRIB_UNUSED;
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151
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152 count0 = cyg_current_time();
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153
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154 k = 0;
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155 if ( cyg_test_is_simulator )
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156 k = 3960;
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157
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158 for(; k<4000;k++) {
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159 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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160 HAL_ICACHE_INVALIDATE_ALL();
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161 c=m[stride*j];
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162 }
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163 }
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164
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165 count1 = cyg_current_time();
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166 t = count1 - count0;
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167 diag_printf("stride=%d, time=%d\n", stride, t);
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168 }
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169
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170 // -------------------------------------------------------------------------
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171
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172 void time1II(void)
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173 {
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174 cyg_uint32 i;
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175
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176 for(i=1; i<=MAX_STRIDE; i+=i) {
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177 time0II(i);
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178 }
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179 }
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180 #endif
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181 // -------------------------------------------------------------------------
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182 // With a DCache invalidate in the middle:
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183 // This is guaranteed to produce bogus timing results since interrupts
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184 // have to be disabled to prevent accidental loss of state.
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185 #ifdef HAL_DCACHE_INVALIDATE_ALL
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186 static void time0DI(register cyg_uint32 stride)
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187 {
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188 register cyg_uint32 j,k;
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189 volatile cyg_tick_count_t count0;
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190 cyg_tick_count_t count1;
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191 cyg_ucount32 t;
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192 register char c CYGBLD_ATTRIB_UNUSED;
208
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193 register CYG_INTERRUPT_STATE oldints;
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194
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195 count0 = cyg_current_time();
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196
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197 HAL_DISABLE_INTERRUPTS(oldints);
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198 HAL_DCACHE_SYNC();
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199
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200 k = 0;
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201 if ( cyg_test_is_simulator )
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202 k = 3960;
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203
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204 for(; k<4000;k++) {
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205 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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206 HAL_DCACHE_INVALIDATE_ALL();
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207 c=m[stride*j];
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208 }
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209 }
208
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210 HAL_RESTORE_INTERRUPTS(oldints);
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211
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212 count1 = cyg_current_time();
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213 t = count1 - count0;
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214 diag_printf("stride=%d, time=%d\n", stride, t);
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215 }
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216
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217 // -------------------------------------------------------------------------
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218
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219 void time1DI(void)
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220 {
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221 cyg_uint32 i;
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222
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223 for(i=1; i<=MAX_STRIDE; i+=i) {
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224 time0DI(i);
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225 }
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226 }
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227 #endif
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228 // -------------------------------------------------------------------------
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229 // This test could be improved by counting number of passes possible
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230 // in a given number of ticks.
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231
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232 static void entry0( cyg_addrword_t data )
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233 {
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234 register CYG_INTERRUPT_STATE oldints;
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235
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236 #ifdef HAL_CACHE_UNIFIED
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237
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238 HAL_DISABLE_INTERRUPTS(oldints);
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239 HAL_DCACHE_PURGE_ALL(); // rely on above definition
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240 HAL_UCACHE_INVALIDATE_ALL();
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241 HAL_UCACHE_DISABLE();
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242 HAL_RESTORE_INTERRUPTS(oldints);
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243 CYG_TEST_INFO("Cache off");
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244 time1();
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245
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246 HAL_DISABLE_INTERRUPTS(oldints);
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247 HAL_DCACHE_PURGE_ALL(); // rely on above definition
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248 HAL_UCACHE_INVALIDATE_ALL();
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249 HAL_UCACHE_ENABLE();
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250 HAL_RESTORE_INTERRUPTS(oldints);
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251 CYG_TEST_INFO("Cache on");
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252 time1();
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253
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254 #ifdef HAL_DCACHE_INVALIDATE_ALL
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255 HAL_DISABLE_INTERRUPTS(oldints);
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256 HAL_DCACHE_PURGE_ALL();
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257 HAL_UCACHE_INVALIDATE_ALL();
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258 HAL_UCACHE_ENABLE();
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259 HAL_RESTORE_INTERRUPTS(oldints);
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260 CYG_TEST_INFO("Cache on: invalidate Cache (expect bogus timing)");
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261 time1DI();
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262 #endif
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263
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264 #else // HAL_CACHE_UNIFIED
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265
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266 HAL_DISABLE_INTERRUPTS(oldints);
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267 HAL_DCACHE_PURGE_ALL();
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268 HAL_ICACHE_INVALIDATE_ALL();
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269 HAL_DCACHE_INVALIDATE_ALL();
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270 HAL_ICACHE_DISABLE();
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271 HAL_DCACHE_DISABLE();
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272 HAL_RESTORE_INTERRUPTS(oldints);
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273 CYG_TEST_INFO("Dcache off Icache off");
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274 time1();
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275
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276 HAL_DISABLE_INTERRUPTS(oldints);
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277 HAL_DCACHE_PURGE_ALL();
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278 HAL_ICACHE_INVALIDATE_ALL();
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279 HAL_DCACHE_INVALIDATE_ALL();
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280 HAL_ICACHE_DISABLE();
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281 HAL_DCACHE_ENABLE();
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282 HAL_RESTORE_INTERRUPTS(oldints);
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283 CYG_TEST_INFO("Dcache on Icache off");
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284 time1();
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285
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286 HAL_DISABLE_INTERRUPTS(oldints);
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287 HAL_DCACHE_PURGE_ALL();
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288 HAL_ICACHE_INVALIDATE_ALL();
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289 HAL_DCACHE_INVALIDATE_ALL();
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290 HAL_ICACHE_ENABLE();
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291 HAL_DCACHE_DISABLE();
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292 HAL_RESTORE_INTERRUPTS(oldints);
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293 CYG_TEST_INFO("Dcache off Icache on");
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294 time1();
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295
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296 HAL_DISABLE_INTERRUPTS(oldints);
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297 HAL_DCACHE_PURGE_ALL();
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298 HAL_ICACHE_INVALIDATE_ALL();
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299 HAL_DCACHE_INVALIDATE_ALL();
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300 HAL_ICACHE_ENABLE();
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301 HAL_DCACHE_ENABLE();
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302 HAL_RESTORE_INTERRUPTS(oldints);
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303 CYG_TEST_INFO("Dcache on Icache on");
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304 time1();
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305
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306
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307 HAL_DISABLE_INTERRUPTS(oldints);
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308 HAL_DCACHE_PURGE_ALL();
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309 HAL_ICACHE_INVALIDATE_ALL();
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310 HAL_DCACHE_INVALIDATE_ALL();
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311 HAL_ICACHE_DISABLE();
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312 HAL_DCACHE_DISABLE();
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313 HAL_RESTORE_INTERRUPTS(oldints);
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314 CYG_TEST_INFO("Dcache off Icache off (again)");
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315 time1();
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316
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317 #if defined(HAL_DCACHE_INVALIDATE_ALL) || defined(HAL_ICACHE_INVALIDATE_ALL)
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318 HAL_DISABLE_INTERRUPTS(oldints);
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319 HAL_DCACHE_PURGE_ALL();
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320 HAL_ICACHE_INVALIDATE_ALL();
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321 HAL_DCACHE_INVALIDATE_ALL();
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322 HAL_ICACHE_ENABLE();
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323 HAL_DCACHE_ENABLE();
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324 HAL_RESTORE_INTERRUPTS(oldints);
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325 CYG_TEST_INFO("Dcache on Icache on (again)");
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326 time1();
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327
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328 #if defined(CYGPKG_HAL_MIPS)
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329 // In some architectures, the time taken for the next two tests is
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330 // very long, partly because HAL_XCACHE_INVALIDATE_ALL() is implemented
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331 // with a loop over the cache. Hence these tests take longer than the
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332 // testing infrastructure is prepared to wait. The simplest way to get
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333 // these tests to run quickly is to make them think they are running
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334 // under a simulator.
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335 // If the target actually is a simulator, skip the below - it's very
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336 // slow on the simulator, even with reduced loop counts.
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337 if (cyg_test_is_simulator)
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338 CYG_TEST_PASS_FINISH("End of test");
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339
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340 #if defined(CYGPKG_HAL_MIPS_TX49)
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341 // The TX49 has a large cache, and even with reduced loop count,
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342 // 90+ seconds elapses between each INFO output.
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343 CYG_TEST_PASS_FINISH("End of test");
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344 #endif
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345
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346 cyg_test_is_simulator = 1;
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347 #endif
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348
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349 #ifdef HAL_ICACHE_INVALIDATE_ALL
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350 HAL_DISABLE_INTERRUPTS(oldints);
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351 HAL_DCACHE_PURGE_ALL();
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352 HAL_ICACHE_INVALIDATE_ALL();
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353 HAL_DCACHE_INVALIDATE_ALL();
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354 HAL_ICACHE_ENABLE();
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355 HAL_DCACHE_ENABLE();
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356 HAL_RESTORE_INTERRUPTS(oldints);
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357 CYG_TEST_INFO("Dcache on Icache on: invalidate ICache each time");
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358 time1II();
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359 #endif
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360 #ifdef HAL_DCACHE_INVALIDATE_ALL
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361 HAL_DISABLE_INTERRUPTS(oldints);
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362 HAL_DCACHE_PURGE_ALL();
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363 HAL_ICACHE_INVALIDATE_ALL();
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364 HAL_DCACHE_INVALIDATE_ALL();
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365 HAL_ICACHE_ENABLE();
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366 HAL_DCACHE_ENABLE();
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367 HAL_RESTORE_INTERRUPTS(oldints);
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368 CYG_TEST_INFO("Dcache on Icache on: invalidate DCache (expect bogus times)");
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369 time1DI();
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370 #endif
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371 #endif // either INVALIDATE_ALL macro
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372
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373 #endif // HAL_CACHE_UNIFIED
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374
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375 CYG_TEST_PASS_FINISH("End of test");
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376 }
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377
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378 // -------------------------------------------------------------------------
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379
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380 void kcache2_main( void )
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381 {
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382 CYG_TEST_INIT();
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383
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384 cyg_thread_create(4, entry0 , (cyg_addrword_t)0, "kcache1",
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385 (void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]);
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386 cyg_thread_resume(thread[0]);
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387
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388 cyg_scheduler_start();
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389 }
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390
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391 // -------------------------------------------------------------------------
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392
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393 externC void
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394 cyg_start( void )
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395 {
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396 kcache2_main();
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397 }
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398
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399 // -------------------------------------------------------------------------
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400
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401 #else // def CYGFUN_KERNEL_API_C
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402 #define N_A_MSG "Kernel C API layer disabled"
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403 #endif // def CYGFUN_KERNEL_API_C
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404 #else // def CYGVAR_KERNEL_COUNTERS_CLOCK
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405 #define N_A_MSG "Kernel real-time clock disabled"
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406 #endif // def CYGVAR_KERNEL_COUNTERS_CLOCK
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407 #else // def HAL_DCACHE_SIZE
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408 #define N_A_MSG "No caches defined"
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409 #endif // def HAL_DCACHE_SIZE
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410
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411 #ifdef N_A_MSG
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412 externC void
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413 cyg_start( void )
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414 {
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415 CYG_TEST_INIT();
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416 CYG_TEST_NA( N_A_MSG );
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417 }
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418 #endif // N_A_MSG
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419
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420 // -------------------------------------------------------------------------
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421 /* EOF kcache1.c */