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comparison packages/hal/sh/sh3/current/include/mod_regs_ser.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children 289bf90c6a9b
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133:98d71f4d8243 134:d2f49caf9e38
1 //=============================================================================
2 //
3 // mod_regs_ser.h
4 //
5 // SCI, SCIF, and IRDA (serial) Module register definitions
6 //
7 //=============================================================================
8 //####COPYRIGHTBEGIN####
9 //
10 // -------------------------------------------
11 // The contents of this file are subject to the Red Hat eCos Public License
12 // Version 1.1 (the "License"); you may not use this file except in
13 // compliance with the License. You may obtain a copy of the License at
14 // http://www.redhat.com/
15 //
16 // Software distributed under the License is distributed on an "AS IS"
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
18 // License for the specific language governing rights and limitations under
19 // the License.
20 //
21 // The Original Code is eCos - Embedded Configurable Operating System,
22 // released September 30, 1998.
23 //
24 // The Initial Developer of the Original Code is Red Hat.
25 // Portions created by Red Hat are
26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
27 // All Rights Reserved.
28 // -------------------------------------------
29 //
30 //####COPYRIGHTEND####
31 //=============================================================================
32 //#####DESCRIPTIONBEGIN####
33 //
34 // Author(s): jskov
35 // Contributors:jskov
36 // Date: 2000-10-30
37 // Note: All three serial module definitions kept in the same file
38 // since they share some of the information.
39 //####DESCRIPTIONEND####
40 //
41 //=============================================================================
42
43 //++++++ Module SCI ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
44
45 //--------------------------------------------------------------------------
46 // Serial registers. All 8 bit registers.
47 #define CYGARC_REG_SCSMR 0xfffffe80 // serial mode register
48 #define CYGARC_REG_SCBRR 0xfffffe82 // bit rate register
49 #define CYGARC_REG_SCSCR 0xfffffe84 // serial control register
50 #define CYGARC_REG_SCTDR 0xfffffe86 // transmit data register
51 #define CYGARC_REG_SCSSR 0xfffffe88 // serial status register
52 #define CYGARC_REG_SCRDR 0xfffffe8a // receive data register
53
54 // Serial Mode Register
55 #define CYGARC_REG_SCSMR_CA 0x80 // communication mode
56 #define CYGARC_REG_SCSMR_CHR 0x40 // character length (7 if set)
57 #define CYGARC_REG_SCSMR_PE 0x20 // parity enable
58 #define CYGARC_REG_SCSMR_OE 0x10 // parity mode
59 #define CYGARC_REG_SCSMR_STOP 0x08 // stop bit length
60 #define CYGARC_REG_SCSMR_MP 0x04 // multiprocessor mode
61 #define CYGARC_REG_SCSMR_CKS1 0x02 // clock select 1
62 #define CYGARC_REG_SCSMR_CKS0 0x01 // clock select 0
63 #define CYGARC_REG_SCSMR_CKSx_MASK 0x03 // mask
64
65 // Serial Control Register
66 #define CYGARC_REG_SCSCR_TIE 0x80 // transmit interrupt enable
67 #define CYGARC_REG_SCSCR_RIE 0x40 // receive interrupt enable
68 #define CYGARC_REG_SCSCR_TE 0x20 // transmit enable
69 #define CYGARC_REG_SCSCR_RE 0x10 // receive enable
70 #define CYGARC_REG_SCSCR_MPIE 0x08 // multiprocessor interrupt enable
71 #define CYGARC_REG_SCSCR_TEIE 0x04 // transmit-end interrupt enable
72 #define CYGARC_REG_SCSCR_CKE1 0x02 // clock enable 1
73 #define CYGARC_REG_SCSCR_CKE0 0x01 // clock enable 0
74
75 // Serial Status Register
76 #define CYGARC_REG_SCSSR_TDRE 0x80 // transmit data register empty
77 #define CYGARC_REG_SCSSR_RDRF 0x40 // receive data register full
78 #define CYGARC_REG_SCSSR_ORER 0x20 // overrun error
79 #define CYGARC_REG_SCSSR_FER 0x10 // framing error
80 #define CYGARC_REG_SCSSR_PER 0x08 // parity error
81 #define CYGARC_REG_SCSSR_TEND 0x04 // transmit end
82 #define CYGARC_REG_SCSSR_MPB 0x02 // multiprocessor bit
83 #define CYGARC_REG_SCSSR_MPBT 0x01 // multiprocessor bit transfer
84
85 // When clearing the status register, always write the value:
86 // CYGARC_REG_SCSSR_CLEARMASK & ~bit
87 // to prevent other bits than the one of interest to be cleared.
88 #define CYGARC_REG_SCSSR_CLEARMASK 0xf8
89
90
91 #if (CYGARC_SH_MOD_SCI >= 2)
92 # define CYGARC_REG_SCSPTR 0xfffffe7c // serial port register
93 #endif
94
95
96 // Baud rate values calculation, depending on peripheral clock (Pf)
97 // n is CKS setting (0-3)
98 // N = (Pf/(64*2^(2n-1)*B))-1
99 // With CYGARC_SCBRR_CKSx providing the values 1, 4, 16, 64 we get
100 // N = (Pf/(32*_CKS*B))-1
101 //
102 // The CYGARC_SCBRR_OPTIMAL_CKS macro should compute the minimal CKS
103 // setting for the given baud rate and peripheral clock.
104 //
105 // The error of the CKS+count value can be computed by:
106 // E(%) = ((Pf/((N+1)*B*(64^(n-1)))-1)*100
107 //
108 #define CYGARC_SCBRR_PRESCALE(_b_) \
109 ((((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/1/(_b_))-1)<256) ? 1 : \
110 (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/4/(_b_))-1)<256) ? 4 : \
111 (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/16/(_b_))-1)<256) ? 16 : 64)
112
113 // These two macros provide the static values we need to stuff into the
114 // registers.
115 #define CYGARC_SCBRR_CKSx(_b_) \
116 ((1 == CYGARC_SCBRR_PRESCALE(_b_)) ? 0 : \
117 (4 == CYGARC_SCBRR_PRESCALE(_b_)) ? 1 : \
118 (16 == CYGARC_SCBRR_PRESCALE(_b_)) ? 2 : 3)
119 #define CYGARC_SCBRR_N(_b_) \
120 (((_b_) < 4800) ? 0 : \
121 ((_b_) > 115200) ? 0 : \
122 ((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/CYGARC_SCBRR_PRESCALE(_b_)/(_b_))-1))
123
124
125 //++++++ Module IRDA +++++++++++++++++++++++++++++++++++++++++++++++++++++++
126 #ifdef CYGARC_SH_MOD_IRDA
127
128 //--------------------------------------------------------------------------
129 // IrDA (infrared data association). Can also act as regular serial w FIFO
130
131 #define CYGARC_REG_SCSMR1 0xa4000140
132 #define CYGARC_REG_SCBRR1 0xa4000142
133 #define CYGARC_REG_SCSCR1 0xa4000144
134 #define CYGARC_REG_SCFTDR1 0xa4000146
135 #define CYGARC_REG_SCSSR1 0xa4000148
136 #define CYGARC_REG_SCFRDR1 0xa400014a
137 #define CYGARC_REG_SCFCR1 0xa400014c
138 #define CYGARC_REG_SCFDR1 0xa400014e
139
140 // Serial Mode Register
141 #define CYGARC_REG_SCSMR1_IRMOD 0x80 // IrDA Mode
142 #define CYGARC_REG_SCSMR1_ICK_MASK 0x78 // IR pulse width
143 #define CYGARC_REG_SCSMR1_PSEL 0x04 // IR pulse selector(?)
144 #define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1
145 #define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0
146 #define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask
147
148 // Serial Control Register
149 #define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable
150 #define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable
151 #define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable
152 #define CYGARC_REG_SCSCR1_RE 0x10 // receive enable
153 #define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1
154 #define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0
155
156 // Serial Status Register
157 #define CYGARC_REG_SCSSR1_PER_MASK 0xf000 // number of parity errors
158 #define CYGARC_REG_SCSSR1_PER_shift 12
159 #define CYGARC_REG_SCSSR1_FER_MASK 0x0f00 // number of framing errors
160 #define CYGARC_REG_SCSSR1_FER_shift 8
161 #define CYGARC_REG_SCSSR1_ER 0x0080 // receive error
162 #define CYGARC_REG_SCSSR1_TEND 0x0040 // transmit end
163 #define CYGARC_REG_SCSSR1_TDFE 0x0020 // transmit fifo data empty
164 #define CYGARC_REG_SCSSR1_BRK 0x0010 // break detection
165 #define CYGARC_REG_SCSSR1_FER 0x0008 // framing error
166 #define CYGARC_REG_SCSSR1_PER 0x0004 // parity error
167 #define CYGARC_REG_SCSSR1_RDF 0x0002 // receive fifo data full
168 #define CYGARC_REG_SCSSR1_DR 0x0001 // receive data ready
169
170 // When clearing the status register, always write the value:
171 // CYGARC_REG_SCSSR2_CLEARMASK & ~bit
172 // to prevent other bits than the one of interest to be cleared.
173 #define CYGARC_REG_SCSSR1_CLEARMASK 0xf3
174
175 // Serial FIFO Control Register
176 #define CYGARC_REG_SCFCR1_RTRG_MASK 0xc0 // receive fifo data trigger
177 #define CYGARC_REG_SCFCR1_RTRG_1 0x00 // trigger on 1 char
178 #define CYGARC_REG_SCFCR1_RTRG_4 0x40 // trigger on 4 chars
179 #define CYGARC_REG_SCFCR1_RTRG_8 0x80 // trigger on 8 chars
180 #define CYGARC_REG_SCFCR1_RTRG_14 0xc0 // trigger on 14 chars
181
182 #define CYGARC_REG_SCFCR1_TTRG_MASK 0x30 // transmit fifo data trigger
183 #define CYGARC_REG_SCFCR1_TTRG_8 0x00 // trigger on 8 chars
184 #define CYGARC_REG_SCFCR1_TTRG_4 0x10 // trigger on 4 chars
185 #define CYGARC_REG_SCFCR1_TTRG_2 0x20 // trigger on 2 chars
186 #define CYGARC_REG_SCFCR1_TTRG_1 0x30 // trigger on 1 char
187
188 #define CYGARC_REG_SCFCR1_MCE 0x08 // modem control enable
189 #define CYGARC_REG_SCFCR1_TFRST 0x04 // transmit fifo reset
190 #define CYGARC_REG_SCFCR1_RFRST 0x02 // receive fifo reset
191 #define CYGARC_REG_SCFCR1_LOOP 0x01 // loop back test
192
193
194 // Serial FIFO Data Count Set Register
195 #define CYGARC_REG_SCFDR1_RCOUNT_MASK 0x001f // number of chars in r fifo
196 #define CYGARC_REG_SCFDR1_RCOUNT_shift 0
197 #define CYGARC_REG_SCFDR1_TCOUNT_MASK 0x1f00 // number of chars in t fifo
198 #define CYGARC_REG_SCFDR1_TCOUNT_shift 8
199
200 #endif // CYGARC_SH_MOD_IRDA
201
202 //++++++ Module SCIF +++++++++++++++++++++++++++++++++++++++++++++++++++++++
203 #ifdef CYGARC_SH_MOD_SCIF
204
205 //--------------------------------------------------------------------------
206 // Serial w FIFO registers
207
208 #define CYGARC_REG_SCSMR2 0xa4000150 // Serial mode
209 #define CYGARC_REG_SCBRR2 0xa4000152 // Bit rate
210 #define CYGARC_REG_SCSCR2 0xa4000154 // Serial control
211 #define CYGARC_REG_SCFTDR2 0xa4000156 // Transmit FIFO data
212 #define CYGARC_REG_SCSSR2 0xa4000158 // Serial status
213 #define CYGARC_REG_SCFRDR2 0xa400015a // Receive data FIFO
214 #define CYGARC_REG_SCFCR2 0xa400015c // FIFO control register
215 #define CYGARC_REG_SCFDR2 0xa400015e // FIFO data count set
216
217 // Serial Mode Register
218 #define CYGARC_REG_SCSMR2_CHR 0x40 // character length (7 if set)
219 #define CYGARC_REG_SCSMR2_PE 0x20 // parity enable
220 #define CYGARC_REG_SCSMR2_OE 0x10 // parity mode
221 #define CYGARC_REG_SCSMR2_STOP 0x08 // stop bit length
222 #define CYGARC_REG_SCSMR2_CKS1 0x02 // clock select 1
223 #define CYGARC_REG_SCSMR2_CKS0 0x01 // clock select 0
224 #define CYGARC_REG_SCSMR2_CKSx_MASK 0x03 // mask
225
226 // Serial Control Register
227 #define CYGARC_REG_SCSCR2_TIE 0x80 // transmit interrupt enable
228 #define CYGARC_REG_SCSCR2_RIE 0x40 // receive interrupt enable
229 #define CYGARC_REG_SCSCR2_TE 0x20 // transmit enable
230 #define CYGARC_REG_SCSCR2_RE 0x10 // receive enable
231 #define CYGARC_REG_SCSCR2_CKE1 0x02 // clock enable 1
232 #define CYGARC_REG_SCSCR2_CKE0 0x01 // clock enable 0
233
234 // Serial Status Register
235 #define CYGARC_REG_SCSSR2_PER_MASK 0xf000 // number of parity errors
236 #define CYGARC_REG_SCSSR2_PER_shift 12
237 #define CYGARC_REG_SCSSR2_FER_MASK 0x0f00 // number of framing errors
238 #define CYGARC_REG_SCSSR2_FER_shift 8
239 #define CYGARC_REG_SCSSR2_ER 0x0080 // receive error
240 #define CYGARC_REG_SCSSR2_TEND 0x0040 // transmit end
241 #define CYGARC_REG_SCSSR2_TDFE 0x0020 // transmit fifo data empty
242 #define CYGARC_REG_SCSSR2_BRK 0x0010 // break detection
243 #define CYGARC_REG_SCSSR2_FER 0x0008 // framing error
244 #define CYGARC_REG_SCSSR2_PER 0x0004 // parity error
245 #define CYGARC_REG_SCSSR2_RDF 0x0002 // receive fifo data full
246 #define CYGARC_REG_SCSSR2_DR 0x0001 // receive data ready
247
248 // When clearing the status register, always write the value:
249 // CYGARC_REG_SCSSR2_CLEARMASK & ~bit
250 // to prevent other bits than the one of interest to be cleared.
251 #define CYGARC_REG_SCSSR2_CLEARMASK 0xf3
252
253 // Serial FIFO Control Register
254 #define CYGARC_REG_SCFCR2_RTRG_MASK 0xc0 // receive fifo data trigger
255 #define CYGARC_REG_SCFCR2_RTRG_1 0x00 // trigger on 1 char
256 #define CYGARC_REG_SCFCR2_RTRG_4 0x40 // trigger on 4 chars
257 #define CYGARC_REG_SCFCR2_RTRG_8 0x80 // trigger on 8 chars
258 #define CYGARC_REG_SCFCR2_RTRG_14 0xc0 // trigger on 14 chars
259
260 #define CYGARC_REG_SCFCR2_TTRG_MASK 0x30 // transmit fifo data trigger
261 #define CYGARC_REG_SCFCR2_TTRG_8 0x00 // trigger on 8 chars
262 #define CYGARC_REG_SCFCR2_TTRG_4 0x10 // trigger on 4 chars
263 #define CYGARC_REG_SCFCR2_TTRG_2 0x20 // trigger on 2 chars
264 #define CYGARC_REG_SCFCR2_TTRG_1 0x30 // trigger on 1 char
265
266 #define CYGARC_REG_SCFCR2_MCE 0x08 // modem control enable
267 #define CYGARC_REG_SCFCR2_TFRST 0x04 // transmit fifo reset
268 #define CYGARC_REG_SCFCR2_RFRST 0x02 // receive fifo reset
269 #define CYGARC_REG_SCFCR2_LOOP 0x01 // loop back test
270
271
272 // Serial FIFO Data Count Set Register
273 #define CYGARC_REG_SCFDR2_RCOUNT_MASK 0x001f // number of chars in r fifo
274 #define CYGARC_REG_SCFDR2_RCOUNT_shift 0
275 #define CYGARC_REG_SCFDR2_TCOUNT_MASK 0x1f00 // number of chars in t fifo
276 #define CYGARC_REG_SCFDR2_TCOUNT_shift 8
277
278 #endif // CYGARC_SH_MOD_SCIF