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annotate packages/hal/sh/sh3/current/include/mod_regs_ser.h @ 134:d2f49caf9e38 ecos-sw-2000-11-03

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Merge from eCos master repository on 2000-11-03-09:00:49-GMT
author jlarmour
date Fri, 03 Nov 2000 21:17:40 +0000
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children 289bf90c6a9b
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1 //=============================================================================
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2 //
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3 // mod_regs_ser.h
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4 //
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5 // SCI, SCIF, and IRDA (serial) Module register definitions
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6 //
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7 //=============================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //=============================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors:jskov
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36 // Date: 2000-10-30
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37 // Note: All three serial module definitions kept in the same file
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38 // since they share some of the information.
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39 //####DESCRIPTIONEND####
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40 //
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41 //=============================================================================
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42
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43 //++++++ Module SCI ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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44
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45 //--------------------------------------------------------------------------
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46 // Serial registers. All 8 bit registers.
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47 #define CYGARC_REG_SCSMR 0xfffffe80 // serial mode register
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48 #define CYGARC_REG_SCBRR 0xfffffe82 // bit rate register
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49 #define CYGARC_REG_SCSCR 0xfffffe84 // serial control register
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50 #define CYGARC_REG_SCTDR 0xfffffe86 // transmit data register
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51 #define CYGARC_REG_SCSSR 0xfffffe88 // serial status register
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52 #define CYGARC_REG_SCRDR 0xfffffe8a // receive data register
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53
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54 // Serial Mode Register
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55 #define CYGARC_REG_SCSMR_CA 0x80 // communication mode
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56 #define CYGARC_REG_SCSMR_CHR 0x40 // character length (7 if set)
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57 #define CYGARC_REG_SCSMR_PE 0x20 // parity enable
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58 #define CYGARC_REG_SCSMR_OE 0x10 // parity mode
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59 #define CYGARC_REG_SCSMR_STOP 0x08 // stop bit length
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60 #define CYGARC_REG_SCSMR_MP 0x04 // multiprocessor mode
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61 #define CYGARC_REG_SCSMR_CKS1 0x02 // clock select 1
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62 #define CYGARC_REG_SCSMR_CKS0 0x01 // clock select 0
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63 #define CYGARC_REG_SCSMR_CKSx_MASK 0x03 // mask
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64
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65 // Serial Control Register
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66 #define CYGARC_REG_SCSCR_TIE 0x80 // transmit interrupt enable
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67 #define CYGARC_REG_SCSCR_RIE 0x40 // receive interrupt enable
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68 #define CYGARC_REG_SCSCR_TE 0x20 // transmit enable
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69 #define CYGARC_REG_SCSCR_RE 0x10 // receive enable
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70 #define CYGARC_REG_SCSCR_MPIE 0x08 // multiprocessor interrupt enable
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71 #define CYGARC_REG_SCSCR_TEIE 0x04 // transmit-end interrupt enable
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72 #define CYGARC_REG_SCSCR_CKE1 0x02 // clock enable 1
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73 #define CYGARC_REG_SCSCR_CKE0 0x01 // clock enable 0
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74
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75 // Serial Status Register
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76 #define CYGARC_REG_SCSSR_TDRE 0x80 // transmit data register empty
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77 #define CYGARC_REG_SCSSR_RDRF 0x40 // receive data register full
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78 #define CYGARC_REG_SCSSR_ORER 0x20 // overrun error
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79 #define CYGARC_REG_SCSSR_FER 0x10 // framing error
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80 #define CYGARC_REG_SCSSR_PER 0x08 // parity error
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81 #define CYGARC_REG_SCSSR_TEND 0x04 // transmit end
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82 #define CYGARC_REG_SCSSR_MPB 0x02 // multiprocessor bit
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83 #define CYGARC_REG_SCSSR_MPBT 0x01 // multiprocessor bit transfer
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84
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85 // When clearing the status register, always write the value:
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86 // CYGARC_REG_SCSSR_CLEARMASK & ~bit
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87 // to prevent other bits than the one of interest to be cleared.
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88 #define CYGARC_REG_SCSSR_CLEARMASK 0xf8
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89
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90
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91 #if (CYGARC_SH_MOD_SCI >= 2)
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92 # define CYGARC_REG_SCSPTR 0xfffffe7c // serial port register
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93 #endif
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94
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95
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96 // Baud rate values calculation, depending on peripheral clock (Pf)
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97 // n is CKS setting (0-3)
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98 // N = (Pf/(64*2^(2n-1)*B))-1
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99 // With CYGARC_SCBRR_CKSx providing the values 1, 4, 16, 64 we get
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100 // N = (Pf/(32*_CKS*B))-1
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101 //
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102 // The CYGARC_SCBRR_OPTIMAL_CKS macro should compute the minimal CKS
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103 // setting for the given baud rate and peripheral clock.
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104 //
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105 // The error of the CKS+count value can be computed by:
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106 // E(%) = ((Pf/((N+1)*B*(64^(n-1)))-1)*100
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107 //
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108 #define CYGARC_SCBRR_PRESCALE(_b_) \
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109 ((((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/1/(_b_))-1)<256) ? 1 : \
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110 (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/4/(_b_))-1)<256) ? 4 : \
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111 (((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/16/(_b_))-1)<256) ? 16 : 64)
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112
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113 // These two macros provide the static values we need to stuff into the
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114 // registers.
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115 #define CYGARC_SCBRR_CKSx(_b_) \
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116 ((1 == CYGARC_SCBRR_PRESCALE(_b_)) ? 0 : \
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117 (4 == CYGARC_SCBRR_PRESCALE(_b_)) ? 1 : \
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118 (16 == CYGARC_SCBRR_PRESCALE(_b_)) ? 2 : 3)
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119 #define CYGARC_SCBRR_N(_b_) \
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120 (((_b_) < 4800) ? 0 : \
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121 ((_b_) > 115200) ? 0 : \
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122 ((CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED/32/CYGARC_SCBRR_PRESCALE(_b_)/(_b_))-1))
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123
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124
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125 //++++++ Module IRDA +++++++++++++++++++++++++++++++++++++++++++++++++++++++
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126 #ifdef CYGARC_SH_MOD_IRDA
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127
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128 //--------------------------------------------------------------------------
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129 // IrDA (infrared data association). Can also act as regular serial w FIFO
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130
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131 #define CYGARC_REG_SCSMR1 0xa4000140
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132 #define CYGARC_REG_SCBRR1 0xa4000142
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133 #define CYGARC_REG_SCSCR1 0xa4000144
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134 #define CYGARC_REG_SCFTDR1 0xa4000146
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135 #define CYGARC_REG_SCSSR1 0xa4000148
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136 #define CYGARC_REG_SCFRDR1 0xa400014a
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137 #define CYGARC_REG_SCFCR1 0xa400014c
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138 #define CYGARC_REG_SCFDR1 0xa400014e
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139
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140 // Serial Mode Register
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141 #define CYGARC_REG_SCSMR1_IRMOD 0x80 // IrDA Mode
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142 #define CYGARC_REG_SCSMR1_ICK_MASK 0x78 // IR pulse width
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143 #define CYGARC_REG_SCSMR1_PSEL 0x04 // IR pulse selector(?)
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144 #define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1
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145 #define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0
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146 #define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask
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147
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148 // Serial Control Register
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149 #define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable
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150 #define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable
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151 #define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable
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152 #define CYGARC_REG_SCSCR1_RE 0x10 // receive enable
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153 #define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1
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154 #define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0
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155
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156 // Serial Status Register
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157 #define CYGARC_REG_SCSSR1_PER_MASK 0xf000 // number of parity errors
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158 #define CYGARC_REG_SCSSR1_PER_shift 12
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159 #define CYGARC_REG_SCSSR1_FER_MASK 0x0f00 // number of framing errors
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160 #define CYGARC_REG_SCSSR1_FER_shift 8
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161 #define CYGARC_REG_SCSSR1_ER 0x0080 // receive error
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162 #define CYGARC_REG_SCSSR1_TEND 0x0040 // transmit end
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163 #define CYGARC_REG_SCSSR1_TDFE 0x0020 // transmit fifo data empty
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164 #define CYGARC_REG_SCSSR1_BRK 0x0010 // break detection
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165 #define CYGARC_REG_SCSSR1_FER 0x0008 // framing error
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166 #define CYGARC_REG_SCSSR1_PER 0x0004 // parity error
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167 #define CYGARC_REG_SCSSR1_RDF 0x0002 // receive fifo data full
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168 #define CYGARC_REG_SCSSR1_DR 0x0001 // receive data ready
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169
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170 // When clearing the status register, always write the value:
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171 // CYGARC_REG_SCSSR2_CLEARMASK & ~bit
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172 // to prevent other bits than the one of interest to be cleared.
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173 #define CYGARC_REG_SCSSR1_CLEARMASK 0xf3
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174
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175 // Serial FIFO Control Register
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176 #define CYGARC_REG_SCFCR1_RTRG_MASK 0xc0 // receive fifo data trigger
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177 #define CYGARC_REG_SCFCR1_RTRG_1 0x00 // trigger on 1 char
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178 #define CYGARC_REG_SCFCR1_RTRG_4 0x40 // trigger on 4 chars
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179 #define CYGARC_REG_SCFCR1_RTRG_8 0x80 // trigger on 8 chars
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180 #define CYGARC_REG_SCFCR1_RTRG_14 0xc0 // trigger on 14 chars
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181
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182 #define CYGARC_REG_SCFCR1_TTRG_MASK 0x30 // transmit fifo data trigger
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183 #define CYGARC_REG_SCFCR1_TTRG_8 0x00 // trigger on 8 chars
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184 #define CYGARC_REG_SCFCR1_TTRG_4 0x10 // trigger on 4 chars
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185 #define CYGARC_REG_SCFCR1_TTRG_2 0x20 // trigger on 2 chars
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186 #define CYGARC_REG_SCFCR1_TTRG_1 0x30 // trigger on 1 char
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187
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188 #define CYGARC_REG_SCFCR1_MCE 0x08 // modem control enable
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189 #define CYGARC_REG_SCFCR1_TFRST 0x04 // transmit fifo reset
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190 #define CYGARC_REG_SCFCR1_RFRST 0x02 // receive fifo reset
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191 #define CYGARC_REG_SCFCR1_LOOP 0x01 // loop back test
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192
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193
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194 // Serial FIFO Data Count Set Register
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195 #define CYGARC_REG_SCFDR1_RCOUNT_MASK 0x001f // number of chars in r fifo
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196 #define CYGARC_REG_SCFDR1_RCOUNT_shift 0
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197 #define CYGARC_REG_SCFDR1_TCOUNT_MASK 0x1f00 // number of chars in t fifo
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198 #define CYGARC_REG_SCFDR1_TCOUNT_shift 8
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199
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200 #endif // CYGARC_SH_MOD_IRDA
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201
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202 //++++++ Module SCIF +++++++++++++++++++++++++++++++++++++++++++++++++++++++
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203 #ifdef CYGARC_SH_MOD_SCIF
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204
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205 //--------------------------------------------------------------------------
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206 // Serial w FIFO registers
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207
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208 #define CYGARC_REG_SCSMR2 0xa4000150 // Serial mode
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209 #define CYGARC_REG_SCBRR2 0xa4000152 // Bit rate
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210 #define CYGARC_REG_SCSCR2 0xa4000154 // Serial control
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211 #define CYGARC_REG_SCFTDR2 0xa4000156 // Transmit FIFO data
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212 #define CYGARC_REG_SCSSR2 0xa4000158 // Serial status
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213 #define CYGARC_REG_SCFRDR2 0xa400015a // Receive data FIFO
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214 #define CYGARC_REG_SCFCR2 0xa400015c // FIFO control register
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215 #define CYGARC_REG_SCFDR2 0xa400015e // FIFO data count set
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216
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217 // Serial Mode Register
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218 #define CYGARC_REG_SCSMR2_CHR 0x40 // character length (7 if set)
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219 #define CYGARC_REG_SCSMR2_PE 0x20 // parity enable
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220 #define CYGARC_REG_SCSMR2_OE 0x10 // parity mode
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221 #define CYGARC_REG_SCSMR2_STOP 0x08 // stop bit length
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222 #define CYGARC_REG_SCSMR2_CKS1 0x02 // clock select 1
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223 #define CYGARC_REG_SCSMR2_CKS0 0x01 // clock select 0
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224 #define CYGARC_REG_SCSMR2_CKSx_MASK 0x03 // mask
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225
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226 // Serial Control Register
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227 #define CYGARC_REG_SCSCR2_TIE 0x80 // transmit interrupt enable
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228 #define CYGARC_REG_SCSCR2_RIE 0x40 // receive interrupt enable
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229 #define CYGARC_REG_SCSCR2_TE 0x20 // transmit enable
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230 #define CYGARC_REG_SCSCR2_RE 0x10 // receive enable
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231 #define CYGARC_REG_SCSCR2_CKE1 0x02 // clock enable 1
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232 #define CYGARC_REG_SCSCR2_CKE0 0x01 // clock enable 0
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233
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234 // Serial Status Register
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235 #define CYGARC_REG_SCSSR2_PER_MASK 0xf000 // number of parity errors
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236 #define CYGARC_REG_SCSSR2_PER_shift 12
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237 #define CYGARC_REG_SCSSR2_FER_MASK 0x0f00 // number of framing errors
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238 #define CYGARC_REG_SCSSR2_FER_shift 8
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239 #define CYGARC_REG_SCSSR2_ER 0x0080 // receive error
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240 #define CYGARC_REG_SCSSR2_TEND 0x0040 // transmit end
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241 #define CYGARC_REG_SCSSR2_TDFE 0x0020 // transmit fifo data empty
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242 #define CYGARC_REG_SCSSR2_BRK 0x0010 // break detection
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243 #define CYGARC_REG_SCSSR2_FER 0x0008 // framing error
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244 #define CYGARC_REG_SCSSR2_PER 0x0004 // parity error
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245 #define CYGARC_REG_SCSSR2_RDF 0x0002 // receive fifo data full
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246 #define CYGARC_REG_SCSSR2_DR 0x0001 // receive data ready
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247
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248 // When clearing the status register, always write the value:
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249 // CYGARC_REG_SCSSR2_CLEARMASK & ~bit
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250 // to prevent other bits than the one of interest to be cleared.
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251 #define CYGARC_REG_SCSSR2_CLEARMASK 0xf3
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252
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253 // Serial FIFO Control Register
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254 #define CYGARC_REG_SCFCR2_RTRG_MASK 0xc0 // receive fifo data trigger
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255 #define CYGARC_REG_SCFCR2_RTRG_1 0x00 // trigger on 1 char
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256 #define CYGARC_REG_SCFCR2_RTRG_4 0x40 // trigger on 4 chars
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257 #define CYGARC_REG_SCFCR2_RTRG_8 0x80 // trigger on 8 chars
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258 #define CYGARC_REG_SCFCR2_RTRG_14 0xc0 // trigger on 14 chars
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259
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260 #define CYGARC_REG_SCFCR2_TTRG_MASK 0x30 // transmit fifo data trigger
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261 #define CYGARC_REG_SCFCR2_TTRG_8 0x00 // trigger on 8 chars
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262 #define CYGARC_REG_SCFCR2_TTRG_4 0x10 // trigger on 4 chars
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263 #define CYGARC_REG_SCFCR2_TTRG_2 0x20 // trigger on 2 chars
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264 #define CYGARC_REG_SCFCR2_TTRG_1 0x30 // trigger on 1 char
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265
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266 #define CYGARC_REG_SCFCR2_MCE 0x08 // modem control enable
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267 #define CYGARC_REG_SCFCR2_TFRST 0x04 // transmit fifo reset
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268 #define CYGARC_REG_SCFCR2_RFRST 0x02 // receive fifo reset
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269 #define CYGARC_REG_SCFCR2_LOOP 0x01 // loop back test
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270
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271
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272 // Serial FIFO Data Count Set Register
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273 #define CYGARC_REG_SCFDR2_RCOUNT_MASK 0x001f // number of chars in r fifo
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274 #define CYGARC_REG_SCFDR2_RCOUNT_shift 0
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275 #define CYGARC_REG_SCFDR2_TCOUNT_MASK 0x1f00 // number of chars in t fifo
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276 #define CYGARC_REG_SCFDR2_TCOUNT_shift 8
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277
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278 #endif // CYGARC_SH_MOD_SCIF