Mercurial > ecos
changeset 3170:07b48df106b8
Fixed memory layout for FlexBus memory. Add different pin options
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--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/ChangeLog @@ -1,3 +1,14 @@ +2012-01-06 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl, + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h + * include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h + * include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi + * /src/twr_k60n512_fxm_misc.c + Fixed memory layout for FlexBus memory. Add different pin options + [Bugzilla 1001579] + 2012-01-06 Ilija Kocho <ilijak@siva.com.mk> * cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl:
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/cdl/hal_cortexm_kinetis_twr_k60n512_fxm.cdl @@ -54,10 +54,6 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T hardware requires { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" } - implements CYGINT_IO_SERIAL_FREESCALE_UART4 - implements CYGINT_HAL_FREESCALE_UART4 -# implements CYGINT_IO_SERIAL_FREESCALE_UART3 -# implements CYGINT_HAL_FREESCALE_UART3 implements CYGINT_HAL_CORTEXM_KINETIS_RTC description " @@ -69,6 +65,8 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T compile twr_k60n512_fxm_misc.c + implements CYGINT_HAL_CORTEXM4_CODE + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies (1 == CYGHWR_DEVS_ETH_PHY_KSZ8041) } requires { is_active(CYGPKG_HAL_FREESCALE_EDMA) implies @@ -156,6 +154,34 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T requires { CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP == 20 } } + cdl_option CYGOPT_HAL_KINETIS_UART3_IMPLEMENT { + display "Use UART3" + flavor bool + default_value { CYGHWR_HAL_KINETIS_FB_CS0_SIZE <= 0x00040000 } + active_if { CYGHWR_HAL_KINETIS_FB_CS0_SIZE <= 0x00040000 } + implements CYGINT_IO_SERIAL_FREESCALE_UART3 + implements CYGINT_HAL_FREESCALE_UART3 + description " + FlexBus lines AD19 and AD18 are multiplxed with UART Rx and Tx + so we can't use UART3 if external RAM is larger than 1MiB. + If external RAM is less than 1MiB we use UART3 which + is compatible with single chip configuration." + } + + cdl_option CYGOPT_HAL_KINETIS_UART4_IMPLEMENT { + display "Use UART4" + flavor bool +# calculated !CYGOPT_HAL_KINETIS_UART3_IMPLEMENT + default_value { CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000 } +# active_if { CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000 } + implements CYGINT_IO_SERIAL_FREESCALE_UART4 + implements CYGINT_HAL_FREESCALE_UART4 + description " + FlexBus lines AD19 and AD18 are multiplxed with UART Rx and Tx + so we can't use UART3 if external RAM is larger than 1MiB. + Instead we use UART4" + } + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { display "Number of communication channels on the board" flavor data @@ -288,22 +314,16 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T cdl_option CYGHWR_HAL_KINETIS_FB_CS0_SIZE { display "Size \[Bytes\]" flavor data - legal_values { CYGHWR_RAM0_MICRON_CELLULAR_SIZE 0x00100000 } + legal_values { 0x00040000 0x00400000 CYGHWR_RAM0_MICRON_CELLULAR_SIZE } parent CYGHWR_HAL_KINETIS_FB_CS0 - default_value CYGHWR_RAM0_MICRON_CELLULAR_SIZE + default_value 0x00040000 } cdl_option CYGHWR_HAL_KINETIS_FB_CS0_BASE { display "Memory base address" flavor data parent CYGHWR_HAL_KINETIS_FB_CS0 - calculated { (CYGHWR_HAL_KINETIS_FB_CS0_SIZE == - CYGHWR_RAM0_MICRON_CELLULAR_SIZE) ? - CYGHWR_HAL_KINETIS_FB_CS0_AR : - CYGHWR_HAL_KINETIS_FB_CS0_AR + - CYGHWR_RAM0_MICRON_CELLULAR_SIZE - - CYGHWR_HAL_KINETIS_FB_CS0_SIZE - } + calculated CYGHWR_HAL_KINETIS_FB_CS0_AR } cdl_component CYGHWR_HAL_KINETIS_FB_CS0_MR { @@ -504,6 +524,18 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T # CS0 Implementation End # FlexBus Implementation End + cdl_option CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE { + display "External RAM size" + flavor data + calculated CYGHWR_HAL_KINETIS_FB_CS0_SIZE + } + + cdl_option CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE { + display "External RAM base address" + flavor data + calculated CYGHWR_HAL_KINETIS_FB_CS0_BASE + } + cdl_option CYGHWR_FREESCALE_ENET_MII_MDC_HAL_CLOCK { display "ENET MII MDC clock provided by HAL" flavor data
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h @@ -17,8 +17,8 @@ #define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) #define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) -#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_CS0_AR) -#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_CS0_SIZE) +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) #ifndef __ASSEMBLER__
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi @@ -8,7 +8,7 @@ MEMORY sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE sram_u : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE - ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_CS0_AR, LENGTH = CYGHWR_HAL_KINETIS_FB_CS0_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE } SECTIONS
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.h @@ -5,10 +5,18 @@ #include <stddef.h> #endif -#define CYGMEM_REGION_ram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) -#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_sram (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_flash (0x00000000) +#define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) + #ifndef __ASSEMBLER__ extern char CYG_LABEL_NAME (__heap1) []; #endif
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/include/pkgconf/mlt_kinetis_flash_unisram_extram.ldi @@ -5,7 +5,7 @@ MEMORY { - ram : ORIGIN = 0x68000000, LENGTH = 0x01000000 + ram : ORIGIN = CYGHWR_HAL_KINETIS_FB_EXTRAM_BASE, LENGTH = CYGHWR_HAL_KINETIS_FB_EXTRAM_SIZE sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE }
--- a/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c +++ b/packages/hal/cortexm/kinetis/twr_k60n512_fxm/current/src/twr_k60n512_fxm_misc.c @@ -231,15 +231,18 @@ static const cyg_uint32 const flexbus_pi CYGHWR_KINETIS_FB_PIN_AD14, CYGHWR_KINETIS_FB_PIN_AD15, CYGHWR_KINETIS_FB_PIN_AD16, - CYGHWR_KINETIS_FB_PIN_AD17, + CYGHWR_KINETIS_FB_PIN_AD17 +# if CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000 + , CYGHWR_KINETIS_FB_PIN_AD18, CYGHWR_KINETIS_FB_PIN_AD19, -# if 1 //CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00100000 CYGHWR_KINETIS_FB_PIN_AD20, - CYGHWR_KINETIS_FB_PIN_AD21, + CYGHWR_KINETIS_FB_PIN_AD21 +# if CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00400000 + , CYGHWR_KINETIS_FB_PIN_AD22, CYGHWR_KINETIS_FB_PIN_AD23 -# if 0 //!(CYGHWR_HAL_KINETIS_FB_CS_CR(0) & CYGHWR_HAL_FB_CSCR_BLS_M) +# if 0 //!(CYGHWR_HAL_KINETIS_FB_CS_CR(0) & CYGHWR_HAL_FB_CSCR_BLS_M) , CYGHWR_KINETIS_FB_PIN_AD24, CYGHWR_KINETIS_FB_PIN_AD25, @@ -249,8 +252,9 @@ static const cyg_uint32 const flexbus_pi CYGHWR_KINETIS_FB_PIN_AD29, CYGHWR_KINETIS_FB_PIN_AD30, CYGHWR_KINETIS_FB_PIN_AD31 -# endif -# endif // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00100000 +# endif +# endif // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00400000 +# endif // CYGHWR_HAL_KINETIS_FB_CS0_SIZE > 0x00040000 }; static const cyg_uint32 const flexbus_pins_final_diff[] = {