Mercurial > ecos
changeset 3169:d739dc63d0e7
Add: Clocking support for PLL1 (K70), DDRAM controller Cache, eDMA - 32 chan. [Bugzilla 1001579
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--- a/packages/hal/cortexm/kinetis/var/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/var/current/ChangeLog @@ -1,3 +1,18 @@ +2012-05-04 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_kinetis.cdl: + * src/kinetis_clocking.cdl: + * src/kinetis_clocking.c: + * include/hal_cache.h + * include/var_io_lmem.h: + * include/var_io_ddrmc.h: + * include/var_io_devs.h: + * include/var_io.h: + * src/kinetis_ddram.c: + * src/kinetis_misc.c: + Add: Clocking support for PLL1 (K70), DDRAM controller + Cache, eDMA - 32 chan. [Bugzilla 1001579] + 2012-01-11 Tomas Frydrych <tomas@sleepfive.com> * include/var_io.h: @@ -9,7 +24,7 @@ 2012-01-11 Tomas Frydrych <tomas@sleepf 2012-01-05 Ilija Kocho <ilijak@siva.com.mk> - * cdl/kinetis_irq_scheme.cdl + * cdl/kinetis_irq_scheme.cdl Centralized IRQ priority scheme. * cdl/hal_cortexm_kinetis.cdl: @@ -65,7 +80,7 @@ 2011-10-19 Ilija Kocho <ilijak@siva.co // ####GPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2011, 2012 Free Software Foundation, Inc. +// Copyright (C) 2011 Free Software Foundation, Inc. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by
--- a/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl +++ b/packages/hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl @@ -65,7 +65,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT requires { CYGHWR_HAL_CORTEXM == "M4" } - + requires { CYGHWR_HAL_CORTEXM_FPU implies CYGHWR_HAL_CORTEXM_KINETIS_FPU } define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_kinetis.h>" @@ -99,9 +99,9 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU { display "Floating Point Unit option" - implements CYGINT_HAL_CORTEXM_FPU flavor bool - default_value { 0 } + implements CYGINT_HAL_CORTEXM_FPV4_SP_D16 + default_value { CYGINT_HAL_CORTEXM_FPV4_SP_D16 } description "Select whether the chip has Floating Point Unit." } @@ -121,6 +121,14 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { default_value { 0 } description "Select whether the chip has FlexNVM." } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_REV { + display "Kinetis revision" + flavor data + legal_values 1 2 + default_value 1 + description "Revision" + } } cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS { @@ -144,10 +152,22 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { display "System frequency clock setpoint" flavor data legal_values 32768 to 220000000 - default_value 96000000 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP ? + CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP : 96000000 } description "Desired system clock frequency" } - script kinetis_clocking.cdl + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP { + display "Auxiliary clock frequency setpoint" + flavor data + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + legal_values 32768 to 220000000 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP ? + CYGNUM_HAL_CORTEXM_KINETIS_PLF_AUX_FREQ_SP : 96000000 } + description "Desired auxiliary clock frequency" + } + + script kinetis_clocking.cdl } cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY { @@ -466,6 +486,71 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { calculated { 4096 } } + cdl_interface CYGINT_HAL_CACHE { + display "Platform has cache" + flavor bool + } + + cdl_interface CYGINT_HAL_HAS_NONCACHEABLE { + display "Platform has non-cacheable regions" + flavor bool + } + } + + cdl_component CYGPKG_HAL_KINETIS_CACHE { + display "Cache memory" + flavor bool + + default_value CYGINT_HAL_CACHE + active_if (CYGINT_HAL_CACHE) + + cdl_component CYGHWR_HAL_NON_CACHABLE { + display "Non cacheable memory regions" + flavor data + active_if CYGINT_HAL_HAS_NONCACHEABLE + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + + cdl_option CYGHWR_HAL_ENET_TCD_SECTION { + display "Ethernet buffer descriptor memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".sram\"" } + + description "Ethernet is a bus master so buffers/buffer + descriptos must reside in non-cacheable memory" + } + + cdl_option CYGHWR_HAL_ENET_BUF_SECTION { + display "Ethernet buffer memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + + description "Ethernet is a bus master so buffers/buffer + descriptos must reside in non-cacheable memory" + } + + cdl_option CYGHWR_HAL_EDMA_TCD_SECTION { + display "eDMA transfer control descriptor memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".sram\"" } + + description "eDMA is a bus master so buffers/buffer + descriptos must reside in non-cacheable memory" + } + + cdl_option CYGHWR_HAL_EDMA_BUF_SECTION { + display "eDMA buffer memory section" + flavor data + legal_values { "\".sram\"" "\".noncache\"" } + default_value { "\".noncache\"" } + + description "eDMA is a bus master so buffers/buffer + descriptos must reside in non-cacheable memory" + } + } } cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS { @@ -575,6 +660,107 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS { } } + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_DDRAM { + display "Platform uses SDRAM" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides FlexBus and if FlexBus is + used on target hardware" + } + + cdl_component CYGPKG_HAL_CORTEXM_KINETIS_DDRMC { + display "SDRAM" + flavor bool + active_if CYGINT_HAL_CORTEXM_KINETIS_DDRAM + default_value CYGINT_HAL_CORTEXM_KINETIS_DDRAM + description "SDRAM external RAM." + + requires CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + compile kinetis_ddram.c + + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHE_TYPE { + display "DDR cache type" + flavor data + calculated CYGSEM_HAL_DCACHE_STARTUP_MODE + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_BASE { + display "Cacheable DDRAM base address" + flavor data + default_value 0x70000000 + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE_MIB { + display "DDRAM size \[MiB\]" + flavor data + default_value 128 + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB { + display "Non-cacheable DDRAM size \[MiB\]" + requires { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB <= + CYGHWR_HAL_KINETIS_DDR_SIZE_MIB } + flavor data + + implements CYGINT_HAL_HAS_NONCACHEABLE + + default_value 16 + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_SIZE { + display "DDRAM size \[MiB\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB * (1024 * 1024) * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE_MIB { + display "Cacheable DDRAM size \[MiB\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_SIZE_MIB - + CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB} + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE { + display "Cacheable DDRAM size \[Bytes\]" + flavor data + calculated { (CYGHWR_HAL_KINETIS_DDR_SIZE - + CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) * 0x1 } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE { + display "Non-cacheable DDRAM base address" + flavor data + + calculated { 0x80000000 + CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE } + } + + cdl_option CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE { + display "Non-cacheable DDRAM size \[Bytes\]" + flavor data + calculated { CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE_MIB + * (1024 * 1024) * 0x1 } + } + + cdl_option CYGHWR_HAL_DDR_SYNC_MODE { + display "Synchronous mode" + flavor bool + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" } + default_value { 1 } + } + + cdl_option CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS { + display "DDR bus configuration" + flavor data + legal_values 0 1 2 3 6 + default_value 6 + description " + DDRAM configuration: 0 - LPDDR Half Strength, + 1 - LPDDR Full Strength, 2 - DDR2 Half Strength, + 3 - DDR1, 6 - DDR2 Full Strength" + } + } + for { set ::channel 0 } { $::channel < 6 } { incr ::channel } { cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] {
--- a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl +++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_clocking.cdl @@ -58,8 +58,9 @@ CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC : CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC ? CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC : - CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL ? - CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV : + (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL || + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1) ? + CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV: CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL ? CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV : 0 @@ -83,9 +84,15 @@ cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK { display "System clock source" flavor data - default_value { "PLL" } + default_value { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1 ? "PLL1" : "PLL" } legal_values { - "PLL" "FLL" "EXT_REFCLK" + "PLL" "FLL" "EXT_REFCLK" ( CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 ? "PLL1" : "PLL" ) + } + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" implies + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 1 + } + requires { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" implies + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 1 } description " Select one of 3 options for MCG output clock: @@ -102,61 +109,141 @@ } description "Set External Reference Clock frequency and type." - cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS { - display "Clock type" + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT0 { + display "External freq ref 0" flavor data - default_value { "OSC" } - legal_values { "OSC" "XTAL" "RTC"} + no_define + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS . " " . + CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ + } + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS { + display "Clock type" + flavor data + default_value { "OSC" } + legal_values { "OSC" "XTAL" "RTC"} + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC") implies + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 50000000) + } - requires { - (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC") implies - (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 50000000) + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL") implies + (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 3000000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 32000000)) || + ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 32000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 40000))) + } + + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ == 32768) + } + + description " + Ext reference can be External oscillator or a crystal + for the on-chip oscillator or Real Time Clock." } - requires { - (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL") implies - (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 3000000) && - (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 32000000)) || - ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 32000) && - (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 40000))) + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ { + display "Clock frequency" + flavor data + legal_values 0 to 50000000 + default_value { + is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ) ? + CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ : + 4000000 + } + description "External oscillator or crystal reference in Hz." } - requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") - implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1) - } - requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") - implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP { + display "XTAL parallel C \[pF\]" + flavor data + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } + legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 } + default_value 0 + description " + The oscillator has 4 on-chip capacitors that combined + produce capacitance in parallel to the crystal." } - requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC") - implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ == 32768) - } - - description " - Ext reference can be External oscillator or a crystal - for the on-chip oscillator or Real Time Clock." } - cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ { - display "Clock frequency" + cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1 { + display "External freq ref 1" flavor data - legal_values 0 to 50000000 - default_value { - is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ) ? - CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ : - 4000000 + no_define + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS . " " . + CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ } - description "External oscillator or crystal reference in Hz." - } + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS { + display "Clock type" + flavor data + default_value { "OSC" } + legal_values { "OSC" "XTAL" } + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "OSC") implies + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 50000000) + } + + requires { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL") implies + (((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 3000000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 32000000)) || + ((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ >= 32000) && + (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ <= 40000))) + } - cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP { - display "XTAL parallel C \[pF\]" - flavor data - active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" } - legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 } - default_value 0 - description " - The oscillator has 4 on-chip capacitors that combined - produce capacitance in parallel to the crystal." + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL == 0) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 == 0) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1) + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") + } + requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "RTC") + implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ == 32768) + } + + description " + Ext reference can be External oscillator or a crystal + for the on-chip oscillator or Real Time Clock." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_FREQ { + display "Clock frequency" + flavor data + legal_values 0 to 50000000 + default_value { + is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ) ? + CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC1_FREQ : + 4000000 + } + description "External oscillator or crystal reference in Hz." + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP { + display "XTAL parallel C \[pF\]" + flavor data + active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS == "XTAL" } + legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 } + default_value 0 + description " + The oscillator has 4 on-chip capacitors that combined + produce capacitance in parallel to the crystal." + } } } @@ -173,7 +260,12 @@ display "PLL/FLL output frequency set point" flavor data legal_values 32768 to 220000000 - calculated CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP + calculated { + ((CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL") || + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")) ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP : + CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP + } description "Desired PLL output frequency." } @@ -186,11 +278,23 @@ implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL") } - legal_values { "INT_RC_32KHZ" "EXT_REFCLK" } + legal_values { "INT_RC_32KHZ" "EXT_REFCLK" "EXT_REFCLK1" } description " - PLL/FLL oscillators can use one of 3 clock - references: External Reference Clock or Low (32768 Hz) - or High (2MHz) Frequency Internal oscillator" + PLL/FLL oscillators can use one of external reference + clock references as well as Low (32768 Hz) or High (2MHz) + Frequency Internal oscillator" + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_PLL1_REFSRC { + display "Reference clock source for PLL1" + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + flavor data + default_value { "EXT_REFCLK" } + + legal_values { "EXT_REFCLK" "EXT_REFCLK1" } + description " + PLL1 oscillator can use one of 2 external reference clock + references." } cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ { @@ -209,6 +313,7 @@ no_define active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" || CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" || + CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" || CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" } @@ -262,12 +367,12 @@ cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 { display "DCO max. frequency with 32768 reference" flavor data - legal_values 0 0x80 + legal_values { 0 0x80 } default_value { ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 96000000) || (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 72000000) || (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 48000000) || - (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 24000000)) ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 9600000)) ? 0x80 : 0x00 } } @@ -326,67 +431,172 @@ cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL { display "PLL oscillator" - flavor none - no_define - active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" || - CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" + flavor bool + default_value 1 +# { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ? 0 : 1 } +# active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" || +# CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" +# } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL { + display "100 Mhz line" + flavor none + no_define + active_if !CYGINT_HAL_CORTEXM_KINETIS_150 + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X { + display "Phase detector proposed input frequency" + no_define + flavor data + calculated { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 180000000) ? + 3800000 : + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 110000000) ? + 3000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 3) ? 2000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4) ? 2000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 5) ? 2500000 : + 300000 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV { + display "PLL External Reference Divider" + flavor data + legal_values 1 to 25 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ_X ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ { + display "Phase detector input frequency" + no_define + flavor data + legal_values 2000000 to 4000000 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV { + display "VCO Divider" + flavor data + legal_values 24 to 55 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP / + CYGNUM_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_INFREQ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV { + display "PLL output frequency actual value" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV * + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV) : -1 + } + } } - cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X { - display "Phase detector proposed input frequency" + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL { + display "150 Mhz line" + flavor none no_define - flavor data - calculated { - (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 180000000) ? - 3800000 : - (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 110000000) ? - 3000000 : - !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 3) ? 2000000 : - !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4) ? 2000000 : - !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 5) ? 2500000 : - 300000 + active_if CYGINT_HAL_CORTEXM_KINETIS_150 + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X { + display "Phase detector proposed input frequency" + no_define + flavor data + legal_values 1000000 to 32000000 + default_value { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ == 50000000) ? + (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 30000000) ? 30000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4000000) ? 4000000 : + 5000000 + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL { + display "PLL0 Reference Oscillator select" + flavor data + default_value 0 + legal_values 0 1 + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV { + display "PLL External Reference Divider" + flavor data + legal_values 1 to 8 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ_X ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ { + display "Phase detector input frequency" + no_define + flavor data + legal_values 1000000 to 32000000 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV { + display "VCO Divider" + flavor data + legal_values 16 to 47 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP / + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_INFREQ) * 2) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV { + display "PLL output frequency actual value" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV * + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) / 2) : -1 + } } } cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV { display "PLL External Reference Divider" flavor data - legal_values 1 to 25 - default_value { - CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X ? - (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / - CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X ) : -1 - } - } - - cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ { - display "Phase detector input frequency" - no_define - flavor data - legal_values 2000000 to 4000000 - calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV ? - (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / - CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV) : -1 + calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ? + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_PRDIV : + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_PRDIV } } cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV { - display "VCO Divider" + display "PLL External Reference Divider" flavor data - legal_values 24 to 55 - default_value { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ ? - (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP / - CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ) : -1 + calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ? + (CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL_VDIV) : + CYGOPT_HAL_CORTEXM_KINETIS_100_MCGOUT_PLL_VDIV } } cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV { display "PLL output frequency actual value" flavor data - calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV ? - (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / - CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV * - CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV) : -1 + calculated { CYGINT_HAL_CORTEXM_KINETIS_150 ? + CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL_FREQ_AV : + CYGNUM_HAL_CORTEXM_KINETIS_100_MCG_PLL_FREQ_AV } } } @@ -632,4 +842,140 @@ } } -# EOF kinetis_clocking.cdl + # PLL1 and OSC1 Configuration + # PLL1 + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 { + display "MCG Has PLL1" + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 { + display "MCG Has OSC1" + } + + cdl_interface CYGINT_HAL_CORTEXM_KINETIS_150 { + display "120 - 150 MHz line" + } + + cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 { + display "PLL1 oscillator" + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL + flavor bool + default_value CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + active_if CYGINT_HAL_CORTEXM_KINETIS_HAS_PLL1 + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP { + display "PLL1 output frequency set point" + flavor data + legal_values 32768 to 220000000 + calculated { + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1") ? + CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP : + CYGNUM_HAL_CORTEXM_KINETIS_AUX_FREQ_SP + } + description "Desired PLL1 output frequency." + } + + cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ { + display "Reference frequency." + flavor data + calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ? + CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ : + (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC + == "INT_RC_32KHZ" ? 32768 : 2000000 ) + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X { + display "Phase detector proposed input frequency" + no_define + flavor data + legal_values 1000000 to 32000000 + default_value { + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ == 50000000) ? + (!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 48000000) ? 50000000/8 : 50000000/5) : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 30000000) ? 30000000 : + !(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP % 4000000) ? 4000000 : + 5000000 + } + } + + cdl_option CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL { + display "PLL10 Reference Oscillator select" + flavor data + default_value 0 + legal_values 0 1 + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV { + display "PLL1 External Reference Divider" + flavor data + legal_values 1 to 8 + default_value { + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ / + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ_X ) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ { + display "Phase detector input frequency" + no_define + flavor data + legal_values 1000000 to 32000000 + calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ? + (CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV { + display "VCO Divider" + flavor data + legal_values 16 to 47 + default_value { CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_FREQ_SP / + CYGNUM_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_INFREQ) * 2) : -1 + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV { + display "PLL1 output frequency actual value" + flavor data + calculated { CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV ? + ((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL1_REF_FREQ / + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV * + CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV) / 2) : -1 + } + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV { + display "PLL1 External Reference Divider" + flavor data + calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_PRDIV + } + + cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV { + display "PLL1 External Reference Divider" + flavor data + calculated CYGOPT_HAL_CORTEXM_KINETIS_150_MCGOUT_PLL1_VDIV + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV { + display "PLL1 output frequency actual value" + flavor data + calculated CYGNUM_HAL_CORTEXM_KINETIS_150_MCG_PLL1_FREQ_AV + } + } + + cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLLSEL_FREQ_AV { + display "Frequency of selected PLL" + flavor data + parent CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL + calculated {CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL1" ? + CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL1_FREQ_AV : + CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV + } + } + + # EOF kinetis_clocking.cdl
--- a/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl +++ b/packages/hal/cortexm/kinetis/var/current/cdl/kinetis_flexbus.cdl @@ -50,7 +50,7 @@ # display "FlexBus" for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } { - + cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] { display "Platform uses Chip select [set ::chipsel]" flavor bool @@ -59,7 +59,7 @@ for { set ::chipsel 0 } { $::chipsel < 6 controller being used provides chip select [set ::chipsel], and if that chip select is used on target hardware." } - + cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] { display "Chip select [set ::chipsel]" flavor bool @@ -68,7 +68,7 @@ for { set ::chipsel 0 } { $::chipsel < 6 description " This option includes initialization data for chip select [set ::chipsel]." - + cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS { display "Port size (encoded)" flavor data
--- a/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h +++ b/packages/hal/cortexm/kinetis/var/current/include/hal_cache.h @@ -10,7 +10,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// Copyright (C) 2012 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -41,18 +41,17 @@ //============================================================================= //#####DESCRIPTIONBEGIN#### // -// Author(s): jlarmour -// Contributors: -// Date: 2004-07-23 +// Author(s): jlarmour, ilijak +// Contributors: +// Date: 2012-05-02 // Purpose: Cache control API // Description: The macros defined here provide the HAL APIs for handling // cache control operations. // -// For Kinetis, for the time being these are empty macros. // Usage: // #include <cyg/hal/hal_cache.h> // ... -// +// // //####DESCRIPTIONEND#### // @@ -62,24 +61,76 @@ //----------------------------------------------------------------------------- // Cache dimensions +#ifdef CYGINT_HAL_CACHE // Data cache -//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes -//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line -//#define HAL_DCACHE_WAYS 0 // Associativity of the cache +#define HAL_DCACHE_SIZE (8192*2) // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_DCACHE_WAYS 2*2 // Associativity of the cache // Instruction cache -//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes -//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line -//#define HAL_ICACHE_WAYS 0 // Associativity of the cache +#define HAL_ICACHE_SIZE 8192*2 // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line +#define HAL_ICACHE_WAYS 2*2 // Associativity of the cache -//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) -//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +#include <cyg/hal/var_io_lmem.h> //----------------------------------------------------------------------------- // Global control of data cache // Enable the data cache +#define HAL_DCACHE_ENABLE() \ + HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE(); \ + HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() \ + HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE(); \ + HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() \ + HAL_CORTEXM_KINETIS_CACHE_PS_INVALL(); \ + HAL_CORTEXM_KINETIS_CACHE_PC_INVALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() \ + HAL_CORTEXM_KINETIS_CACHE_PS_SYNC(); \ + HAL_CORTEXM_KINETIS_CACHE_PC_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() \ + HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR(); \ + HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED() && \ + HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED(); \ + CYG_MACRO_END + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ + HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base_, _size_); \ + HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base_, _size_) + +#else // CYGINT_HAL_CACHE + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +// Enable the data cache #define HAL_DCACHE_ENABLE() // Disable the data cache @@ -97,7 +148,7 @@ // Query the state of the data cache (does not affect the caching) #define HAL_DCACHE_IS_ENABLED(_state_) \ CYG_MACRO_START \ - (_state_) = 0; \ + (_state_) = 0; \ CYG_MACRO_END // Set the data cache refill burst size @@ -131,7 +182,7 @@ //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) // Invalidate cache lines in the given range without writing to memory. -//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) // Write dirty cache lines to memory for the given address range. //#define HAL_DCACHE_STORE( _base_ , _size_ ) @@ -147,26 +198,25 @@ // Allocate and zero the cache lines associated with the given range. //#define HAL_DCACHE_ZERO( _base_ , _size_ ) +#endif // CYGINT_HAL_CACHE + //----------------------------------------------------------------------------- // Global control of Instruction cache // Enable the instruction cache -#define HAL_ICACHE_ENABLE() +#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE() // Disable the instruction cache -#define HAL_ICACHE_DISABLE() +#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE() // Invalidate the entire cache -#define HAL_ICACHE_INVALIDATE_ALL() +#define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_INVALIDATE_ALL() // Synchronize the contents of the cache with memory. -#define HAL_ICACHE_SYNC() +#define HAL_ICACHE_SYNC() HAL_DCACHE_SYNC() // Query the state of the instruction cache (does not affect the caching) -#define HAL_ICACHE_IS_ENABLED(_state_) \ - CYG_MACRO_START \ - (_state_) = 0; \ - CYG_MACRO_END +#define HAL_ICACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_) // Set the instruction cache refill burst size //#define HAL_ICACHE_BURST_SIZE(_size_) @@ -185,8 +235,46 @@ // Instruction cache line control // Invalidate cache lines in the given range without writing to memory. -//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) +#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) HAL_DCACHE_INVALIDATE( _base_ , _size_ ) //----------------------------------------------------------------------------- -#endif // ifndef CYGONCE_HAL_CACHE_H +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_UCACHE_ENABLE() HAL_DCACHE_ENABLE() + +// Disable the instruction cache +#define HAL_UCACHE_DISABLE() HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_UCACHE_INVALIDATE_ALL() HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_UCACHE_SYNC() HAL_DCACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_UCACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_) + +// Set the instruction cache refill burst size +//#define HAL_UCACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_UCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_UCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_UCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +#endif // CYGONCE_HAL_CACHE_H + +//----------------------------------------------------------------------------- // End of hal_cache.h
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io.h +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io.h @@ -10,7 +10,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2011, 2012 Free Software Foundation, Inc. +// Copyright (C) 2011 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -109,6 +109,9 @@ typedef struct cyghwr_hal_kinetis_flash_ #define CYGHWR_HAL_KINETIS_OSC_CR (0x40065000) #define CYGHWR_HAL_KINETIS_OSC_CR_P ((volatile cyg_uint8*) 0x40065000) +#define CYGHWR_HAL_KINETIS_OSC1_CR (0x400E5000) +#define CYGHWR_HAL_KINETIS_OSC1_CR_P ((volatile cyg_uint8*) 0x400E5000) + #define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_M 0x01 #define CYGHWR_HAL_KINETIS_OSC_CR_SC16P_S 0 #define CYGHWR_HAL_KINETIS_OSC_CR_SC8P_M 0x02 @@ -134,10 +137,25 @@ typedef volatile struct cyghwr_hal_kinet cyg_uint8 c6; // MCG Control 6 Register cyg_uint8 status; // MCG Status Register cyg_uint8 mcg_res0; +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1 cyg_uint8 atc; // MCG Auto Trim Control Register +#elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 + cyg_uint8 sc; // MCG Status and Control Register +#endif cyg_uint8 mcg_res1; cyg_uint8 atcvh; // MCG Auto Trim Compare Value High Register cyg_uint8 atcvl; // MCG Auto Trim Compare Value Low Register +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 + cyg_uint8 c7; // MCG Control 7 Register + cyg_uint8 c8; // MCG Control 8 Register +#endif +#if CYGINT_HAL_CORTEXM_KINETIS_150 + cyg_uint8 c10; // MCG Control 10 Register + cyg_uint8 mcg_res2; + cyg_uint8 c11; // MCG Control 11 Register + cyg_uint8 c12; // MCG Control 12 Register + cyg_uint8 s2; // MCG Status 2 Register +#endif //CYGINT_HAL_CORTEXM_KINETIS_150 } cyghwr_hal_kinetis_mcg_t; #define CYGHWR_HAL_KINETIS_MCG_P ((cyghwr_hal_kinetis_mcg_t *)0x40064000) @@ -176,6 +194,11 @@ enum { #define CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S 4 #define CYGHWR_HAL_KINETIS_MCG_C2_RANGE(__v) \ VALUE_(CYGHWR_HAL_KINETIS_MCG_C2_RANGE_S, __v) + +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 +#define CYGHWR_HAL_KINETIS_MCG_C2_LOCRE0_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C2_LOCRE0_S 7 +#endif // C3 Bit Fields #define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_M 0xFF #define CYGHWR_HAL_KINETIS_MCG_C3_SCTRIM_S 0 @@ -203,6 +226,10 @@ enum { #define CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_S 5 #define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M 0x40 #define CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_S 6 +#if CYGINT_HAL_CORTEXM_KINETIS_HAS_OSC1 +# define CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_M 0x80 +# define CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_S 7 +#endif // C6 Bit Fields #define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M 0x1F #define CYGHWR_HAL_KINETIS_MCG_C6_VDIV_S 0 @@ -235,6 +262,8 @@ enum { #define CYGHWR_HAL_KINETIS_MCG_S_LOCK_S 6 #define CYGHWR_HAL_KINETIS_MCG_S_LOLS_M 0x80 #define CYGHWR_HAL_KINETIS_MCG_S_LOLS_S 7 + +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1 // ATC Bit Fields #define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_M 0x20 #define CYGHWR_HAL_KINETIS_MCG_ATC_ATMF_S 5 @@ -242,6 +271,23 @@ enum { #define CYGHWR_HAL_KINETIS_MCG_ATC_ATMS_S 6 #define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_M 0x80 #define CYGHWR_HAL_KINETIS_MCG_ATC_ATME_S 7 +#elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 +// SC Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_SC_LOCS0_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_SC_LOCS0_S 0 +#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_M 0x0E +#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_S 1 +#define CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_SC_FCRDIV_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_SC_FLTPRSRV_M 0x10 +#define CYGHWR_HAL_KINETIS_MCG_SC_FLTPRSRV_S 4 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATMF_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATMF_S 5 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATMS_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATMS_S 6 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATME_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_SC_ATME_S 7 +#endif // CYGHWR_HAL_CORTEXM_KINETIS_REV // ATCVH Bit Fields #define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_M 0xFF #define CYGHWR_HAL_KINETIS_MCG_ATCVH_ATCVH_S 0 @@ -251,7 +297,72 @@ enum { #define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_M 0xFF #define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S 0 #define CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL(__v) \ - VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S, __v) +VALUE_(CYGHWR_HAL_KINETIS_MCG_ATCVL_ATCVL_S, __v) + +#if CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 +// C7 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_M 0x1 +#define CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_S 0 +// C8 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C8_LOCS1_M 0x1 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOCS1_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C8_CME1_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C8_CME1_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOLRE_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOLRE_S 6 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOCRE1_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C8_LOCRE1_S 7 +#endif // CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 + +#if CYGINT_HAL_CORTEXM_KINETIS_150 + +// C10 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C10_EREFS1_M 0x04 +#define CYGHWR_HAL_KINETIS_MCG_C10_EREFS1_S 2 +#define CYGHWR_HAL_KINETIS_MCG_C10_HGO1_M 0x08 +#define CYGHWR_HAL_KINETIS_MCG_C10_HGO1_S 3 +#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_M 0x30 +#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_S 4 +#define CYGHWR_HAL_KINETIS_MCG_C10_RANGE1(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C10_RANGE1_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C10_LOCRE0_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C10_LOCRE0_S 7 +// C11 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_M 0x7 +#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M 0x10 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_S 4 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_S 6 +# define CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_M 0x80 +# define CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_S 7 +// C12 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_M 0x1F +#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_S 0 +#define CYGHWR_HAL_KINETIS_MCG_C12_VDIV1(__v) \ + VALUE_(CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_S, __v) +#define CYGHWR_HAL_KINETIS_MCG_C12_CME2_M 0x20 +#define CYGHWR_HAL_KINETIS_MCG_C12_CME2_S 5 +#define CYGHWR_HAL_KINETIS_MCG_C12_LOLIE1_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_C12_LOLIE1_S 7 +// S2 Bit Fields +#define CYGHWR_HAL_KINETIS_MCG_S2_LOCS2_M 0x01 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOCS2_S 0 +#define CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_M 0x02 +#define CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_S 1 +#define CYGHWR_HAL_KINETIS_MCG_S2_PLLCST_M 0x10 +#define CYGHWR_HAL_KINETIS_MCG_S2_PLLCST_S 4 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M 0x40 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_S 6 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOLS1_M 0x80 +#define CYGHWR_HAL_KINETIS_MCG_S2_LOLS1_S 7 + +#endif //CYGINT_HAL_CORTEXM_KINETIS_150 + //--------------------------------------------------------------------------- // Real Time Clock @@ -434,6 +545,10 @@ typedef volatile struct cyghwr_hal_kinet cyg_uint32 uidmh; // Unique Identification Register Mid-High cyg_uint32 uidml; // Unique Identification Register Mid Low cyg_uint32 uidl; // Unique Identification Register Low + + cyg_uint32 clkdiv3; // System Clock Divider Register 3 + cyg_uint32 clkdiv4; // System Clock Divider Register 4 + cyg_uint32 mcr; // Misc control register } cyghwr_hal_kinetis_sim_t; #define CYGHWR_HAL_KINETIS_SIM_P ((cyghwr_hal_kinetis_sim_t *) 0x40047000) @@ -560,15 +675,15 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SDID_REVID(__val) \ VALUE_(CYGHWR_HAL_KINETIS_SIM_SDID_REVID_S, __val) // SCGC1 Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_M 0x20 +#define CYGHWR_HAL_KINETIS_SIM_SCGC1_OSC1_S 5 #define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M 0x400 #define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_S 10 #define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M 0x800 #define CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_S 11 -#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M #define CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M \ (CYGHWR_HAL_KINETIS_SIM_SCGC1_UART4_M | CYGHWR_HAL_KINETIS_SIM_SCGC1_UART5_M) -#endif // SCGC2 Bit Fields #define CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M 0x1 @@ -578,12 +693,10 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M 0x2000 #define CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_S 13 -#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M #define CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M \ (CYGHWR_HAL_KINETIS_SIM_SCGC2_ENET_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC0_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC2_DAC1_M) -#endif // SCGC3 Bit Fields #define CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M 0x1 @@ -592,22 +705,31 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_S 4 #define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M 0x1000 #define CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_S 12 +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC +# define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M 0x4000 +# define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S 14 +#else +# define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M 0 +# define CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_S 0 +#endif #define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M 0x20000 #define CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_S 17 #define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M 0x1000000 #define CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_S 24 #define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M 0x8000000 #define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_S 27 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M 0x10000000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_S 28 -#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M #define CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M \ (CYGHWR_HAL_KINETIS_SIM_SCGC3_RNGB_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC3_FLEXCAN1_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC3_SPI2_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC3_SDHC_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC3_FTM2_M | \ - CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M) -#endif + CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC1_M | \ + CYGHWR_HAL_KINETIS_SIM_SCGC3_ADC3_M ) // SCGC4 Bit Fields #define CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M 0x2 @@ -635,7 +757,6 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M 0x10000000 #define CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_S 28 -#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M #define CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M \ (CYGHWR_HAL_KINETIS_SIM_SCGC4_EWM_M |CYGHWR_HAL_KINETIS_SIM_SCGC4_CMT_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C0_M |CYGHWR_HAL_KINETIS_SIM_SCGC4_I2C1_M | \ @@ -643,7 +764,6 @@ typedef volatile struct cyghwr_hal_kinet CYGHWR_HAL_KINETIS_SIM_SCGC4_UART2_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_UART3_M |\ CYGHWR_HAL_KINETIS_SIM_SCGC4_USBOTG_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_CMP_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC4_VREF_M | CYGHWR_HAL_KINETIS_SIM_SCGC4_LLWU_M) -#endif // SCGC5 Bit Fields #define CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M 0x1 @@ -662,7 +782,8 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTD_S 12 #define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_M 0x2000 #define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTE_S 13 - +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_M 0x4000 +#define CYGHWR_HAL_KINETIS_SIM_SCGC5_PORTF_S 14 #ifndef CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M #define CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M \ (CYGHWR_HAL_KINETIS_SIM_SCGC5_LPTIMER_M | \ @@ -680,6 +801,10 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_S 0 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M 0x2 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX0_S 1 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX1_S 2 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_M 0x10 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_FLEXCAN0_S 4 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_DSPI0_M 0x1000 @@ -705,7 +830,6 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M 0x20000000 #define CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_S 29 -#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M #define CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M \ (CYGHWR_HAL_KINETIS_SIM_SCGC6_FTFL_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC6_DMAMUX_M | \ @@ -721,7 +845,6 @@ typedef volatile struct cyghwr_hal_kinet CYGHWR_HAL_KINETIS_SIM_SCGC6_FTM1_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC6_ADC0_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC6_RTC_M) -#endif // SCGC7 Bit Fields #define CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M 0x1 @@ -731,12 +854,10 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M 0x4 #define CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_S 2 -#ifndef CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M #define CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M \ (CYGHWR_HAL_KINETIS_SIM_SCGC7_FLEXBUS_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC7_DMA_M | \ CYGHWR_HAL_KINETIS_SIM_SCGC7_MPU_M) -#endif // CLKDIV1 Bit Fields #define CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4_M 0xF0000 @@ -816,6 +937,20 @@ typedef volatile struct cyghwr_hal_kinet #define CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S 0 #define CYGHWR_HAL_KINETIS_SIM_UIDL_UID(__val) \ VALUE_(CYGHWR_HAL_KINETIS_SIM_UIDL_UID_S, __val) +// MCR Bit Fields +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_M 0xE000 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_S 5 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG(__val) \ + VALUE_(CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG_S, __val) +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_M 0x8 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_S 3 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_M 0x4 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_S 2 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_M 0x2 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_S 1 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M 0x1 +#define CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_S 0 + //--------------------------------------------------------------------------- // PORT - Peripheral register structure @@ -939,6 +1074,50 @@ CYG_MACRO_START \ CYG_MACRO_END //--------------------------------------------------------------------------- +// PMC Power Management Controller + +typedef volatile struct cyghwr_hal_kinetis_pmc_s { + cyg_uint8 lvdsc1; // Low Voltage Detect Status and Control 1 Register + cyg_uint8 lvdsc2; // Low Voltage Detect Status and Control 2 Register + cyg_uint8 regsc; // Regulator Status and Control Register +} cyghwr_hal_kinetis_pmc_t; + +// PMC base address +#define CYGHWR_HAL_KINETIS_PMC_P ((cyghwr_hal_kinetis_pmc_t *)0x4007D000) + +// LVDSC1 Bit Fields +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M 0x3 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV(__val) \ + (__val & CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDV_M) +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_M 0x10 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDRE_S 4 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_M 0x20 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDIE_S 5 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDACK_M 0x40 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDACK_S 6 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDF_M 0x80 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC1_LVDF_S 7 +// LVDSC2 Bit Fields +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M 0x3 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV(__val) \ + (__val & CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWV_M) +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_M 0x20 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWIE_S 5 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_M 0x40 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWACK_S 6 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWF_M 0x80 +#define CYGHWR_HAL_KINETIS_PMC_LVDSC2_LVWF_S 7 +// REGSC Bit Fields +#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGBE_M 0x1 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGBE_S 0 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_REGONS_M 0x4 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_REGONS_S 2 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_M 0x8 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_ACKISO_S 3 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGEN_M 0x10 +#define CYGHWR_HAL_KINETIS_PMC_REGSC_BGEN_S 4 + +//--------------------------------------------------------------------------- // FMC Flash Memory Controller #define CYGHWR_HAL_KINETIS_FMC_BASE (0x4001F000) @@ -1042,11 +1221,12 @@ typedef volatile struct cyghwr_hal_kinet #ifdef CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS # include <cyg/hal/var_io_flexbus.h> #endif + //---------------------------------------------------------------------------- -// DMA -//#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DMA -//# include <cyg/hal/var_io_dma.h> -//#endif +// DDRMC - SDRAM controller +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC +# include <cyg/hal/var_io_ddrmc.h> +#endif //--------------------------------------------------------------------------- // GPIO
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_ddrmc.h @@ -0,0 +1,111 @@ +#ifndef CYGONCE_HAL_VAR_IO_DDRMC_H +#define CYGONCE_HAL_VAR_IO_DDRMC_H +//=========================================================================== +// +// var_io_ddrmc.h +// +// Kinetis DDRam controller specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2012-03-08 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io_ddrmc.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +//---------------------------------------------------------------------------- +// DDRMC - SDRAM controller + +# define CYGNUM_HAL_KINETIS_DDRMC_CR_N 64 // Number of DDRMC control registers + +typedef volatile struct cyghwr_hal_kinetis_ddrmc_s { + cyg_uint32 cr[CYGNUM_HAL_KINETIS_DDRMC_CR_N]; // Control registers + cyg_uint32 reserved1[32]; + cyg_uint32 rcr; // RCR control register + cyg_uint32 reserved2[10]; + cyg_uint32 pad_ctrl; // I/O Pad control register +} cyghwr_hal_kinetis_ddrmc_t; + +# define CYGHWR_HAL_KINETIS_DDRMC_P ((cyghwr_hal_kinetis_ddrmc_t *)0x400ae000) + +// RCR +# define CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M 0x40000000 +// PAD CTRL +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_M 0x03000000 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_S 20 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT(_x_) \ + VALUE_(CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_CS0_S, _x_) +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_DIS 0 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_50 3 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_75 1 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_ODT_150 2 + +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_M 0x0000000f +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_S 0 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY(_x_) \ + VALUE_(CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_S, _x_) +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_0BUF 0 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_4BUF 1 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_7BUF 2 +# define CYGHWR_HAL_KINETIS_DDRMC_PADCTRL_SPDLY_10BUF 3 + +# define CYGHWR_HAL_KINETIS_DDRMC_CR00_START 0x1 +# define CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL 0x400 + +# define CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M 0x0000ffff + +# ifndef CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP +# define CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRCFG(CYGHWR_HAL_KINETIS_SIM_MCR_DDRBUS)| \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRDQSDIS_M * 0) | \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRPEN_M * 1) | \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRS_M * 0) | \ + (CYGHWR_HAL_KINETIS_SIM_MCR_DDRSREN_M * 0 )) +# endif + +__externC void hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 src[], cyg_uint32 num); +# define HAL_CORTEXM_KINETIS_DDRMC_INIT(__inidat) \ + hal_cortexm_kinetis_ddrmc_init(__inidat, ((sizeof(__inidat)/2)/sizeof(__inidat[0]))) +__externC void hal_cortexm_kinetis_ddrmc_diag(void); + +//----------------------------------------------------------------------------- +// end of var_io_ddrmc.h +#endif // CYGONCE_HAL_VAR_IO_DDRMC_H
--- a/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_devs.h @@ -10,7 +10,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2011, 2012 Free Software Foundation, Inc. +// Copyright (C) 2011 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -56,28 +56,9 @@ // DEVS: // Following macros may be, and usually are borrwed by some device drivers. - -//============================================================================= -// Peripheral clock - -// -//=========================================================================== - - -//============================================================================= -// DEVS: -// Following macros may be, and usually are borrwed by some device drivers. - // Peripheral clock [Hz]; __externC cyg_uint32 hal_get_peripheral_clock(void); -//---------------------------------------------------------------------------- -// SLCD -// Only for the K40 variant -#if CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM == 40 -#define CYGADDR_HAL_FREESCALE_SLCD_BASE (0x400BE000) -#endif - //----------------------------------------------------------------------------- // Freescale UART // Borrow some HAL resources to Freescale UART driver @@ -248,7 +229,8 @@ #define FREESCALE_DMAMUX_SRC_KINETIS_SPI2R 20 #define FREESCALE_DMAMUX_SRC_KINETIS_SPI2T 21 #define FREESCALE_DMAMUX_SRC_KINETIS_I2C0 22 -#define FREESCALE_DMAMUX_SRC_KINETIS_I2C1 23 +#define FREESCALE_DMAMUX_SRC_KINETIS_I2C1 23 // Either I2C1 +#define FREESCALE_DMAMUX_SRC_KINETIS_I2C2 23 // or I2C2 #define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C0 24 #define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C1 25 #define FREESCALE_DMAMUX_SRC_KINETIS_FTM0C2 26 @@ -290,6 +272,72 @@ #define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX8 62 #define FREESCALE_DMAMUX_SRC_KINETIS_DMAMUX9 63 +// DMAMUX1 DMA request sources +#define FREESCALE_DMAMUX1_SRC_KINETIS_DISABLE 0 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE 1 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART0R 2 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART0T 3 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART1R 4 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART1T 5 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART2R 6 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART2T 7 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART3R 8 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART3T 9 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART4R 10 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART4T 11 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART5R 12 +#define FREESCALE_DMAMUX1_SRC_KINETIS_UART5T 13 +#define FREESCALE_DMAMUX1_SRC_KINETIS_I2S0R 14 +#define FREESCALE_DMAMUX1_SRC_KINETIS_I3S0T 15 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI0R 16 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI0T 17 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI1R 18 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI1T 19 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI2R 20 +#define FREESCALE_DMAMUX1_SRC_KINETIS_SPI2T 21 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_22 22 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_23 23 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C0 24 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C1 25 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C2 26 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C3 27 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C4 28 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C5 29 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C6 30 +#define FREESCALE_DMAMUX1_SRC_KINETIS_FTM3C7 31 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_32 32 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_33 33 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_34 34 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_35 35 +#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T0 36 +#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T1 37 +#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T2 38 +#define FREESCALE_DMAMUX1_SRC_KINETIS_1588T3 39 +#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC0 40 +#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC1 41 +#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC2 42 +#define FREESCALE_DMAMUX1_SRC_KINETIS_ADC3 43 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_44 44 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DAC0 45 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DAC1 46 +#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP0 47 +#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP1 48 +#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP2 49 +#define FREESCALE_DMAMUX1_SRC_KINETIS_CMP3 50 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_51 51 +#define FREESCALE_DMAMUX1_SRC_KINETIS_RESERVE_52 52 +#define FREESCALE_DMAMUX1_SRC_KINETIS_PORTF 53 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX0 54 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX1 55 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX2 56 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX3 57 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX4 58 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX5 59 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX6 60 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX7 61 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX8 62 +#define FREESCALE_DMAMUX1_SRC_KINETIS_DMAMUX9 63 + #define FREESCALE_DMAMUX_SRC_SPI0_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI0R #define FREESCALE_DMAMUX_SRC_SPI0_TX FREESCALE_DMAMUX_SRC_KINETIS_SPI0T #define FREESCALE_DMAMUX_SRC_SPI1_RX FREESCALE_DMAMUX_SRC_KINETIS_SPI1R @@ -302,8 +350,14 @@ // Lend some eDMA macros to device driver that use DMA // Base address +#define CYGHWR_HAL_FREESCALE_EDMA0_P ((cyghwr_hal_freescale_edma_t *)0x40008000) +// DMAMUX base addresses +#define CYGHWR_HAL_FREESCALE_DMAMUX0_P ((cyghwr_hal_freescale_dmamux_t *) 0x40021000) +#define CYGHWR_HAL_FREESCALE_DMAMUX1_P ((cyghwr_hal_freescale_dmamux_t *) 0x40022000) + #define CYGHWR_IO_FREESCALE_EDMA0_P CYGHWR_HAL_FREESCALE_EDMA0_P #define CYGHWR_IO_FREESCALE_DMAMUX0_P CYGHWR_HAL_FREESCALE_DMAMUX0_P +#define CYGHWR_IO_FREESCALE_DMAMUX1_P CYGHWR_HAL_FREESCALE_DMAMUX1_P //----------------------------------------------------------------------------- // end of var_io_devs.h
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/include/var_io_lmem.h @@ -0,0 +1,246 @@ +#ifndef CYGONCE_HAL_VAR_IO_LMEM_H +#define CYGONCE_HAL_VAR_IO_LMEM_H +//=========================================================================== +// +// var_io_lmem.h +// +// Kinetis Local memory controller specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Kocho <ilijak@siva.com.mk> +// Date: 2012-04-28 +// Purpose: Kinetis variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io_lmem.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +//---------------------------------------------------------------------------- +// LMEM - Local memory controller + +typedef volatile struct cyghwr_hal_kinetis_lmem_s { + cyg_uint32 ccr; // Cache control register + cyg_uint32 clcr; // Cache line control register + void *csar; // Cache search address register + cyg_uint32 cvr; // Cache read/write value register + cyg_uint8 reserved[16]; + cyg_uint32 rmr; // Cache regions mode register +} cyghwr_hal_kinetis_lmem_t; + +#define CYGHWR_HAL_KINETIS_LMEM_PC_P ((cyghwr_hal_kinetis_lmem_t *) 0xE0082000) +#define CYGHWR_HAL_KINETIS_LMEM_PS_P ((cyghwr_hal_kinetis_lmem_t *) 0xE0082800) + +// CCR Bit Fields +#define CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M 0x1 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M 0x2 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M 0x1000000 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M 0x2000000 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M 0x4000000 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M 0x8000000 +#define CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M 0x80000000 + +//CLCR Bit Fields +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M 0x1 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_M 0xFFC +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S 2 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR(_ca_) \ + (_ca_ << CYGHWR_HAL_KINETIS_LMEM_CLCR_CACHEADDR_S) +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_WSEL_M 0x4000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_TDSEL_M 0x10000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIVB_M 0x100000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCIMB_M 0x200000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCWAY_M 0x400000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S 24 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(_cmd_) \ + (_cmd_ << CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD_S) +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M 0x4000000 +#define CYGHWR_HAL_KINETIS_LMEM_CLCR_LACC_M 0x8000000 + +// CSAR Bit Fields +#define CYGHWR_HAL_KINETIS_LMEM_CSAR_LGO_M 0x1 +#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_M 0xFFFFFFFC +#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S 2 +#define CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR(_adr_) \ + (_adr_ << CYGHWR_HAL_KINETIS_LMEM_CSAR_PHYADDR_S) + +// CCVR Bit Fields +#define CYGHWR_HAL_KINETIS_LMEM_CCVR_DATA_M 0xFFFFFFFF + +// PCCRMR Bit Fields + +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_M 0x3 +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION(_region_,_mask_) \ + (_mask_ << ((15 - _region_) * 2)) + +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M 0 +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M 2 +#define CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M 3 + +#define CYGHWR_HAL_KINETIS_LMEM_R_FLASH_0000 0 +#define CYGHWR_HAL_KINETIS_LMEM_R_DRAM_0800 1 +#define CYGHWR_HAL_KINETIS_LMEM_R_FLEXNVM_1000 2 +#define CYGHWR_HAL_KINETIS_LMEM_R_FLEXBUS_1800 3 +#define CYGHWR_HAL_KINETIS_LMEM_R_SRAM_L 4 +#define CYGHWR_HAL_KINETIS_LMEM_R_SRAM_U 5 +#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_6000 6 +#define CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 7 +#define CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 8 +#define CYGHWR_HAL_KINETIS_LMEM_FLEXBUS_9000 9 + + +#define HAL_CORTEXM_KINETIS_CACHE_PC_ENABLE() \ + hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_ENABLE() \ + hal_cortexm_kinetis_cache_enable(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_DISABLE() \ + hal_cortexm_kinetis_cache_disable(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_DISABLE() \ + hal_cortexm_kinetis_cache_disable(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_INVALL() \ + hal_cortexm_kinetis_cache_inval(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_INVALL() \ + hal_cortexm_kinetis_cache_inval(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_SYNC() \ + hal_cortexm_kinetis_cache_sync(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_SYNC() \ + hal_cortexm_kinetis_cache_sync(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_CLEAR() \ + hal_cortexm_kinetis_cache_clear(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_CLEAR() \ + hal_cortexm_kinetis_cache_clear(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_IS_ENABLED() \ + hal_cortexm_kinetis_cache_is_enabled(CYGHWR_HAL_KINETIS_LMEM_PC_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_IS_ENABLED() \ + hal_cortexm_kinetis_cache_is_enabled(CYGHWR_HAL_KINETIS_LMEM_PS_P) + +#define HAL_CORTEXM_KINETIS_CACHE_PS_INVALIDATE(_base, _size_) \ + hal_cortexm_kinetis_cache_invalidate(CYGHWR_HAL_KINETIS_LMEM_PS_P, _base, _size_) + +#define HAL_CORTEXM_KINETIS_CACHE_PC_INVALIDATE(_base, _size_) \ + hal_cortexm_kinetis_cache_invalidate(CYGHWR_HAL_KINETIS_LMEM_PC_P, _base, _size_) + +__externC void inline +hal_cortexm_kinetis_cache_enable(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr = (CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_ENWRBUF_M + ); +} + +__externC void inline +hal_cortexm_kinetis_cache_disable(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr = (CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M + ); +} + +__externC void inline +hal_cortexm_kinetis_cache_inval(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M + ); +} + +__externC void inline +hal_cortexm_kinetis_cache_sync(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M + ); +} + +__externC void inline +hal_cortexm_kinetis_cache_clear(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_KINETIS_LMEM_CCR_GO_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_INVW1_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_KINETIS_LMEM_CCR_PUSHW1_M + ); +} + +__externC bool inline +hal_cortexm_kinetis_cache_is_enabled(cyghwr_hal_kinetis_lmem_t* lmem_p) +{ + return lmem_p->ccr & CYGHWR_HAL_KINETIS_LMEM_CCR_ENCACHE_M; +} + + +__externC void inline +hal_cortexm_kinetis_cache_invalidate(cyghwr_hal_kinetis_lmem_t* lmem_p, + cyg_uint8* addr_p, cyg_uint32 size) +{ + size = (((cyg_uint32)addr_p & 0xf) + size)/HAL_DCACHE_LINE_SIZE + 1; + while(size--){ + lmem_p->csar = addr_p; + lmem_p->clcr = CYGHWR_HAL_KINETIS_LMEM_CLCR_LADSEL_M | + CYGHWR_HAL_KINETIS_LMEM_CLCR_LCMD(1) | + CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M; + addr_p += HAL_DCACHE_LINE_SIZE; + while(lmem_p->clcr & CYGHWR_HAL_KINETIS_LMEM_CLCR_LGO_M); + } +} + +# define HAL_CORTEXM_KINETIS_DDRMC_INIT(__inidat) \ + hal_cortexm_kinetis_ddrmc_init(__inidat, ((sizeof(__inidat)/2)/sizeof(__inidat[0]))) +__externC void hal_cortexm_kinetis_ddrmc_diag(void); + +//----------------------------------------------------------------------------- +// end of var_io_ddrmc.h +#endif // CYGONCE_HAL_VAR_IO_LMEM_H
--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_clocking.c @@ -101,6 +101,7 @@ hal_start_clocks( void ) // Real Time Clock hal_start_rtc_clock(); # endif + hal_set_clock_dividers(); // Main clock - MCG hal_start_main_clock(); #endif @@ -121,72 +122,160 @@ hal_start_clocks( void ) // Setup MCG // Note: Currently only PBE mode is supported and tested. +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL + +// MCG can have 1 or 2 PLL oscillators. +// PLL0 aka PLL is always present. +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_pll0(cyghwr_hal_kinetis_mcg_t *mcg_p) +{ + mcg_p->c5 = CYGHWR_HAL_KINETIS_MCG_C5_PRDIV( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV-1) | + CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M +# ifdef CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 + | CYGHWR_HAL_KINETIS_MCG_C5_PLLREFSEL0_M +# endif //CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 + ; +# if CYGINT_HAL_CORTEXM_KINETIS_150 + mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-16); +# else + mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-24); +# endif + mcg_p->c5 |= CYGHWR_HAL_KINETIS_MCG_C5_PLLCLKEN_M; + MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M)); +} +#endif //CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL + +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + +// PLL1 Oscillator is present on some devices. +static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_pll1(cyghwr_hal_kinetis_mcg_t *mcg_p) +{ + mcg_p->c11 = CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M; + mcg_p->c11 = CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_PRDIV-1) | + CYGHWR_HAL_KINETIS_MCG_C11_PLLSTEN1_M +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1 + | CYGHWR_HAL_KINETIS_MCG_C11_PLLCS_M +# endif +# ifdef CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_1 + | CYGHWR_HAL_KINETIS_MCG_C11_PLLREFSEL1_M +# endif + ; + mcg_p->c12 = CYGHWR_HAL_KINETIS_MCG_C12_VDIV1( + CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1_VDIV-16); + mcg_p->c11 |= CYGHWR_HAL_KINETIS_MCG_C11_PLLCLKEN1_M; + MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M)); +} +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + +// There are 1 or 2 external oscillators +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_start_ext_ref(void) +{ + volatile cyg_uint8 *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_P; + +# if defined CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_0 || \ + defined CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_0 +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL + // Set the oscillator 0 + *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP / 2; +# elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC + // Select external oscillator + *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M | + CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M; +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL +# endif // CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_0 || ... + +# if defined CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 || \ + defined CYGHWR_HAL_CORTEXM_KINETIS_PLL1REFSEL_1 +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL + // Set the oscillator 1 + osc_cr_p = CYGHWR_HAL_KINETIS_OSC1_CR_P; + *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC1_CAP / 2; +# elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_OSC + // Select external oscillator + *osc_cr_p = CYGHWR_HAL_KINETIS_OSC1_CR_ERCLKEN_M | + CYGHWR_HAL_KINETIS_OSC1_CR_EREFSTEN_M; +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL +# endif // CYGHWR_HAL_CORTEXM_KINETIS_PLLREFSEL_1 || ... +} +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT + + void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR hal_start_main_clock(void) { cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P; #if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL ||\ - defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1 ||\ + (defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC &&\ + CYGHWR_HAL_CORTEXM_KINETIS_REV == 1) cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; #endif + +#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + // Select RTC clock source for MCG reference +# if CYGHWR_HAL_CORTEXM_KINETIS_REV == 1 + sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M; +# elif CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 + mcg_p->c7 |= CYGHWR_HAL_KINETIS_MCG_C7_OSCSEL_M; +# endif // CYGHWR_HAL_CORTEXM_KINETIS_REV == 2 +#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC + #ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT -# if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL || \ - defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC - volatile cyg_uint8 *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_P; + hal_start_ext_ref(); # endif -# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL - // Set the main oscillator - *osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP / 2; -# elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC - // Select exteranal oscillator - *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M | - CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M; -# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL +#if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) -# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC - // Select RTC clock source for MCG reference - sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M; -# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC -#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT - -#if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ - defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || \ - defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) - // Enter FBE mode mcg_p->c2 = CYGHWR_HAL_KINETIS_MCG_C2_RANGE( CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE) -# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL | CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M | CYGHWR_HAL_KINETIS_MCG_C2_HGO_M -# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL ; + mcg_p->c1 = CYGHWR_HAL_KINETIS_MCG_C1_FRDIV( CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG) # if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ - defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) |CYGHWR_HAL_KINETIS_MCG_C1_CLKS(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF) -# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL* ; # ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL // Wait for oscillator start up MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M)); # endif +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT1_IS_XTAL + // Wait for oscillator 1 start up + MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_OSCINIT1_M)); +# endif # ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT // Wait for reference clock to switch to external reference MCG_WAIT_WHILE(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_IREFST_M); // Wait for status flags update MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != # if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ -defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT # else CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL # endif ); # endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT - // Set peripheral dividers before switching to high frequency. - hal_set_clock_dividers(); + # ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL // Configure FLL mcg_p->c4 = (mcg_p->c4 & 0x1f) | @@ -195,33 +284,42 @@ defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_M CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS)); # endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL -# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL - // Configure PLL and enter PBE mode - mcg_p->c5 = CYGHWR_HAL_KINETIS_MCG_C5_PRDIV( - CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV-1) | - CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M; - mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV( - CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-24); +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL + hal_start_pll0(mcg_p); +# endif +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + hal_start_pll1(mcg_p); +# endif +# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1) // Switch to PBE mode mcg_p->c6 |= CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M; MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT); MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_PLLST_M)); +# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M)); +# endif +# if defined CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 + MCG_WAIT_WHILE(!(mcg_p->s2 & CYGHWR_HAL_KINETIS_MCG_S2_LOCK1_M)); +# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL1 // Enter PEE mode mcg_p->c1 &= ~CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M; MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) != CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL); -# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL +# endif // defined CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL* + # if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \ + defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || \ defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M; # endif #endif // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || + // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1) || // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) } @@ -233,9 +331,21 @@ hal_get_cpu_clock(void) #ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P; +# if CYGINT_HAL_CORTEXM_KINETIS_150 + freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) * + ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+16) / 2; +# else freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / ((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) * ((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+24); +# endif +#elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL1 + cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P; + + freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ / + ((mcg_p->c11 & CYGHWR_HAL_KINETIS_MCG_C11_PRDIV1_M)+1) * + ((mcg_p->c12 & CYGHWR_HAL_KINETIS_MCG_C12_VDIV1_M)+16) / 2; #elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV; #elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK) @@ -246,6 +356,9 @@ hal_get_cpu_clock(void) return freq; } + +// Clock dividers provide clock sources for various peripherals. + void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR hal_set_clock_dividers(void) {
new file mode 100644 --- /dev/null +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_ddram.c @@ -0,0 +1,118 @@ +//========================================================================== +// +// kinetis_ddram.c +// +// Cortex-M Kinetis HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija kocho <ilijak@siva.com.mk> +// Date: 2012-03-08 +// Description: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_kinetis.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/cortexm_endian.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + + + +// DDRAM Controller +#ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC +// Initialize DDRAM controller. +// inidat[] is an array of ordered pairs: (register-index, register-value). +void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR +hal_cortexm_kinetis_ddrmc_init(const cyg_uint32 inidat[], cyg_uint32 num) +{ + cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P; + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + volatile cyg_uint32* cr_p; + cyg_uint32 cr_i; + cyg_uint32 regval; + + sim_p->scgc3 |= CYGHWR_HAL_KINETIS_SIM_SCGC3_DDR_M; + + regval = sim_p->mcr & ~CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP_M; + sim_p->mcr = regval | CYGHWR_HAL_KINETIS_SIM_MCR_DDR_SETUP; + + ddrmc_p->rcr |= CYGHWR_HAL_KINETIS_DDRMC_RCR_RST_M; + ddrmc_p->pad_ctrl = 0x01030203; + cr_p = ddrmc_p->cr; + do { + cr_i = *inidat++; + cr_p[cr_i] = *inidat++; + } while(--num); + __asm__ volatile ("nop\n"); + ddrmc_p->cr[0] |= CYGHWR_HAL_KINETIS_DDRMC_CR00_START; + while(!(ddrmc_p->cr[30] & CYGHWR_HAL_KINETIS_DDRMC_CR30_DRAM_INIT_CPL)); +} + +void +hal_cortexm_kinetis_ddrmc_diag(void) +{ + cyghwr_hal_kinetis_ddrmc_t* ddrmc_p = CYGHWR_HAL_KINETIS_DDRMC_P; + cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P; + volatile cyg_uint32* cr_p; + cyg_uint32 cr_i; + + diag_printf("SCGC3 = 0x%08x, MCR = 0x%08x\n", sim_p->scgc3, sim_p->mcr); + diag_printf("RCR= 0x%08x, PAD_CTRL= 0x%08x\n", ddrmc_p->rcr, ddrmc_p->pad_ctrl); + cr_p = ddrmc_p->cr; + for(cr_i=0; cr_i < 64; cr_i++){ + diag_printf(" CR%02d = 0x%08x\n", cr_i, cr_p[cr_i]); + } +} + +#endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + +//========================================================================== +// EOF kinetis_ddram.c
--- a/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c +++ b/packages/hal/cortexm/kinetis/var/current/src/kinetis_misc.c @@ -66,8 +66,19 @@ #include <cyg/hal/hal_intr.h> // HAL header #include <cyg/hal/hal_if.h> // HAL header +#include <cyg/hal/hal_cache.h> + void sst25xx_freescale_dspi_reg(void); +#ifdef CYGPKG_HAL_KINETIS_CACHE +# if defined CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP || \ + defined CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP + +# define ENABLE_CACHE_ON_STARTUP + +# endif +#endif // defined CYGPKG_HAL_KINETIS_CACHE + #ifdef CYG_HAL_STARTUP_ROM //=========================================================================== @@ -100,7 +111,46 @@ hal_kinetis_flash_conf_p( void ) //=== KINETIS FLASH security configuration END. ============================ -//volatile cyg_uint32 *poin; +#if defined CYG_HAL_STARTUP_ROM && defined CYGPKG_HAL_KINETIS_CACHE + +// Function for demotion of caching memory regions + +static void +hal_cortexm_kinetis_conf_cache_regions(cyghwr_hal_kinetis_lmem_t* lmem_p, + cyg_uint32 reg_n, const cyg_uint32 *reg_mode_p) +{ + cyg_uint32 region; + cyg_uint32 mode; + cyg_uint32 regval; + cyg_uint32 reg_mode; + + regval = lmem_p->rmr; + for(; reg_n; reg_n--){ + reg_mode = *reg_mode_p++; + region = reg_mode >> 16; + mode = reg_mode & 0x0000ffff; + regval &= ~(0x3 << (15-region)*2); + regval |= mode << (15-region)*2; + } + lmem_p->rmr = regval; +} + +const cyg_uint32 cache_reg_modes[] = { + (CYGHWR_HAL_KINETIS_LMEM_DRAM_7000 << 16) | +#if defined CYGSEM_HAL_DCACHE_STARTUP_MODE_WRITETHRU + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WT_M, +#elif defined CYGSEM_HAL_DCACHE_STARTUP_MODE_COPYBACK + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_WB_M, +#else + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M, +#endif + + (CYGHWR_HAL_KINETIS_LMEM_DRAM_8000 << 16) | + CYGHWR_HAL_KINETIS_LMEM_CRMR_REGION_NC_M +}; + +#endif // defined CYG_HAL_STARTUP_ROM && defined CYGPKG_HAL_KINETIS_CACHE + //========================================================================== // Setup variant specific hardware //========================================================================= @@ -108,12 +158,23 @@ hal_kinetis_flash_conf_p( void ) void hal_variant_init( void ) { hal_update_clock_var(); +#if defined CYG_HAL_STARTUP_ROM && defined CYGPKG_HAL_KINETIS_CACHE + hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PS_P, + sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]), + cache_reg_modes); + hal_cortexm_kinetis_conf_cache_regions(CYGHWR_HAL_KINETIS_LMEM_PC_P, + sizeof(cache_reg_modes)/sizeof(cache_reg_modes[0]), + cache_reg_modes); +# ifdef ENABLE_CACHE_ON_STARTUP + HAL_DCACHE_ENABLE(); + HAL_ICACHE_ENABLE(); +# endif +#endif // defined CYG_HAL_STARTUP_ROM && defined CYGPKG_HAL_KINETIS_CACHE #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT hal_if_init(); #endif } - //=========================================================================== // The WDOG at Freescale Kinetis is enabled after reset. hal_wdog_disable // provides functionality for disabling it at startup. @@ -191,6 +252,5 @@ hal_dump_pin_setting(cyg_uint32 pin) } } - //========================================================================== // EOF kinetis_misc.c