Mercurial > ecos
changeset 3168:2a048cafed94
Add support for 32 channel eDMA [Bugzilla 1001579]
| author | vae |
|---|---|
| date | Wed, 09 May 2012 22:12:01 +0000 |
| parents | 139bc58bc0bd |
| children | d739dc63d0e7 |
| files | packages/hal/misc/freescale/edma/current/ChangeLog packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl packages/hal/misc/freescale/edma/current/include/freescale_edma.h packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c |
| diffstat | 4 files changed, 194 insertions(+), 35 deletions(-) [+] |
line wrap: on
line diff
--- a/packages/hal/misc/freescale/edma/current/ChangeLog +++ b/packages/hal/misc/freescale/edma/current/ChangeLog @@ -1,3 +1,10 @@ +2012-05-04 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_freescale_edma.cdl + * include/freescale_edma.h + * src/hal/freescale_edma.c + Add support for 32 channel eDMA [Bugzilla 1001579] + 2012-01-06 Ilija Kocho <ilijak@siva.com.mk> * cdl/hal_freescale_edma.cdl @@ -5,7 +12,6 @@ 2012-01-06 Ilija Kocho <ilijak@siva.co * src/hal/freescale_edma.c New package -- Freescale eDMA DMA controller support [Bugzilla 1001450] - //=========================================================================== // ####GPLCOPYRIGHTBEGIN#### // -------------------------------------------
--- a/packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl +++ b/packages/hal/misc/freescale/edma/current/cdl/hal_freescale_edma.cdl @@ -55,6 +55,8 @@ cdl_package CYGPKG_HAL_FREESCALE_EDMA { active_if CYGINT_HAL_DMA + requires { CYGSEM_HAL_DCACHE_STARTUP_MODE == "WRITETHRU" } + cdl_option CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM { display "Number of DMA channels" flavor data @@ -80,6 +82,67 @@ cdl_package CYGPKG_HAL_FREESCALE_EDMA { active_if CYGOPT_HAL_FREESCALE_EDMA_EMLM default_value 0 } + + cdl_option CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE { + display "Number of channels in DMA group" + flavor data + calculated 16 + } + + cdl_component CYGHWR_HAL_FREESCALE_EDMA_GROPS { + display "Groups" + flavor none + no_define + active_if { CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > + CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE } + + cdl_option CYGNUM_HAL_FREESCALE_EDMA_GROUP_NUM { + display "Number of DMA groups" + flavor data + calculated { CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE ? + CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM / + CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE : 0} + } + + cdl_option CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO { + display "Group 0 priority" + flavor data + legal_values 0 1 + default_value 0 + } + + cdl_option CYGNUM_HAL_FREESCALE_EDMA_GR1_PRIO { + display "Group 1 priority" + flavor data + legal_values 0 1 + calculated { CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO ? 0 : 1 } + } + + cdl_option CYGOPT_HAL_FREESCALE_EDMA_ERGA { + display "Round robin group arbitration" + active_if { CYGNUM_HAL_FREESCALE_EDMA_GROUP_NUM > 1 } + flavor bool + default_value 0 + } + } + + cdl_option CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM { + display "Channels per DMAMUX" + flavor data + calculated 16 + } + + cdl_component CYGNUM_HAL_FREESCALE_DMAMUX_NUM { + display "Number of DMAMUX units" + flavor data + active_if { CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > + CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM + } + calculated { CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ? + ( CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM / + CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ) : 0 + } + } } # EOF hal_freescale_dma.cdl
--- a/packages/hal/misc/freescale/edma/current/include/freescale_edma.h +++ b/packages/hal/misc/freescale/edma/current/include/freescale_edma.h @@ -51,16 +51,23 @@ // //=========================================================================== +#include <pkgconf/hal.h> +#if defined CYGHWR_HAL_EDMA_TCD_SECTION || defined CYGHWR_HAL_EDMA_MEM_SECTION +# include <cyg/infra/cyg_type.h> +#endif + // ---------------------------------------------------------------------------- // DMAMUX DMA Multiplexer // DMAMUX - Peripheral register structure typedef volatile struct cyghwr_hal_freescale_dmamux_s { - cyg_uint8 chcfg[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Channel Configuration Register + cyg_uint8 chcfg[CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM]; // Channel Configuration Register } cyghwr_hal_freescale_dmamux_t; -// DMAMUX - Peripheral instance base addresses -#define CYGHWR_HAL_FREESCALE_DMAMUX0_P ((cyghwr_hal_freescale_dmamux_t *) 0x40021000) +// DMAMUX - Peripheral instance base addresses - defined in HAL (typically var_io_devs.h) +// CYGHWR_IO_FREESCALE_DMAMUX0_P defined in HAL +// CYGHWR_IO_FREESCALE_DMAMUX1_P defined in HAL + // ---------------------------------------------------------------------------- // DMAMUX Register Masks @@ -76,7 +83,7 @@ typedef volatile struct cyghwr_hal_frees #define FREESCALE_DMAMUX_CHCFG_ASIS FREESCALE_DMAMUX_CHCFG_ENBL_M // DMAMUX DMA request sources -// Provided by HAL (var_io_devs.h) +// Provided by HAL (typically var_io_devs.h) #define FREESCALE_DMAMUX_SRC(__src) (_src) //--------------------------------------------------------------------------- @@ -92,6 +99,17 @@ enum { FREESCALE_DMA_PRI_CH9, FREESCALE_DMA_PRI_CH8, FREESCALE_DMA_PRI_CH15, FREESCALE_DMA_PRI_CH14, FREESCALE_DMA_PRI_CH13, FREESCALE_DMA_PRI_CH12 +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16 + , + FREESCALE_DMA_PRI_CH19, FREESCALE_DMA_PRI_CH18, + FREESCALE_DMA_PRI_CH17, FREESCALE_DMA_PRI_CH16, + FREESCALE_DMA_PRI_CH23, FREESCALE_DMA_PRI_CH22, + FREESCALE_DMA_PRI_CH21, FREESCALE_DMA_PRI_CH20, + FREESCALE_DMA_PRI_CH27, FREESCALE_DMA_PRI_CH26, + FREESCALE_DMA_PRI_CH25, FREESCALE_DMA_PRI_CH24, + FREESCALE_DMA_PRI_CH31, FREESCALE_DMA_PRI_CH30, + FREESCALE_DMA_PRI_CH29, FREESCALE_DMA_PRI_CH28 +#endif }; // Transfer control descriptor @@ -155,7 +173,8 @@ typedef volatile struct cyghwr_hal_frees tcd[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; // Transfer control descriptors } cyghwr_hal_freescale_edma_t; -#define CYGHWR_HAL_FREESCALE_EDMA0_P ((cyghwr_hal_freescale_edma_t *)0x40008000) +// CYGHWR_IO_FREESCALE_EDMA0_P is defined by HAL +// #define CYGHWR_IO_FREESCALE_EDMA0_P // ---------------------------------------------------------------------------- // DMA Register Bits @@ -165,6 +184,8 @@ typedef volatile struct cyghwr_hal_frees #define FREESCALE_EDMA_CR_EDBG_S 1 #define FREESCALE_EDMA_CR_ERCA_M 0x4 #define FREESCALE_EDMA_CR_ERCA_S 2 +#define FREESCALE_EDMA_CR_ERGA_M 0x8 +#define FREESCALE_EDMA_CR_ERGA_S 3 #define FREESCALE_EDMA_CR_HOE_M 0x10 #define FREESCALE_EDMA_CR_HOE_S 4 #define FREESCALE_EDMA_CR_HALT_M 0x20 @@ -177,6 +198,9 @@ typedef volatile struct cyghwr_hal_frees #define FREESCALE_EDMA_CR_ECX_S 16 #define FREESCALE_EDMA_CR_CX_M 0x20000 #define FREESCALE_EDMA_CR_CX_S 17 + +#define FREESCALE_EDMA_GR_PRI(_gr_, _pr_) VALUE_((8 + 2 * _gr_), (_pr_ & 0x3)) + // ES Bit Fields #define FREESCALE_EDMA_ES_DBE_M 0x1 #define FREESCALE_EDMA_ES_DBE_S 0 @@ -200,6 +224,8 @@ typedef volatile struct cyghwr_hal_frees VALUE_(FREESCALE_EDMA_ES_ERRCHN_S, __val) #define FREESCALE_EDMA_ES_CPE_M 0x4000 #define FREESCALE_EDMA_ES_CPE_S 14 +#define FREESCALE_EDMA_ES_GPE_M 0x8000 +#define FREESCALE_EDMA_ES_GPE_S 15 #define FREESCALE_EDMA_ES_ECX_M 0x10000 #define FREESCALE_EDMA_ES_ECX_S 16 #define FREESCALE_EDMA_ES_VLD_M 0x80000000 @@ -208,7 +234,7 @@ typedef volatile struct cyghwr_hal_frees #define FREESCALE_EDMA_ERQ(__rq) BIT(__rq) // EEI Bit Fields #define FREESCALE_EDMA_EEI(__rq) BIT(__rq) -#define FREESCALE_EDMA_CHAN_M 0x0F +#define FREESCALE_EDMA_CHAN_M 0x1F // CEEI Bit Fields #define FREESCALE_EDMA_CEEI_CEEI(__val) (__val & FREESCALE_EDMA_CHAN_M) #define FREESCALE_EDMA_CEEI_CAEE_M 0x40 @@ -216,7 +242,6 @@ typedef volatile struct cyghwr_hal_frees #define FREESCALE_EDMA_CEEI_NOP_M 0x80 #define FREESCALE_EDMA_CEEI_NOP_S 7 // SEEI Bit Fields -#define FREESCALE_EDMA_SEEI_SEEI_M 0xF #define FREESCALE_EDMA_SEEI_SEEI(__val) (__val & FREESCALE_EDMA_CHAN_M) #define FREESCALE_EDMA_SEEI_SAEE_M 0x40 #define FREESCALE_EDMA_SEEI_SAEE_S 6 @@ -265,7 +290,9 @@ typedef volatile struct cyghwr_hal_frees // HRS Bit Fields #define FREESCALE_EDMA_HRS(__ch) BIT(__ch) // DCHPRI Bit Fields + #define FREESCALE_EDMA_DCHPRI_CHPRI_M 0xF + #define FREESCALE_EDMA_DCHPRI_CHPRI(__val) \ (__val & FREESCALE_EDMA_DCHPRI_CHPRI_M) #define FREESCALE_EDMA_DCHPRI_DPA_M 0x40 @@ -382,6 +409,20 @@ typedef volatile struct cyghwr_hal_frees #define FREESCALE_EDMA_BITER_ELINKYES_ELINK_M 0x8000 #define FREESCALE_EDMA_BITER_ELINKYES_ELINK_S 15 +// EDMA buffer descriptor memory section +#ifdef CYGHWR_HAL_EDMA_TCD_SECTION +# define EDMA_RAM_TCD_SECTION CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_EDMA_TCD_SECTION) +#else +# define EDMA_RAM_MEM_SECTION +#endif // CYGHWR_HAL_EDMA_MEM_SECTION + +// EDMA buffer memory section +#ifdef CYGHWR_HAL_EDMA_BUF_SECTION +# define EDMA_RAM_BUF_SECTION CYGBLD_ATTRIB_SECTION(CYGHWR_HAL_EDMA_BUF_SECTION) +#else +# define EDMA_RAM_BUF_SECTION +#endif // CYGHWR_HAL_EDMA_BUF_SECTION + //----------------------------------------------------------------------------- // DMA Channel data @@ -396,8 +437,7 @@ typedef struct cyghwr_hal_freescale_dma_ // DMA Channel set typedef struct cyghwr_hal_freescale_dma_set_s { - cyghwr_hal_freescale_edma_t *edma_p; - cyghwr_hal_freescale_dmamux_t *dmamux_p; + cyghwr_hal_freescale_edma_t* edma_p; const cyghwr_hal_freescale_dma_chan_set_t *chan_p; cyg_uint8 chan_n; } cyghwr_hal_freescale_dma_set_t; @@ -407,7 +447,7 @@ typedef struct cyghwr_hal_freescale_dma_ hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p); __externC void -hal_freescale_edma_diag(cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask); +hal_freescale_edma_diag(const cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask); __externC void hal_freescale_edma_transfer_init(cyghwr_hal_freescale_edma_t *edma_p,
--- a/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c +++ b/packages/hal/misc/freescale/edma/current/src/hal_freescale_edma.c @@ -75,23 +75,42 @@ const cyg_uint8 const PRICHAN_I[CYGNUM_H FREESCALE_DMA_PRI_CH10, FREESCALE_DMA_PRI_CH11, FREESCALE_DMA_PRI_CH12, FREESCALE_DMA_PRI_CH13, FREESCALE_DMA_PRI_CH14, FREESCALE_DMA_PRI_CH15 +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE + , + FREESCALE_DMA_PRI_CH16, FREESCALE_DMA_PRI_CH17, + FREESCALE_DMA_PRI_CH18, FREESCALE_DMA_PRI_CH19, + FREESCALE_DMA_PRI_CH20, FREESCALE_DMA_PRI_CH21, + FREESCALE_DMA_PRI_CH22, FREESCALE_DMA_PRI_CH23, + FREESCALE_DMA_PRI_CH24, FREESCALE_DMA_PRI_CH25, + FREESCALE_DMA_PRI_CH26, FREESCALE_DMA_PRI_CH27, + FREESCALE_DMA_PRI_CH28, FREESCALE_DMA_PRI_CH29, + FREESCALE_DMA_PRI_CH30, FREESCALE_DMA_PRI_CH31 +#endif }; // Find an eDMA channel with given priority -volatile cyg_uint8* +static volatile cyg_uint8* hal_freescale_edma_find_chan_with_pri(cyghwr_hal_freescale_edma_t *edma_p, - cyg_uint8 pri) + cyg_uint32 pri, cyg_uint32 group_i) { volatile cyg_uint8 *chan_p; - for(chan_p = &edma_p->dchpri[0]; - chan_p < &edma_p->dchpri[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]; + for(chan_p = &edma_p->dchpri[group_i * CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE]; + chan_p < &edma_p->dchpri[group_i * CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE + + CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE]; chan_p++) { - if(*chan_p == pri) break; + if((*chan_p & FREESCALE_EDMA_DCHPRI_CHPRI_M) == pri) break; } +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE + if(0 == group_i){ + if(chan_p >= &edma_p->dchpri[CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE]) + chan_p = NULL; + } +#endif if(chan_p >= &edma_p->dchpri[CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM]) chan_p = NULL; + return chan_p; } @@ -101,13 +120,22 @@ hal_freescale_edma_find_chan_with_pri(cy void hal_freescale_edma_init_1chan( cyghwr_hal_freescale_edma_t *edma_p, - cyghwr_hal_freescale_dmamux_t *dmamux_p, const cyghwr_hal_freescale_dma_chan_set_t *chan_p) { cyg_uint8 oldprio; + cyghwr_hal_freescale_dmamux_t *dmamux_p; volatile cyg_uint8 *prev_ch_reqprio_p; // Previous chan with req. prio. - volatile cyg_uint8 *chcfg_p = &dmamux_p->chcfg[chan_p->dma_chan_i]; + volatile cyg_uint8 *chcfg_p; + cyg_uint32 group_i; +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE + dmamux_p = chan_p->dma_chan_i < CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ? + CYGHWR_IO_FREESCALE_DMAMUX0_P : + CYGHWR_IO_FREESCALE_DMAMUX1_P; +#else + dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P; +#endif + chcfg_p = &dmamux_p->chcfg[chan_p->dma_chan_i % CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM]; edma_p->cerq = chan_p->dma_chan_i; if(chan_p->dma_src & FREESCALE_DMAMUX_CHCFG_SOURCE_M) { @@ -119,8 +147,9 @@ hal_freescale_edma_init_1chan( if((chan_p->dma_prio != FREESCALE_EDMA_DCHPRI_ASIS) && (edma_p->dchpri[PRICHAN_I[chan_p->dma_chan_i]] != chan_p->dma_prio)) { + group_i = chan_p->dma_chan_i >= CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE ? 1 : 0; if((prev_ch_reqprio_p = - hal_freescale_edma_find_chan_with_pri(edma_p, chan_p->dma_prio))) + hal_freescale_edma_find_chan_with_pri(edma_p, chan_p->dma_prio, group_i))) { oldprio = edma_p->dchpri[PRICHAN_I[chan_p->dma_chan_i]]; edma_p->dchpri[PRICHAN_I[chan_p->dma_chan_i]] = chan_p->dma_prio; @@ -129,7 +158,6 @@ hal_freescale_edma_init_1chan( } } - // Init DMA controller const cyg_uint32 FREESCALE_EDMA_CR_INI = 0 @@ -142,12 +170,26 @@ const cyg_uint32 FREESCALE_EDMA_CR_INI = #ifdef CYGOPT_HAL_FREESCALE_EDMA_ERCA | FREESCALE_EDMA_CR_ERCA_M #endif +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16 +#ifdef CYGOPT_HAL_FREESCALE_EDMA_ERGA + | FREESCALE_EDMA_CR_ERGA_M +#endif + | FREESCALE_EDMA_GR_PRI(0, CYGNUM_HAL_FREESCALE_EDMA_GR0_PRIO) + | FREESCALE_EDMA_GR_PRI(1, CYGNUM_HAL_FREESCALE_EDMA_GR1_PRIO) +#endif ; void hal_freescale_edma_init(cyghwr_hal_freescale_edma_t *edma_p) { - edma_p->cr |= FREESCALE_EDMA_CR_INI; + cyg_uint32 regval; + + regval = edma_p->cr; +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16 + regval &= ~(FREESCALE_EDMA_GR_PRI(0, 3) | FREESCALE_EDMA_GR_PRI(1, 3)); +#endif + regval |= FREESCALE_EDMA_CR_INI; + edma_p->cr = regval; } // Initialize a set of DMA channels @@ -155,27 +197,25 @@ void hal_freescale_edma_init_chanset(cyghwr_hal_freescale_dma_set_t *inidat_p) { cyghwr_hal_freescale_edma_t *edma_p; - cyghwr_hal_freescale_dmamux_t *dmamux_p; const cyghwr_hal_freescale_dma_chan_set_t *chan_p; - edma_p = inidat_p->edma_p; + edma_p = inidat_p->edma_p = CYGHWR_HAL_FREESCALE_EDMA0_P; hal_freescale_edma_init(edma_p); - dmamux_p = inidat_p->dmamux_p; for(chan_p = inidat_p->chan_p; chan_p < inidat_p->chan_p + inidat_p->chan_n; chan_p++) { - hal_freescale_edma_init_1chan(edma_p, dmamux_p, chan_p); + hal_freescale_edma_init_1chan(edma_p, chan_p); } edma_p->es = 0; } -#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > 16 -#define DMA_CHANMASK_FORMAT "0x%08x" +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM == 32 +# define DMA_CHANMASK_FORMAT "0x%08x" #else -#define DMA_CHANMASK_FORMAT "0x%04x" +# define DMA_CHANMASK_FORMAT "0x%04x" #endif #define EDMA_DIAG_PRINTF_FORMAT(__mf) "CR=0x%08x ES=0x%08x ERQ=" __mf \ @@ -183,7 +223,7 @@ hal_freescale_edma_init_chanset(cyghwr_h // Display DMA configuration void -hal_freescale_edma_diag(cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask) +hal_freescale_edma_diag(const cyghwr_hal_freescale_dma_set_t *inidat_p, cyg_uint32 mask) { cyghwr_hal_freescale_edma_t *edma_p; cyghwr_hal_freescale_dmamux_t *dmamux_p; @@ -192,19 +232,29 @@ hal_freescale_edma_diag(cyghwr_hal_frees cyg_uint32 chan_p_i; edma_p = inidat_p->edma_p; - dmamux_p = inidat_p->dmamux_p; - diag_printf("DMAMUX: %p DMA: %p\n", dmamux_p, edma_p); diag_printf(EDMA_DIAG_PRINTF_FORMAT(DMA_CHANMASK_FORMAT), edma_p->cr, edma_p->es, edma_p->erq, edma_p->irq, edma_p->err, edma_p->hrs); for(chan_i = 0; chan_i < CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM; chan_i++){ if(mask & 0x1){ - diag_printf("Chan %2d: CHCFG=0x%02x (%2d) DCHPRI=0x%02x", chan_i, - dmamux_p->chcfg[chan_i], - FREESCALE_DMAMUX_CHCFG_SOURCE(dmamux_p->chcfg[chan_i]), - edma_p->dchpri[PRICHAN_I[chan_i]]); chan_p = inidat_p->chan_p; +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE + dmamux_p = chan_i < CYGNUM_HAL_FREESCALE_DMAMUX_CHAN_NUM ? + CYGHWR_IO_FREESCALE_DMAMUX0_P : + CYGHWR_IO_FREESCALE_DMAMUX1_P; +#else + dmamux_p = CYGHWR_IO_FREESCALE_DMAMUX0_P; +#endif + diag_printf("Chan %2d: CHCFG=0x%02x (%2d) DCHPRI=0x%02x dmamux[%c]=%p", chan_i, + dmamux_p->chcfg[chan_i % 16], + FREESCALE_DMAMUX_CHCFG_SOURCE(dmamux_p->chcfg[chan_i % 16]), + edma_p->dchpri[PRICHAN_I[chan_i]], + CYGHWR_IO_FREESCALE_DMAMUX0_P == dmamux_p ? '0' : ( +#if CYGNUM_HAL_FREESCALE_EDMA_CHAN_NUM > CYGNUM_HAL_FREESCALE_EDMA_GROUP_SIZE + CYGHWR_IO_FREESCALE_DMAMUX1_P == dmamux_p ? '1' : +#endif + '?'), dmamux_p); for(chan_p_i = 0; chan_p_i < inidat_p->chan_n; chan_p_i++){ if(chan_p->dma_chan_i == chan_i){ diag_printf(" ISR_NUM=%2d[0x%02x] ISR_PRI=%3d[0x%02x]",