Mercurial > ecos
changeset 3191:4f12eb4ce827
Synchronized with Kinetis variant changes to SDRAM controller support. Memory layouts adapted to separate data and code cacing partitions. [Bugzilla 1001606]
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--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/ChangeLog @@ -1,3 +1,19 @@ +2012-09-28 Ilija Kocho <ilijak@siva.com.mk> + + * twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl + * twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h + * twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi + * twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h + * twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi + * twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h + * twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi + * twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h + * twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi + * twr_k70f120m/current/src/twr_k70f120m_misc.c + Synchronized with Kinetis variant changes to SDRAM controller support. + Memory layouts adapted to separate data and code cacing partitions. + [Bugzilla 1001606] + 2012-05-19 John Dallaway <john@dallaway.org.uk> * cdl/hal_cortexm_kinetis_twr_k70f120m.cdl: Reference per-package
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/cdl/hal_cortexm_kinetis_twr_k70f120m.cdl @@ -93,6 +93,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Freescale TWR-K70F120M\"" puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_system_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 4000000" } cdl_component CYG_HAL_STARTUP_ENV { @@ -133,7 +134,7 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T by RedBoot into external RAM." } - cdl_option CYGHWR_MEMORY_LAYOUT_PLF { + cdl_component CYGHWR_MEMORY_LAYOUT_PLF { display "Memory layout by platform" flavor data active_if { CYG_HAL_STARTUP_PLF != "ByVariant" } @@ -151,6 +152,13 @@ cdl_package CYGPKG_HAL_CORTEXM_KINETIS_T description " Combination of 'Startup type' and 'Kinetis member in use' produces the memory layout." + + cdl_option CYGHWR_MEMORY_RAM_RESERVED { + display "Reserved RAM space \[Bytes\]" + flavor data + legal_values 0 to 0x40000 + default_value 0x20000 + } } cdl_option CYGNUM_HAL_CORTEXM_KINETIS_PLF_CLOCK_FREQ_SP {
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.h @@ -9,14 +9,18 @@ #define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE) #define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) -#define CYGMEM_REGION_sram_u (0x20000000) -#define CYGMEM_REGION_sram_u_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) -#define CYGMEM_REGION_sram_u_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) -#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE) +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) #define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + #define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) #define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) #define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_ram.ldi @@ -5,22 +5,24 @@ MEMORY { - sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE - flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE - ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE - ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE + sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE + sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE } SECTIONS { SECTIONS_BEGIN - USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE (NOLOAD), LMA_EQ_VMA) - SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 , LMA_EQ_VMA) - SECTION_rom_vectors (ram, CYGHWR_HAL_KINETIS_DDR_BASE + 0x20000, LMA_EQ_VMA) - SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE+CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) @@ -35,5 +37,5 @@ SECTIONS hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); hal_virtual_vector_table = hal_vsr_table + 128*4; -hal_startup_stack = CYGHWR_HAL_KINETIS_DDR_BASE + CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-32; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.h @@ -17,10 +17,18 @@ #define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) #define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) -#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE) +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) #define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +//#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE) +//#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) +//#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + #define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) #define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) #define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_sram2s_extram_rom.ldi @@ -8,7 +8,8 @@ MEMORY sram_l : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE sram : ORIGIN = 0x20000000, LENGTH = CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE - ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE } @@ -34,15 +35,15 @@ SECTIONS SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) - USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE (NOLOAD), LMA_EQ_VMA) - SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) - USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), FOLLOWING(.sram)) - SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_BASE, FOLLOWING (.noncache)) + USER_SECTION (code_sram, sram_l, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 (NOLOAD), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000, FOLLOWING (.got)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram)) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) SECTIONS_END } -hal_vsr_table = (0x20000000); +hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); hal_virtual_vector_table = hal_vsr_table + 128*4; hal_startup_stack = (0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE);
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.h @@ -9,10 +9,14 @@ #define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_KINETIS_SRAM_SIZE) #define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) -#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE) +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) #define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + #define CYGMEM_REGION_ramnc (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE) #define CYGMEM_REGION_ramnc_SIZE (CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE) #define CYGMEM_REGION_ramnc_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_ram.ldi @@ -3,28 +3,30 @@ #include <pkgconf/hal.h> #include <cyg/infra/cyg_type.inc> + MEMORY { - sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE - flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE - ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE - ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE } SECTIONS { SECTIONS_BEGIN - SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400 , LMA_EQ_VMA) - SECTION_rom_vectors (ram, CYGHWR_HAL_KINETIS_DDR_BASE + 0x20000, LMA_EQ_VMA) - SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, LMA_EQ_VMA) + SECTION_rom_vectors (ramcod, CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LMA_EQ_VMA) + SECTION_RELOCS (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ramcod, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE + CYGHWR_MEMORY_RAM_RESERVED, LMA_EQ_VMA) SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) - SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ramcod, ALIGN (0x8), LMA_EQ_VMA) SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); @@ -34,5 +36,6 @@ SECTIONS hal_vsr_table = (0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE); hal_virtual_vector_table = hal_vsr_table + 128*4; -hal_startup_stack = CYGHWR_HAL_KINETIS_DDR_BASE + CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE; +//hal_startup_stack = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE + CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE; +hal_startup_stack = 0x20000000 + CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE;
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.h @@ -13,7 +13,11 @@ #define CYGMEM_REGION_flash_SIZE (CYGHWR_HAL_KINETIS_FLASH_SIZE) #define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R) -#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_BASE) +#define CYGMEM_REGION_ramcod (CYGHWR_HAL_KINETIS_DDR_CODE_BASE) +#define CYGMEM_REGION_ramcod_SIZE (CYGHWR_HAL_KINETIS_DDR_CODE_SIZE) +#define CYGMEM_REGION_ramcod_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (CYGHWR_HAL_KINETIS_DDR_CACHED_BASE) #define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE) #define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/include/pkgconf/mlt_kinetis_flash_unisram_extram_rom.ldi @@ -5,10 +5,11 @@ MEMORY { - sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE - flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE - ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE - ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE + sram : ORIGIN = 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE, LENGTH = CYGHWR_HAL_KINETIS_SRAM_SIZE-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x00000000, LENGTH = CYGHWR_HAL_KINETIS_FLASH_SIZE + ramcod : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CODE_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CODE_SIZE + ram : ORIGIN = CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_CACHED_SIZE + ramnc : ORIGIN = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE, LENGTH = CYGHWR_HAL_KINETIS_DDR_NON_CACHED_SIZE } SECTIONS @@ -34,10 +35,10 @@ SECTIONS SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) SECTION_sram (sram, 0x20000000 - CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE + 0x400, FOLLOWING (.got)) - USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), FOLLOWING(.sram)) - SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_BASE, FOLLOWING (.noncache)) + SECTION_data (ram, CYGHWR_HAL_KINETIS_DDR_CACHED_BASE, FOLLOWING (.sram)) SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + USER_SECTION (noncache, ramnc, CYGHWR_HAL_KINETIS_DDR_NON_CACHED_BASE (NOLOAD), LMA_EQ_VMA) SECTIONS_END }
--- a/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c +++ b/packages/hal/cortexm/kinetis/twr_k70f120m/current/src/twr_k70f120m_misc.c @@ -83,56 +83,57 @@ static inline void hal_gpio_init(void); #endif #ifdef CYGPKG_HAL_CORTEXM_KINETIS_DDRMC + // DDRAM controller setup parameters const cyg_uint32 kinetis_ddr_cfg[] = { - 0, 0x00000400, // DDR_CR00 - 2, 0x02000031, // DDR_CR02 - 3, 0x02020506, // DDR_CR03 - 4, 0x06090202, // DDR_CR04 - 5, 0x02020302, // DDR_CR05 - 6, 0x02904002, // DDR_CR06 - 7, 0x01000303, // DDR_CR07 - 8, 0x05030201, // DDR_CR08 - 9, 0x020000c8, // DDR_CR09 - 10, 0x03003207, // DDR_CR10 - 11, 0x01000000, // DDR_CR11 - 12, 0x04920031, // DDR_CR12 - 13, 0x00000005, // DDR_CR13 - 14, 0x00C80002, // DDR_CR14 - 15, 0x00000032, // DDR_CR15 - 16, 0x00000001, // DDR_CR16 - 20, 0x00030300, // DDR_CR20 - 21, 0x00040232, // DDR_CR21 - 22, 0x00000000, // DDR_CR22 - 23, 0x00040302, // DDR_CR23 - 25, 0x0A010201, // DDR_CR25 - 26, 0x0101FFFF, // DDR_CR26 - 27, 0x01010101, // DDR_CR27 - 28, 0x00000003, // DDR_CR28 - 29, 0x00000000, // DDR_CR29 - 30, 0x00000001, // DDR_CR30 - 34, 0x02020101, // DDR_CR34 - 36, 0x01010201, // DDR_CR36 - 37, 0x00000200, // DDR_CR37 - 38, 0x00200000, // DDR_CR38 - 39, 0x01010020, // DDR_CR39 - 40, 0x00002000 | SYNC_ASYNC, // DDR_CR40 - 41, 0x01010020, // DDR_CR41 - 42, 0x00002000 | SYNC_ASYNC, // DDR_CR42 - 43, 0x01010020, // DDR_CR43 - 44, 0x00000000 | SYNC_ASYNC, // DDR_CR44 - 45, 0x03030303, // DDR_CR45 - 46, 0x02006401, // DDR_CR46 - 47, 0x01020202, // DDR_CR47 - 48, 0x01010064, // DDR_CR48 - 49, 0x00020101, // DDR_CR49 - 50, 0x00000064, // DDR_CR50 - 52, 0x02000602, // DDR_CR52 - 53, 0x03c80000, // DDR_CR53 - 54, 0x03c803c8, // DDR_CR54 - 55, 0x03c803c8, // DDR_CR55 - 56, 0x020303c8, // DDR_CR56 - 57, 0x01010002 // DDR_CR57 + 0x00000400, // DDR_CR00 + 0x02000031, // DDR_CR02 + 0x02020506, // DDR_CR03 + 0x06090202, // DDR_CR04 + 0x02020302, // DDR_CR05 + 0x02904002, // DDR_CR06 + 0x01000303, // DDR_CR07 + 0x05030201, // DDR_CR08 + 0x020000c8, // DDR_CR09 + 0x03003207, // DDR_CR10 + 0x01000000, // DDR_CR11 + 0x04920031, // DDR_CR12 + 0x00000005, // DDR_CR13 + 0x00C80002, // DDR_CR14 + 0x00000032, // DDR_CR15 + 0x00000001, // DDR_CR16 + 0x00030300, // DDR_CR20 + 0x00040232, // DDR_CR21 + 0x00000000, // DDR_CR22 + 0x00040302, // DDR_CR23 + 0x0A010201, // DDR_CR25 + 0x0101FFFF, // DDR_CR26 + 0x01010101, // DDR_CR27 + 0x00000003, // DDR_CR28 + 0x00000000, // DDR_CR29 + 0x00000001, // DDR_CR30 + 0x02020101, // DDR_CR34 + 0x01010201, // DDR_CR36 + 0x00000200, // DDR_CR37 + 0x00200000, // DDR_CR38 + 0x01010020, // DDR_CR39 + 0x00002000 | SYNC_ASYNC, // DDR_CR40 + 0x01010020, // DDR_CR41 + 0x00002000 | SYNC_ASYNC, // DDR_CR42 + 0x01010020, // DDR_CR43 + 0x00000000 | SYNC_ASYNC, // DDR_CR44 + 0x03030303, // DDR_CR45 + 0x02006401, // DDR_CR46 + 0x01020202, // DDR_CR47 + 0x01010064, // DDR_CR48 + 0x00020101, // DDR_CR49 + 0x00000064, // DDR_CR50 + 0x02000602, // DDR_CR52 + 0x03c80000, // DDR_CR53 + 0x03c803c8, // DDR_CR54 + 0x03c803c8, // DDR_CR55 + 0x020303c8, // DDR_CR56 + 0x01010002 // DDR_CR57 }; #endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC @@ -147,7 +148,8 @@ const cyg_uint32 kinetis_ddr_cfg[] = { __externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR hal_system_init( void ) { -#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM) +//#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM) +#if !defined(CYG_HAL_STARTUP_RAM) hal_wdog_disable(); hal_gpio_init(); hal_start_clocks(); @@ -155,26 +157,6 @@ hal_system_init( void ) HAL_CORTEXM_KINETIS_DDRMC_INIT( kinetis_ddr_cfg ); # endif // CYGPKG_HAL_CORTEXM_KINETIS_DDRMC #endif -#if defined(CYG_HAL_STARTUP_SRAM) && !defined(CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED) - // Note: For CYG_HAL_STARTUP_SRAM, the SRAM_L bank simulates ROM - // Relocate data from ROM to RAM - { - register cyg_uint32 *ram_p, *rom_p; - for( ram_p = &__ram_data_start, rom_p = &__rom_data_start; - ram_p < &__ram_data_end; - ram_p++, rom_p++ ) - *ram_p = *rom_p; - } - - // Relocate data from ROM to SRAM - { - register cyg_uint32 *ram_p, *sram_p; - for( ram_p = &__sram_data_start, sram_p = &__srom_data_start; - ram_p < &__sram_data_end; - ram_p++, sram_p++ ) - *ram_p = *sram_p; - } -#endif } //=========================================================================== @@ -232,23 +214,26 @@ static struct { CYG_ADDRESS end; // End address (last byte) } hal_data_access[] = { - { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // Main RAM + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // System bus RAM partition #ifdef CYGMEM_REGION_sram - { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM #elif defined CYGMEM_REGION_sram_l - { CYGMEM_REGION_sram_l, CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1 }, // On-chip SRAM lower bank + { CYGMEM_REGION_sram_l, CYGMEM_REGION_sram_l+CYGMEM_REGION_sram_l_SIZE-1 }, // On-chip SRAM lower bank +#endif +#ifdef CYGMEM_REGION_ramcod + { CYGMEM_REGION_ramcod, CYGMEM_REGION_ramcod+CYGMEM_REGION_ramcod_SIZE-1 }, // Code bus RAM partition +#endif +#ifdef CYGMEM_REGION_ramnc + { CYGMEM_REGION_ramnc, CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1 }, // Non cachable RAM partition #endif #ifdef CYGMEM_REGION_flash - { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash #endif #ifdef CYGMEM_REGION_rom - { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash [currently none] #endif -#ifdef CYGMEM_REGION_ramnc - { CYGMEM_REGION_ramnc, CYGMEM_REGION_ramnc+CYGMEM_REGION_ramnc_SIZE-1 }, // Non cachable RAM -#endif - { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals - { 0x40000000, 0x60000000-1 }, // Chip specific peripherals + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 } // Chip specific peripherals }; __externC int cyg_hal_stub_permit_data_access( void* addr, cyg_uint32 count ) @@ -290,13 +275,22 @@ cyg_plf_memory_segment(int seg, unsigned break; #endif #ifdef CYGMEM_REGION_sram_l -# define CASE_RAMNC 5 +# define CASE_CODE 3 +# define CASE_RAMNC 4 case 2: *start = (unsigned char *)CYGMEM_REGION_sram_l; *end = (unsigned char *)(CYGMEM_REGION_sram_l + CYGMEM_REGION_sram_l_SIZE); break; #else -# define CASE_RAMNC 4 +# define CASE_CODE 2 +# define CASE_RAMNC 3 +#endif + +#ifdef CYGMEM_REGION_ramcod + case CASE_CODE: + *start = (unsigned char *)CYGMEM_REGION_ramcod; + *end = (unsigned char *)(CYGMEM_REGION_ramcod + CYGMEM_REGION_ramcod_SIZE); + break; #endif #ifdef CYGMEM_REGION_ramnc