Mercurial > ecos
changeset 3144:a9a10d06a94b
Add support for STM32 F2 / F4 processors, and a few minor improvements.
| author | jlarmour |
|---|---|
| date | Sun, 01 Apr 2012 02:05:07 +0000 |
| parents | ceb1113eb4bd |
| children | ed053d86fcd2 |
| files | packages/devs/serial/cortexm/stm32/current/ChangeLog packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h |
| diffstat | 4 files changed, 252 insertions(+), 16 deletions(-) [+] |
line wrap: on
line diff
--- a/packages/devs/serial/cortexm/stm32/current/ChangeLog +++ b/packages/devs/serial/cortexm/stm32/current/ChangeLog @@ -1,8 +1,36 @@ +2011-12-15 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/ser_cortexm_stm32.cdl: Default baud rates to the HAL + diag console channel. Add support for serial port 5 + (USART6 in STM32 speak). Select serial/tty test devices better + according to the configuration. + * src/stm32_serial.c: Support serial port 5. Make use of AFIO + remap specific to F1 processors. + 2010-12-31 John Dallaway <john@dallaway.org.uk> * src/stm32_serial.c, src/stm32_serial.h: Set the M bit when configuring for 8 data bits + parity bit. [ Bugzilla 1001068 ] +2009-12-03 Nick Garnett <nickg@ecoscentric.com> + + * cdl/ser_cortexm_stm32.cdl: + * src/stm32_serial.c (stm32_serial_info, stm32_serial_info0) + (stm32_serial_info1, stm32_serial_info2, stm32_serial_info3) + (stm32_serial_info4, stm32_serial_init): + Add configuration options to set serial ISR interrupt priorities. + +2009-07-02 Nick Garnett <nickg@ecoscentric.com> + + * src/stm32_serial.c (stm32_serial_info) + (stm32_serial_config_port): Add support for UART pin remap. + +2009-06-29 Nick Garnett <nickg@ecoscentric.com> + + * src/stm32_serial.c (stm32_serial_info) + (stm32_serial_config_port): Add support for individual clock + enable on each UART. + 2008-10-07 Nick Garnett <nickg@ecoscentric.com> * cdl/ser_cortexm_stm32.cdl: @@ -15,7 +43,7 @@ 2008-10-07 Nick Garnett <nickg@ecoscen // ####GPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 2008, 2010 Free Software Foundation, Inc. +// Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by
--- a/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl +++ b/packages/devs/serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl @@ -8,7 +8,7 @@ ## ####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 2008 Free Software Foundation, Inc. +## Copyright (C) 2008, 2011 Free Software Foundation, Inc. ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -91,7 +91,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 230400 } - default_value { 38400 } + default_value { CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } description " This option specifies the default baud rate (speed) for the ST STM32 port 0." @@ -106,6 +106,13 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S This option specifies the size of the internal buffers used for the ST STM32 port 0." } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_INT_PRI { + display "Interrupt priority for STM32 serial port 0" + flavor data + default_value 128 + legal_values 0 to 255 + } } cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 { @@ -131,7 +138,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 230400 } - default_value 38400 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD description " This option specifies the default baud rate (speed) for the ST STM32 port 1." @@ -146,6 +153,13 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S This option specifies the size of the internal buffers used for the ST STM32 port 1." } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_INT_PRI { + display "Interrupt priority for STM32 serial port 1" + flavor data + default_value 128 + legal_values 0 to 255 + } } cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 { @@ -171,7 +185,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 230400 } - default_value 38400 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD description " This option specifies the default baud rate (speed) for the ST STM32 port 2." @@ -186,6 +200,13 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S This option specifies the size of the internal buffers used for the ST STM32 port 2." } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_INT_PRI { + display "Interrupt priority for STM32 serial port 2" + flavor data + default_value 128 + legal_values 0 to 255 + } } cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 { @@ -211,7 +232,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 230400 } - default_value 38400 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD description " This option specifies the default baud rate (speed) for the ST STM32 port 3." @@ -226,6 +247,13 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S This option specifies the size of the internal buffers used for the ST STM32 port 3." } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_INT_PRI { + display "Interrupt priority for STM32 serial port 3" + flavor data + default_value 128 + legal_values 0 to 255 + } } cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 { @@ -251,7 +279,7 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 230400 } - default_value 38400 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD description " This option specifies the default baud rate (speed) for the ST STM32 port 4." @@ -266,6 +294,60 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S This option specifies the size of the internal buffers used for the ST STM32 port 4." } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_INT_PRI { + display "Interrupt priority for STM32 serial port 4" + flavor data + default_value 128 + legal_values 0 to 255 + } +} + +cdl_component CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5 { + display "ST STM32 serial port 5 driver" + flavor bool + default_value CYGINT_HAL_STM32_UART5>0 + description " + This option includes the serial device driver for the ST STM32 + port 5." + + cdl_option CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME { + display "Device name for ST STM32 serial port 5 driver" + flavor data + default_value {"\"/dev/ser5\""} + description " + This option specifies the name of the serial device for the + ST STM32 port 5." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD { + display "Baud rate for the ST STM32 serial port 5 driver" + flavor data + legal_values { 50 75 110 "134_5" 150 200 300 600 1200 1800 2400 3600 + 4800 7200 9600 14400 19200 38400 57600 115200 230400 + } + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option specifies the default baud rate (speed) for the + ST STM32 port 5." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE { + display "Buffer size for the ST STM32 serial port 5 driver" + flavor data + legal_values 0 to 8192 + default_value 128 + description " + This option specifies the size of the internal buffers used + for the ST STM32 port 5." + } + + cdl_option CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_INT_PRI { + display "Interrupt priority for STM32 serial port 5" + flavor data + default_value 128 + legal_values 0 to 255 + } } @@ -312,13 +394,23 @@ cdl_component CYGPKG_IO_SERIAL_CORTEXM_S cdl_option CYGPRI_SER_TEST_SER_DEV { display "Serial device used for testing" flavor data - default_value { "\"/dev/ser1\"" } + default_value { CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL0_NAME : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL1_NAME : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL2_NAME : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL3_NAME : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 ? CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL4_NAME : \ + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME } } cdl_option CYGPRI_SER_TEST_TTY_DEV { display "TTY-mode serial device used for testing" flavor data - default_value { "\"/dev/tty1\"" } + default_value { CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL0 ? "\"/dev/tty0\"" : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1 ? "\"/dev/tty1\"" : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2 ? "\"/dev/tty2\"" : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3 ? "\"/dev/tty3\"" : \ + CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4 ? "\"/dev/tty4\"" : \ + "\"/dev/tty5\"" } } define_proc {
--- a/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c +++ b/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.c @@ -8,7 +8,7 @@ // ####ECOSGPLCOPYRIGHTBEGIN#### // ------------------------------------------- // This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2010 Free Software Foundation, Inc. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. // // eCos is free software; you can redistribute it and/or modify it under // the terms of the GNU General Public License as published by the Free @@ -79,10 +79,15 @@ typedef struct stm32_serial_info CYG_WORD uart; CYG_ADDRWORD base; CYG_WORD int_num; + cyg_int32 int_pri; cyg_int32 rx_pin; cyg_int32 tx_pin; cyg_int32 rts_pin; cyg_int32 cts_pin; + cyg_int32 clk_enable; +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + cyg_int32 remap; +#endif cyg_bool tx_active; @@ -102,7 +107,8 @@ static bool stm32_serial_putc_interrupt( || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \ - || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0) static bool stm32_serial_putc_polled(serial_channel *chan, unsigned char c); #endif static Cyg_ErrNo stm32_serial_lookup(struct cyg_devtab_entry **tab, @@ -113,7 +119,8 @@ static unsigned char stm32_serial_getc_i || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \ - || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0) static unsigned char stm32_serial_getc_polled(serial_channel *chan); #endif static Cyg_ErrNo stm32_serial_set_config(serial_channel *chan, cyg_uint32 key, @@ -130,7 +137,8 @@ static void stm32_serial_DSR(cyg_v || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE > 0) \ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE > 0) \ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE > 0) \ - || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE > 0) + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE > 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE > 0) static SERIAL_FUNS(stm32_serial_funs_interrupt, stm32_serial_putc_interrupt, stm32_serial_getc_interrupt, @@ -144,7 +152,8 @@ static SERIAL_FUNS(stm32_serial_funs_int || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL1) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE == 0) \ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL2) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE == 0) \ || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL3) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE == 0) \ - || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL4) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE == 0) \ + || (defined(CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5) && CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE == 0) static SERIAL_FUNS(stm32_serial_funs_polled, stm32_serial_putc_polled, stm32_serial_getc_polled, @@ -161,10 +170,15 @@ static stm32_serial_info stm32_serial_in uart : 0, base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART1, int_num : CYGNUM_HAL_INTERRUPT_UART1, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_INT_PRI, rx_pin : CYGHWR_HAL_STM32_UART1_RX, tx_pin : CYGHWR_HAL_STM32_UART1_TX, rts_pin : CYGHWR_HAL_STM32_UART1_RTS, cts_pin : CYGHWR_HAL_STM32_UART1_CTS, + clk_enable : CYGHWR_HAL_STM32_UART1_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART1_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART1_REMAP_CONFIG, +#endif }; #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL0_BUFSIZE > 0 @@ -211,10 +225,15 @@ static stm32_serial_info stm32_serial_in uart : 1, base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART2, int_num : CYGNUM_HAL_INTERRUPT_UART2, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_INT_PRI, rx_pin : CYGHWR_HAL_STM32_UART2_RX, tx_pin : CYGHWR_HAL_STM32_UART2_TX, rts_pin : CYGHWR_HAL_STM32_UART2_RTS, cts_pin : CYGHWR_HAL_STM32_UART2_CTS, + clk_enable : CYGHWR_HAL_STM32_UART2_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART2_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART2_REMAP_CONFIG, +#endif }; #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL1_BUFSIZE > 0 @@ -261,10 +280,15 @@ static stm32_serial_info stm32_serial_in uart : 2, base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART3, int_num : CYGNUM_HAL_INTERRUPT_UART3, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_INT_PRI, rx_pin : CYGHWR_HAL_STM32_UART3_RX, tx_pin : CYGHWR_HAL_STM32_UART3_TX, rts_pin : CYGHWR_HAL_STM32_UART3_RTS, cts_pin : CYGHWR_HAL_STM32_UART3_CTS, + clk_enable : CYGHWR_HAL_STM32_UART3_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART3_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART3_REMAP_CONFIG, +#endif }; #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL2_BUFSIZE > 0 @@ -311,10 +335,15 @@ static stm32_serial_info stm32_serial_in uart : 3, base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART4, int_num : CYGNUM_HAL_INTERRUPT_UART4, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_INT_PRI, rx_pin : CYGHWR_HAL_STM32_UART4_RX, tx_pin : CYGHWR_HAL_STM32_UART4_TX, rts_pin : CYGHWR_HAL_STM32_UART4_RTS, cts_pin : CYGHWR_HAL_STM32_UART4_CTS, + clk_enable : CYGHWR_HAL_STM32_UART4_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART4_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART4_REMAP_CONFIG, +#endif }; #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL3_BUFSIZE > 0 @@ -361,10 +390,15 @@ static stm32_serial_info stm32_serial_in uart : 4, base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART5, int_num : CYGNUM_HAL_INTERRUPT_UART5, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_INT_PRI, rx_pin : CYGHWR_HAL_STM32_UART5_RX, tx_pin : CYGHWR_HAL_STM32_UART5_TX, rts_pin : CYGHWR_HAL_STM32_UART5_RTS, cts_pin : CYGHWR_HAL_STM32_UART5_CTS, + clk_enable : CYGHWR_HAL_STM32_UART5_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART5_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART5_REMAP_CONFIG, +#endif }; #if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL4_BUFSIZE > 0 @@ -406,6 +440,62 @@ DEVTAB_ENTRY(stm32_serial_io4, //========================================================================== + +#ifdef CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5 +static stm32_serial_info stm32_serial_info5 = { + uart : 5, + base : (CYG_ADDRWORD) CYGHWR_HAL_STM32_UART6, + int_num : CYGNUM_HAL_INTERRUPT_UART6, + int_pri : CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_INT_PRI, + rx_pin : CYGHWR_HAL_STM32_UART6_RX, + tx_pin : CYGHWR_HAL_STM32_UART6_TX, + rts_pin : CYGHWR_HAL_STM32_UART6_RTS, + cts_pin : CYGHWR_HAL_STM32_UART6_CTS, + clk_enable : CYGHWR_HAL_STM32_UART6_CLOCK, +#ifdef CYGHWR_HAL_STM32_UART6_REMAP_CONFIG + remap : CYGHWR_HAL_STM32_UART6_REMAP_CONFIG, +#endif +}; + +#if CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE > 0 +static unsigned char stm32_serial_out_buf5[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE]; +static unsigned char stm32_serial_in_buf5[CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(stm32_serial_channel5, + stm32_serial_funs_interrupt, + stm32_serial_info5, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &stm32_serial_out_buf5[0], sizeof(stm32_serial_out_buf5), + &stm32_serial_in_buf5[0], sizeof(stm32_serial_in_buf5) + ); +#else +static SERIAL_CHANNEL(stm32_serial_channel5, + stm32_serial_funs_polled, + stm32_serial_info5, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_CORTEXM_STM32_SERIAL5_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(stm32_serial_io5, + CYGDAT_IO_SERIAL_CORTEXM_STM32_SERIAL5_NAME, + 0, // Does not depend on a lower level interface + &cyg_io_serial_devio, + stm32_serial_init, + stm32_serial_lookup, // Serial driver may need initializing + &stm32_serial_channel5 + ); +#endif // CYGPKG_IO_SERIAL_CORTEXM_STM32_SERIAL5 + + +//========================================================================== // Internal function to actually configure the hardware to desired baud // rate, etc. @@ -417,7 +507,7 @@ stm32_serial_config_port(serial_channel cyg_uint32 parity = select_parity[new_config->parity]; cyg_uint32 word_length = ((new_config->word_length == CYGNUM_SERIAL_WORD_LENGTH_8) && (new_config->parity != CYGNUM_SERIAL_PARITY_NONE)) ? - CYGHWR_HAL_STM32_UART_CR1_M_9 : CYGHWR_HAL_STM32_UART_CR1_M_8; + CYGHWR_HAL_STM32_UART_CR1_M_9 : select_word_length[new_config->word_length-CYGNUM_SERIAL_WORD_LENGTH_5]; cyg_uint32 stop_bits = select_stop_bits[new_config->stop]; cyg_uint32 cr1 = 0; cyg_uint32 cr2 = 0; @@ -432,6 +522,22 @@ stm32_serial_config_port(serial_channel CYGHWR_HAL_STM32_GPIO_SET( stm32_chan->rts_pin ); CYGHWR_HAL_STM32_GPIO_SET( stm32_chan->cts_pin ); + // Enable clock + CYGHWR_HAL_STM32_CLOCK_ENABLE( stm32_chan->clk_enable ); + + // Handle any pin remapping +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + if( stm32_chan->remap != 0 ) + { + CYG_ADDRESS afio = CYGHWR_HAL_STM32_AFIO; + cyg_uint32 mapr; + CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_AFIO_CLOCK ); + HAL_READ_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr ); + mapr |= stm32_chan->remap; + HAL_WRITE_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr ); + } +#endif + // Select line parameters cr1 |= parity|word_length; cr2 |= stop_bits; @@ -490,7 +596,7 @@ stm32_serial_init(struct cyg_devtab_entr (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices if (chan->out_cbuf.len != 0) { cyg_drv_interrupt_create(stm32_chan->int_num, - 0x80, + stm32_chan->int_pri, (cyg_addrword_t)chan, stm32_serial_ISR, stm32_serial_DSR,
--- a/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h +++ b/packages/devs/serial/cortexm/stm32/current/src/stm32_serial.h @@ -54,6 +54,16 @@ #include <cyg/hal/hal_io.h> // Register definitions // ==================================================================== +// Translate system word length selector into local values. + +static cyg_uint32 select_word_length[] = { + 0, + 0, + 0, + CYGHWR_HAL_STM32_UART_CR1_M_8 +}; + +// ==================================================================== // Translate system stop bit selector into control register bits. static cyg_uint32 select_stop_bits[] = {