Mercurial > ecos
changeset 3145:ed053d86fcd2
Update STM3210e port to match new STM32 variant HAL definitions.
| author | jlarmour |
|---|---|
| date | Sun, 01 Apr 2012 02:07:35 +0000 |
| parents | a9a10d06a94b |
| children | ce7ee640986b |
| files | packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c |
| diffstat | 7 files changed, 243 insertions(+), 43 deletions(-) [+] |
line wrap: on
line diff
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog @@ -1,9 +1,58 @@ +2012-03-23 James Smith <jsmith@ecoscentric.com> + + * include/plf_io.h: Update GPIO pin definitions to use new PIN + wrapper macros. Update to use common SPEED_SPI name for SPI pin + speed selection. + +2012-02-29 James Smith <jsmith@ecoscentric.com> + + * src/stm3210e_eval_flash.c: Flash structure needs to be "const" + to match header. + +2012-01-12 Nick Garnett <nickg@ecoscentric.com> + + * include/plf_io.h: Add SPI and I2C pin and DMA definitions. + +2011-12-20 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Just set a requires on + RedBoot's number of memory segments to be 2 rather than using a + non-configurable option. + +2011-12-08 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Indicate to new STM32 variant + HAL CDL that this is an F103ZE processor. + +2011-01-27 Nick Garnett <nickg@ecoscentric.com> + + * misc/redboot_JTAG.ecm: + * misc/redboot_ROM.ecm: Define CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES + to take on-chip flash out of FIS control. + +2011-01-01 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl + (CYGHWR_HAL_CORTEXM_STM32_FLASH): Should be on by default if generic flash + active in configuration. + 2010-08-29 John Dallaway <john@dallaway.org.uk> * misc/redboot_JTAG.ecm, misc/redbooot_ROM.ecm: Inhibit the FIS directory entry for RedBoot and management of the internal flash. Issues reported by Carlo Caione. +2009-11-09 Ross Younger <wry@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Add + CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_{ADD,REMOVE}, + default to -Werror. + +2009-07-02 Nick Garnett <nickg@ecoscentric.com> + + * src/stm3210e_eval_misc.c (hal_system_init): Adjust clock enables + in line with changes to bit definitions. + 2009-02-04 Nick Garnett <nickg@ecoscentric.com> * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi: @@ -37,6 +86,18 @@ 2008-11-19 Nick Garnett <nickg@ecoscen * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi (hal_startup_stack): Adjust initial stack to top of external SRAM. +2008-10-28 Nick Garnett <nickg@ecoscentric.com> + + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h: Adjust top of + RAM to 1MB. + 2008-10-10 Nick Garnett <nickg@ecoscentric.com> * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi:
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl @@ -8,7 +8,7 @@ ## ####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 2008 Free Software Foundation, Inc. +## Copyright (C) 2008 Free Software Foundation, Inc. ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free @@ -49,6 +49,8 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL { display "ST STM3210E EVAL Development Board HAL" parent CYGPKG_HAL_CORTEXM_STM32 + requires { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" } + requires { CYGHWR_HAL_CORTEXM_STM32_F1 == "F103ZE" } define_header hal_cortexm_stm32_stm3210e_eval.h include_dir cyg/hal hardware @@ -89,11 +91,11 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM display "Memory layout" flavor data no_define - calculated { (CYG_HAL_STARTUP == "RAM" ) ? "cortexm_stm3210e_eval_ram" : - (CYG_HAL_STARTUP == "SRAM") ? "cortexm_stm3210e_eval_sram" : - (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm3210e_eval_rom" : - (CYG_HAL_STARTUP == "JTAG") ? "cortexm_stm3210e_eval_jtag" : - "undefined" } + calculated { (CYG_HAL_STARTUP == "RAM" ) ? "cortexm_stm3210e_eval_ram" : + (CYG_HAL_STARTUP == "SRAM" ) ? "cortexm_stm3210e_eval_sram" : + (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm3210e_eval_rom" : + (CYG_HAL_STARTUP == "JTAG" ) ? "cortexm_stm3210e_eval_jtag" : + "undefined" } cdl_option CYGHWR_MEMORY_LAYOUT_LDI { display "Memory layout linker script fragment" @@ -121,13 +123,26 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM description "Main clock input." } - cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH { - display "External NOR flash support" + cdl_component CYGHWR_HAL_CORTEXM_STM32_FLASH { + display "Flash support" parent CYGPKG_IO_FLASH active_if CYGPKG_IO_FLASH - flavor none compile -library=libextras.a stm3210e_eval_flash.c - description "This option enables support for the external NOR flash device." + default_value 1 + description "Control flash device support for STM3210E-EVAL board." + + cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL { + display "Internal flash support" + default_value 1 + description "This option enables support for the internal flash device." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR { + display "External NOR flash support" + default_value 1 + description "This option enables support for the external NOR flash device." + } + } # Both UARTs 0 and 1 are available for diagnostic/debug use. @@ -175,6 +190,12 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM description " This option controls the default baud rate used for the console connection. + RedBoot usess polling to transfer data over this port and + might not be able to keep up with baud rates above the + default, particularly when doing XYZmodem downloads. The + interrupt-driven device driver is able to handle these + baud rates, so any high speed application transfers should + use that instead. Note: this should match the value chosen for the GDB port if the diagnostic and GDB port are the same." } @@ -187,11 +208,16 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM description " This option controls the default baud rate used for the GDB connection. + RedBoot usess polling to transfer data over this port and + might not be able to keep up with baud rates above the + default, particularly when doing XYZmodem downloads. The + interrupt-driven device driver is able to handle these + baud rates, so any high speed application transfers should + use that instead. Note: this should match the value chosen for the console port if the console and GDB port are the same." } - cdl_component CYGBLD_GLOBAL_OPTIONS { display "Global build options" flavor none @@ -233,6 +259,36 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM } } + cdl_component CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_OPTIONS { + display "stm3210e HAL build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this HAL." + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-Werror" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are used + in addition to the set of global flags." + } + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are + removed from the set of global flags if + present." + } + } + cdl_option CYGSEM_HAL_ROM_MONITOR { display "Behave as a ROM monitor" flavor bool @@ -280,15 +336,7 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM configuration." requires { CYGNUM_REDBOOT_FLASH_BASE == 0x64000000 } - - cdl_option CYGPRI_HAL_STM3210E_EVAL_MEM_SEGMENTS { - display "Set RedBoot memory segments" - requires { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 3 } - no_define - calculated 2 - description "This CDL option is used to inform RedBoot of the - number of RAM memory segments on this platform." - } + requires { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 2 } cdl_option CYGBLD_BUILD_REDBOOT_BIN { display "Build Redboot ROM binary images" @@ -327,5 +375,4 @@ cdl_package CYGPKG_HAL_CORTEXM_STM32_STM build process to be converted to S-Record and binary files." } - }
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h @@ -71,6 +71,84 @@ #define HAL_AM29XXXXX_UNCACHED_ADDRESS(__addr) (__addr) +//============================================================================= +// I2C busses and devices + +# define HAL_I2C_EXPORTED_DEVICES \ + __externC cyg_i2c_bus hal_stm32_i2c_bus1; \ + __externC cyg_i2c_device hal_stm32_i2c_temperature; + + +//============================================================================= +// I2C bus pin configurations + +#if defined(CYGHWR_HAL_STM32_I2C1_REMAP) +#define CYGHWR_HAL_STM32_I2C1_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 8, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C1_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 9, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#else +#define CYGHWR_HAL_STM32_I2C1_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 6, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C1_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 7, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#endif + +#define CYGHWR_HAL_STM32_I2C1_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 6, 0, M2P ) +#define CYGHWR_HAL_STM32_I2C1_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 7, 0, P2M ) + + +#define CYGHWR_HAL_STM32_I2C2_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C2_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, NA, OPENDRAIN, NA, AT_LEAST(50) ) + +#define CYGHWR_HAL_STM32_I2C2_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 4, 0, M2P ) +#define CYGHWR_HAL_STM32_I2C2_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 5, 0, P2M ) + +//============================================================================= +// SPI bus pin configurations + +// NOTE: The SPEED_SPI manifest is declared by the device driver +// (e.g. "devs/spi/cortexm/stm32/<vsn>/src/spi_stm32.c") and is not +// currently defined in a header. + +#ifndef CYGHWR_HAL_STM32_SPI1_REMAP +#define CYGHWR_HAL_STM32_SPI1_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 5, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 6, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI1_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 7, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG 0 +#else +#define CYGHWR_HAL_STM32_SPI1_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 3, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 4, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI1_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP +#endif + +#define CYGHWR_HAL_STM32_SPI1_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 3, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI1_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 2, 0, P2M ) + + +#define CYGHWR_HAL_STM32_SPI2_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 13, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI2_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 14, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI2_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 15, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG 0 + +#define CYGHWR_HAL_STM32_SPI2_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 5, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI2_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 4, 0, P2M ) + + + +#ifndef CYGHWR_HAL_STM32_SPI3_REMAP +#define CYGHWR_HAL_STM32_SPI3_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 3, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 4, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI3_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG 0 +#else +#define CYGHWR_HAL_STM32_SPI3_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 11, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI3_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_SPI3_RMP +#endif + +#define CYGHWR_HAL_STM32_SPI3_DMA_TX CYGHWR_HAL_STM32_DMA( 2, 2, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI3_DMA_RX CYGHWR_HAL_STM32_DMA( 2, 1, 0, P2M ) + + //----------------------------------------------------------------------------- // end of plf_io.h #endif // CYGONCE_HAL_PLF_IO_H
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm @@ -59,7 +59,7 @@ cdl_option CYGSEM_REDBOOT_FLASH_COMBINED }; cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { - user_value 0 + user_value 0 }; cdl_option CYGOPT_REDBOOT_FIS_REDBOOT { @@ -70,10 +70,6 @@ cdl_component CYGOPT_REDBOOT_FIS_REDBOOT user_value 0 }; -cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES { - user_value 1 0x08000000 -}; - cdl_option CYGBLD_ISO_STRTOK_R_HEADER { inferred_value 1 <cyg/libc/string/string.h> }; @@ -95,3 +91,9 @@ cdl_option CYGBLD_ISO_STRING_STRFUNCS_HE }; +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES { + user_value 1 "0x08000000" +}; + + +
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm @@ -59,7 +59,7 @@ cdl_option CYGSEM_REDBOOT_FLASH_COMBINED }; cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { - user_value 0 + user_value 0 }; cdl_option CYGOPT_REDBOOT_FIS_REDBOOT { @@ -70,10 +70,6 @@ cdl_component CYGOPT_REDBOOT_FIS_REDBOOT user_value 0 }; -cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES { - user_value 1 0x08000000 -}; - cdl_option CYGBLD_ISO_STRTOK_R_HEADER { inferred_value 1 <cyg/libc/string/string.h> }; @@ -95,3 +91,8 @@ cdl_option CYGBLD_ISO_STRING_STRFUNCS_HE }; +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES { + user_value 1 "0x08000000" +}; + +
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c @@ -60,12 +60,13 @@ #include <cyg/hal/hal_io.h> +#ifdef CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL //-------------------------------------------------------------------------- // Internal flash #include <cyg/io/stm32_flash.h> -cyg_stm32_flash_dev hal_stm32_flash_priv; +const cyg_stm32_flash_dev hal_stm32_flash_priv; CYG_FLASH_DRIVER(hal_stm32_flash, &cyg_stm32_flash_funs, @@ -77,6 +78,9 @@ CYG_FLASH_DRIVER(hal_stm32_flash, &hal_stm32_flash_priv ); +#endif // CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL + +#ifdef CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR //-------------------------------------------------------------------------- // There is a Spansion S29GL128P90FFIR20 or a NUMONYX equivalent. // These are AMD compatible and with CFI can all be handled by the AMD @@ -105,5 +109,7 @@ CYG_FLASH_DRIVER(hal_stm3210e_flash, hal_stm3210e_flash_priv.block_info, &hal_stm3210e_flash_priv); +#endif // CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR + //-------------------------------------------------------------------------- // EOF stm3210e_eval_flash.c
--- a/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c +++ b/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c @@ -76,25 +76,25 @@ { CYG_ADDRESS base; -#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_SRAM) +#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM) // Enable peripheral clocks in RCC base = CYGHWR_HAL_STM32_RCC; HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHBENR, - CYGHWR_HAL_STM32_RCC_AHBENR_FSMC | - CYGHWR_HAL_STM32_RCC_AHBENR_FLITF| - CYGHWR_HAL_STM32_RCC_AHBENR_SRAM ); + BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FSMC) | + BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FLITF) | + BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_SRAM) ); HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB2ENR, - CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA | - CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB | - CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC | - CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD | - CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE | - CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF | - CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG ); + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG) ); // Set all unused GPIO lines to input with pull down to prevent // them floating and annoying any external hardware. @@ -237,6 +237,11 @@ cyg_plf_memory_segment(int seg, unsigned *start = (unsigned char *)CYGMEM_REGION_sram; *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); break; +#elif defined(CYGMEM_REGION_xram) + case 1: + *start = (unsigned char *)CYGMEM_REGION_xram; + *end = (unsigned char *)(CYGMEM_REGION_xram + CYGMEM_REGION_xram_SIZE); + break; #endif default: *start = *end = NO_MEMORY;