flash_v2: packages/hal/mn10300/arch/current/include/hal

annotate packages/hal/mn10300/arch/current/include/hal_cache.h @ 14:01ce82f3e11a ecos-sw-1999-06-11

Merge from eCos master repository on 1999-06-11-17:05:41-BST

author	jlarmour
date	Fri, 11 Jun 1999 09:36:56 +0000
parents	1d7f19c9e4d1
children	641b639be825

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // hal_cache.h
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // HAL cache control API
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	11 //####COPYRIGHTBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	12 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	13 // -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	14 // The contents of this file are subject to the Cygnus eCos Public License
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	15 // Version 1.0 (the "License"); you may not use this file except in
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	16 // compliance with the License. You may obtain a copy of the License at
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	17 // http://sourceware.cygnus.com/ecos
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	18 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	19 // Software distributed under the License is distributed on an "AS IS"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	21 // License for the specific language governing rights and limitations under
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	22 // the License.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	23 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	24 // The Original Code is eCos - Embedded Cygnus Operating System, released
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	25 // September 30, 1998.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	26 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	27 // The Initial Developer of the Original Code is Cygnus. Portions created
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	29 // -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	30 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	31 //####COPYRIGHTEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	32 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	33 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	34 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	35 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	36 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	37 // Date: 1998-02-17
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	38 // Purpose: Cache control API
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	39 // Description: The macros defined here provide the HAL APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	40 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	41 // Usage:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	42 // #include <cyg/hal/hal_cache.h>
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	43 // ...
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	44 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	45 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	46 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	47 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	48 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	49
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	50 #include <pkgconf/hal.h>
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	52
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	53 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	54 // MN10300 Simulator
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	55
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	56 #if defined(CYG_HAL_MN10300_SIM)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	57
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	58 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	59 // Cache dimensions
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	60
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	61 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	62 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	63 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	64 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	65
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	66 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	67 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	68 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	69 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	70
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	71 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	72 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	73
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	74 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	75 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	76
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	77 // Enable the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	78 #define HAL_DCACHE_ENABLE()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	80 // Disable the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	81 #define HAL_DCACHE_DISABLE()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	82
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	83 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	84 #define HAL_DCACHE_INVALIDATE_ALL()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	86 // Synchronize the contents of the cache with memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	87 #define HAL_DCACHE_SYNC()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	88
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	89 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	91
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	92 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	94
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	95 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	97 //#define HAL_DCACHE_LOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	99 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	100 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	101
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	102 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	103 //#define HAL_DCACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	104
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	105 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	106 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	107
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	108 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	109 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	110 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	111
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	112 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	113 // for the given address range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	114 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	115
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	116 // Invalidate cache lines in the given range without writing to memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	117 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	118
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	119 // Write dirty cache lines to memory for the given address range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	120 //#define HAL_DCACHE_STORE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	121
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	122 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	123 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	124 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	125
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	126 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	127 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	128 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	129
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	130 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	131 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	132
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	133 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	134 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	135
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	136 // Enable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	137 #define HAL_ICACHE_ENABLE()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	138
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	139 // Disable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	140 #define HAL_ICACHE_DISABLE()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	141
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	142 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	143 #define HAL_ICACHE_INVALIDATE_ALL()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	144
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	145 // Synchronize the contents of the cache with memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	146 #define HAL_ICACHE_SYNC()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	147
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	148 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	149 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	150
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	151 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	152 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	153 //#define HAL_ICACHE_LOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	154
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	155 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	156 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	157
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	158 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	159 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	160
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	161 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	162 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	163
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	164 // Invalidate cache lines in the given range without writing to memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	165 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	166
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	167 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	168
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	169
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	170 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	171 // MN103002 implementation
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	172
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	173 #if !defined(CYG_HAL_MN10300_SIM) && defined(CYG_HAL_MN10300_MN103002)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	174
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	175 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	176 // Cache dimensions
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	177
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	178
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	179 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	180 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	181 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	182 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	183
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	184 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	185 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	186 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	187 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	188
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	189 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	190 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	191
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	192 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	193 // Control registers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	194
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	195 #define HAL_CHCTR ((volatile CYG_ADDRWORD *)0x20000070)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	196
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	197 #define HAL_CHCTR_ICEN 0x0001
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	198 #define HAL_CHCTR_DCEN 0x0002
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	199 #define HAL_CHCTR_ICBUSY 0x0004
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	200 #define HAL_CHCTR_DCBUSY 0x0008
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	201 #define HAL_CHCTR_ICINV 0x0010
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	202 #define HAL_CHCTR_DCINV 0x0020
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	203 #define HAL_CHCTR_DCWTMD 0x0040
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	204 #define HAL_CHCTR_ICWMD 0x0300
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	205 #define HAL_CHCTR_DCWMD 0x3000
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	206
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	207 #define HAL_DCACHE_PURGE_WAY0 ((volatile CYG_BYTE *)0x28400000)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	208 #define HAL_DCACHE_PURGE_WAY1 ((volatile CYG_BYTE *)0x28401000)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	209
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	210 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	211 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	212
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	213 // Enable the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	214 #define HAL_DCACHE_ENABLE() \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	215 { \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	216 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	217 chctr \|= HAL_CHCTR_DCEN; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	218 *HAL_CHCTR = chctr; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	221 // Disable the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	222 #define HAL_DCACHE_DISABLE() \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223 { \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	224 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	225 chctr &= ~HAL_CHCTR_DCEN; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	226 *HAL_CHCTR = chctr; \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	227 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	228 }
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	229
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	230 // Query the state of the data cache
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	231 #define HAL_DCACHE_IS_ENABLED(_state_) \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	232 { \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	233 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	234 _state_ = (0 != (chctr & HAL_CHCTR_DCEN)); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	235 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	236
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	237 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	238 #define HAL_DCACHE_INVALIDATE_ALL() \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	239 { \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	240 register CYG_ADDRWORD chctr; \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	241 register CYG_ADDRWORD state; \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	242 HAL_DCACHE_IS_ENABLED(state); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	243 if (state) \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	244 HAL_DCACHE_DISABLE(); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	245 chctr = *HAL_CHCTR; \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	246 chctr \|= HAL_CHCTR_DCINV; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	247 *HAL_CHCTR = chctr; \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	248 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	249 if (state) \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	250 HAL_DCACHE_ENABLE(); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	251 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	252
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	253 // Synchronize the contents of the cache with memory.
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	254 #define HAL_DCACHE_SYNC() HAL_DCACHE_STORE( 0, HAL_DCACHE_SIZE/HAL_DCACHE_WAYS )
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	255
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	256 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	257 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	258
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	259 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	260 #define HAL_DCACHE_WRITE_MODE( _mode_ ) \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	261 { \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	262 register CYG_ADDRWORD chctr; \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	263 register CYG_ADDRWORD state; \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	264 HAL_DCACHE_IS_ENABLED(state); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	265 if (state) \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	266 HAL_DCACHE_DISABLE(); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	267 chctr = *HAL_CHCTR; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	268 chctr \|= HAL_CHCTR_DCWTMD*(_mode_); \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	269 *HAL_CHCTR = chctr; \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	270 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	271 if (state) \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	272 HAL_DCACHE_ENABLE(); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	273 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	274
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	275 #define HAL_DCACHE_WRITEBACK_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	276 #define HAL_DCACHE_WRITETHRU_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	277
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	278 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	279 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	280 //#define HAL_DCACHE_LOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	281
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	282 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	283 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	284
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	285 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	286 //#define HAL_DCACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	287
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	288 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	289 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	290
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	291 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	292 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	293 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	294
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	295 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	296 // for the given address range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	297 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	298
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	299 // Invalidate cache lines in the given range without writing to memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	300 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	301
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	302 // Write dirty cache lines to memory for the given address range.
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 4 diff changeset	303
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 4 diff changeset	304 // This functionality requires 4 register variables. To prevent register
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 4 diff changeset	305 // spilling, put the code in a separate function.
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 4 diff changeset	306 externC void cyg_hal_dcache_store(CYG_ADDRWORD base, int size);
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 4 diff changeset	307
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 4 diff changeset	308 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 4 diff changeset	309 cyg_hal_dcache_store((_base_), (_size_))
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	310
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	311 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	312 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	313 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	314
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	315 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	316 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	317 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	318
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	319 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	320 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	321
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	322 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	323 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	324
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	325 // Enable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	326 #define HAL_ICACHE_ENABLE() \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	327 { \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	328 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	329 chctr \|= HAL_CHCTR_ICEN; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	330 *HAL_CHCTR = chctr; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	331 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	332
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	333 // Disable the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	334 #define HAL_ICACHE_DISABLE() \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	335 { \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	336 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	337 chctr &= ~HAL_CHCTR_ICEN; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	338 *HAL_CHCTR = chctr; \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	339 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	340 }
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	341
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	342 // Query the state of the instruction cache
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	343 #define HAL_ICACHE_IS_ENABLED(_state_) \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	344 { \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	345 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	346 _state_ = (0 != (chctr & HAL_CHCTR_ICEN)); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	347 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	348
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	349 // Invalidate the entire cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	350 #define HAL_ICACHE_INVALIDATE_ALL() \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	351 { \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	352 register CYG_ADDRWORD chctr; \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	353 register CYG_ADDRWORD state; \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	354 HAL_ICACHE_IS_ENABLED(state); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	355 if (state) \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	356 HAL_ICACHE_DISABLE(); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	357 chctr = *HAL_CHCTR; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	358 chctr \|= HAL_CHCTR_ICINV; \
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	359 *HAL_CHCTR = chctr; \
4 1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	360 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	361 if (state) \
1d7f19c9e4d1 Merge from eCos master repository on 1999-05-11-21:11:10-BST jlarmour parents: 2 diff changeset	362 HAL_ICACHE_ENABLE(); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	363 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	364
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	365 // Synchronize the contents of the cache with memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	366 #define HAL_ICACHE_SYNC()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	367
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	368 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	369 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	370
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	371 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	372 // and then lock the cache so that it stays there.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	373 //#define HAL_ICACHE_LOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	374
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	375 // Undo a previous lock operation
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	376 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	377
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	378 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	379 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	380
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	381 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	382 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	383
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	384 // Invalidate cache lines in the given range without writing to memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	385 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	386
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	387 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	388
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	389 //-----------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	390 // Check that a supported configuration has actually defined some macros.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	391
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	392 #ifndef HAL_DCACHE_ENABLE
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	393
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	394 #error Unsupported MN10300 configuration
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	395
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	396 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	397
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	398 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	399 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	400 // End of hal_cache.h

Mercurial > flash_v2

annotate packages/hal/mn10300/arch/current/include/hal_cache.h @ 14:01ce82f3e11a ecos-sw-1999-06-11