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annotate packages/devs/eth/powerpc/quicc/current/src/if_quicc.c @ 132:0ae0bc38e387 ecos-sw-2000-10-31

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Merge from eCos master repository on 2000-10-31-00:30:36-GMT
author jlarmour
date Tue, 31 Oct 2000 20:53:09 +0000
parents 6bd9d475ed4b
children d397fc472bcf
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1 //==========================================================================
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2 //
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3 // dev/if_quicc.c
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4 //
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5 // Ethernet device driver for PowerPC QUICC (MPC8xx) boards
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //####BSDCOPYRIGHTBEGIN####
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32 //
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33 // -------------------------------------------
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34 //
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35 // Portions of this software may have been derived from OpenBSD or other sources,
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36 // and are covered by the appropriate copyright disclaimers included herein.
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37 //
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38 // -------------------------------------------
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39 //
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40 //####BSDCOPYRIGHTEND####
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41 //==========================================================================
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42 //#####DESCRIPTIONBEGIN####
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43 //
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44 // Author(s): gthomas
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45 // Contributors: gthomas
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46 // Date: 2000-01-10
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47 // Purpose:
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48 // Description: hardware driver for MPC8xx QUICC
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49 //
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50 //
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51 //####DESCRIPTIONEND####
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52 //
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53 //==========================================================================
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54
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55 // Ethernet device driver for MPC8xx QUICC
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56
132
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57 #include <pkgconf/system.h>
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58 #include <pkgconf/devs_eth_powerpc_quicc.h>
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59
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60 #ifdef CYGPKG_NET
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61 #include <pkgconf/net.h>
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62 #endif
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63
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64 #include <cyg/infra/cyg_type.h>
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65 #include <cyg/infra/diag.h>
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66
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67 #include <cyg/hal/hal_arch.h>
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68 #include <cyg/hal/hal_cache.h>
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69 #include <cyg/hal/hal_intr.h>
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70 #include <cyg/hal/drv_api.h>
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71
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72 #include <netdev.h>
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73 #include <eth_drv.h>
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74
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75 #include "quicc_eth.h"
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76
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77 static unsigned char quicc_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM]
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78 [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE];
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79 static unsigned char quicc_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM]
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80 [CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE];
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81
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82 static struct quicc_eth_info quicc_eth0_info;
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83 static unsigned char enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x79, 0xB8};
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84
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85 ETH_DRV_SC(quicc_eth0_sc,
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86 &quicc_eth0_info, // Driver specific data
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87 "eth0", // Name for this interface
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88 quicc_eth_start,
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89 quicc_eth_stop,
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90 quicc_eth_control,
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91 quicc_eth_can_send,
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92 quicc_eth_send,
115
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93 quicc_eth_recv,
121
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94 quicc_eth_deliver,
117
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95 quicc_eth_int,
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96 quicc_eth_int_vector);
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97
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98 NETDEVTAB_ENTRY(quicc_netdev,
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99 "quicc_eth",
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100 quicc_eth_init,
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101 &quicc_eth0_sc);
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102
132
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103 extern int _mbx_fetch_VPD(int, void *, int);
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104
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105 static cyg_interrupt quicc_eth_interrupt;
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106 static cyg_handle_t quicc_eth_interrupt_handle;
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107 static void quicc_eth_int(struct eth_drv_sc *data);
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108
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109 // This ISR is called when the ethernet interrupt occurs
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110 static int
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111 quicc_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
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112 {
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113 cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
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114 return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
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115 }
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116
121
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117 // Deliver function (ex-DSR) handles the ethernet [logical] processing
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118 static void
121
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119 quicc_eth_deliver(struct eth_drv_sc * sc)
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120 {
121
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121 quicc_eth_int(sc);
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122 // Allow interrupts to happen again
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123 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
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124 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
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125 }
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126
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127 //
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128 // Initialize the interface - performed at system startup
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129 // This function must set up the interface, including arranging to
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130 // handle interrupts, etc, so that it may be "started" cheaply later.
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131 //
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132 static bool
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133 quicc_eth_init(struct cyg_netdevtab_entry *tab)
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134 {
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135 struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
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136 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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137 volatile EPPC *eppc = (volatile EPPC *)eppc_base();
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138 struct cp_bufdesc *rxbd, *txbd;
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139 unsigned char *RxBUF, *TxBUF, *ep, *ap;
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140 volatile struct ethernet_pram *enet_pram;
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141 volatile struct scc_regs *scc;
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142 int TxBD, RxBD;
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143 int cache_state;
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144 int i;
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145
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146 // Fetch the board address from the VPD
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147 #define VPD_ETHERNET_ADDRESS 0x08
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148 _mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr));
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149
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150 // Ensure consistent state between cache and what the QUICC sees
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151 HAL_DCACHE_IS_ENABLED(cache_state);
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152 HAL_DCACHE_SYNC();
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153 HAL_DCACHE_DISABLE();
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154
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155 // Set up to handle interrupts
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156 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_CPM_SCC1,
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157 CYGARC_SIU_PRIORITY_HIGH,
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158 (cyg_addrword_t)sc, // Data item passed to interrupt handler
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159 (cyg_ISR_t *)quicc_eth_isr,
121
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160 (cyg_DSR_t *)eth_drv_dsr,
82
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161 &quicc_eth_interrupt_handle,
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162 &quicc_eth_interrupt);
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163 cyg_drv_interrupt_attach(quicc_eth_interrupt_handle);
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164 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
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165 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_CPM_SCC1);
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166
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167 qi->pram = enet_pram = &eppc->pram[0].enet_scc;
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168 qi->ctl = scc = &eppc->scc_regs[0]; // Use SCC1
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169
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170 // Shut down ethernet, in case it is already running
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171 scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT);
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172
132
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173 memset((void *)enet_pram, 0, sizeof(*enet_pram));
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174
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175 TxBD = 0x2C00; // FIXME
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176 RxBD = TxBD + CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc);
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177
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178 txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
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179 rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
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180 qi->tbase = txbd;
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181 qi->txbd = txbd;
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182 qi->tnext = txbd;
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183 qi->rbase = rxbd;
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184 qi->rxbd = rxbd;
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185 qi->rnext = rxbd;
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186
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187 RxBUF = &quicc_eth_rxbufs[0][0];
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188 TxBUF = &quicc_eth_txbufs[0][0];
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189
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190 // setup buffer descriptors
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191 for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM; i++) {
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192 rxbd->length = 0;
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193 rxbd->buffer = RxBUF;
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194 rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
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195 RxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
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196 rxbd++;
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197 }
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198 rxbd--;
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199 rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
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200 for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM; i++) {
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201 txbd->length = 0;
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202 txbd->buffer = TxBUF;
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203 txbd->ctrl = 0;
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204 TxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
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205 txbd++;
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206 }
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207 txbd--;
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208 txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
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209
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210 // Set up parallel ports for connection to MC68160 ethernet tranceiver
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211 eppc->pio_papar |= (QUICC_MBX_PA_RXD | QUICC_MBX_PA_TXD);
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212 eppc->pio_padir &= ~(QUICC_MBX_PA_RXD | QUICC_MBX_PA_TXD);
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213 eppc->pio_paodr &= ~QUICC_MBX_PA_TXD;
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214
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215 eppc->pio_pcpar &= ~(QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
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216 eppc->pio_pcdir &= ~(QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
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217 eppc->pio_pcso |= (QUICC_MBX_PC_COLLISION | QUICC_MBX_PC_Rx_ENABLE);
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218
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219 eppc->pio_papar |= (QUICC_MBX_PA_Tx_CLOCK | QUICC_MBX_PA_Rx_CLOCK);
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220 eppc->pio_padir &= ~(QUICC_MBX_PA_Tx_CLOCK | QUICC_MBX_PA_Rx_CLOCK);
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221
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222 // Set up clock routing
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223 eppc->si_sicr &= ~QUICC_MBX_SICR_MASK;
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224 eppc->si_sicr |= QUICC_MBX_SICR_ENET;
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225 eppc->si_sicr &= ~QUICC_MBX_SICR_SCC1_ENABLE;
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226
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227 // Set up DMA mode
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228 eppc->dma_sdcr = 0x0001;
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229
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230 // Initialize shared PRAM
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231 enet_pram->rbase = RxBD;
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232 enet_pram->tbase = TxBD;
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233
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234 // Set Big Endian mode
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235 enet_pram->rfcr = QUICC_SCC_FCR_BE;
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236 enet_pram->tfcr = QUICC_SCC_FCR_BE;
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237
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238 // Size of receive buffers
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239 enet_pram->mrblr = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
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240
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241 // Initialize CRC calculations
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242 enet_pram->c_pres = 0xFFFFFFFF;
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243 enet_pram->c_mask = 0xDEBB20E3; // Actual CRC formula
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244 enet_pram->crcec = 0;
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245 enet_pram->alec = 0;
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246 enet_pram->disfc = 0;
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247
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248 // Frame padding
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249 enet_pram->pads = 0x8888;
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250 enet_pram->pads = 0x0000;
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251
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252 // Retries
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253 enet_pram->ret_lim = 15;
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254 enet_pram->ret_cnt = 0;
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255
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256 // Frame sizes
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257 enet_pram->mflr = IEEE_8023_MAX_FRAME;
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258 enet_pram->minflr = IEEE_8023_MIN_FRAME;
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259 enet_pram->maxd1 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
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260 enet_pram->maxd2 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
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261
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262 // Group address hash
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263 enet_pram->gaddr1 = 0;
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264 enet_pram->gaddr2 = 0;
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265 enet_pram->gaddr3 = 0;
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266 enet_pram->gaddr4 = 0;
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267
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268 // Device physical address
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269 ep = &enaddr[sizeof(enaddr)];
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270 ap = (unsigned char *)&enet_pram->paddr_h;
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271 for (i = 0; i < sizeof(enaddr); i++) {
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272 *ap++ = *--ep;
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273 }
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274
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275 // Persistence counter
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276 enet_pram->p_per = 0;
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277
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278 // Individual address filter
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279 enet_pram->iaddr1 = 0;
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280 enet_pram->iaddr2 = 0;
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281 enet_pram->iaddr3 = 0;
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282 enet_pram->iaddr4 = 0;
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283
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284 // Temp address
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285 enet_pram->taddr_h = 0;
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286 enet_pram->taddr_m = 0;
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287 enet_pram->taddr_l = 0;
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288
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289 // Initialize the CPM (set up buffer pointers, etc).
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290 eppc->cp_cr = QUICC_CPM_SCC1 | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
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291 while (eppc->cp_cr & QUICC_CPM_CR_BUSY) ;
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292
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293 // Clear any pending interrupt/exceptions
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294 scc->scc_scce = 0xFFFF;
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295
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296 // Enable interrupts
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297 scc->scc_sccm = QUICC_SCCE_INTS;
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298
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299 // Set up SCC1 to run in ethernet mode
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300 scc->scc_gsmr_h = 0;
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301 scc->scc_gsmr_l = QUICC_SCC_GSML_TCI | QUICC_SCC_GSML_TPL_48 |
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302 QUICC_SCC_GSML_TPP_01 | QUICC_SCC_GSML_MODE_ENET;
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303
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304 // Sync delimiters
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305 scc->scc_dsr = 0xD555;
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306
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307 // Protocol specifics (as if GSML wasn't enough)
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308 scc->scc_psmr = QUICC_PMSR_ENET_CRC | QUICC_PMSR_SEARCH_AFTER_22 |
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309 QUICC_PMSR_RCV_SHORT_FRAMES;
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310
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311 // Configure board interface
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312 *MBX_CTL1 = MBX_CTL1_ETEN | MBX_CTL1_TPEN; // Enable ethernet, TP mode
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313
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314 // Enable ethernet interface
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315 eppc->pio_pcpar |= QUICC_MBX_PC_Tx_ENABLE;
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316 eppc->pio_pcdir &= ~QUICC_MBX_PC_Tx_ENABLE;
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317
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318 if (cache_state)
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319 HAL_DCACHE_ENABLE();
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320
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321 // Initialize upper level driver
115
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322 (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
82
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323
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324 return true;
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325 }
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326
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327 //
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328 // This function is called to shut down the interface.
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329 //
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330 static void
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331 quicc_eth_stop(struct eth_drv_sc *sc)
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332 {
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333 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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334 volatile struct scc_regs *scc = qi->ctl;
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335 // Disable the device!
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336 scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT);
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337 }
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338
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339 //
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340 // This function is called to "start up" the interface. It may be called
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341 // multiple times, even when the hardware is already running. It will be
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342 // called whenever something "hardware oriented" changes and should leave
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343 // the hardware ready to send/receive packets.
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344 //
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345 static void
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346 quicc_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
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347 {
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348 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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349 volatile struct scc_regs *scc = qi->ctl;
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350 // Enable the device!
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351 scc->scc_gsmr_l |= QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT;
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352 }
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353
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354 //
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355 // This function is called for low level "control" operations
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356 //
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357 static int
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358 quicc_eth_control(struct eth_drv_sc *sc, unsigned long key,
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359 void *data, int length)
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360 {
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361 switch (key) {
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362 case ETH_DRV_SET_MAC_ADDRESS:
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363 return 0;
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364 break;
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365 default:
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366 return 1;
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367 break;
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368 }
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369 }
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370
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371 //
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372 // This function is called to see if another packet can be sent.
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373 // It should return the number of packets which can be handled.
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374 // Zero should be returned if the interface is busy and can not send any more.
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375 //
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376 static int
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377 quicc_eth_can_send(struct eth_drv_sc *sc)
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378 {
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379 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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380 volatile struct cp_bufdesc *txbd = qi->txbd;
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381 return ((txbd->ctrl & QUICC_BD_CTL_Ready) == 0);
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382 }
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383
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384 //
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385 // This routine is called to send data to the hardware.
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386 static void
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387 quicc_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
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388 int total_len, unsigned long key)
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389 {
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390 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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391 volatile struct cp_bufdesc *txbd, *txfirst;
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392 volatile char *bp;
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393 int i, txindex, cache_state;
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394 // Find a free buffer
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395 txbd = txfirst = qi->txbd;
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396 while (txbd->ctrl & QUICC_BD_CTL_Ready) {
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397 // This buffer is busy, move to next one
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398 if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
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399 txbd = qi->tbase;
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400 } else {
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401 txbd++;
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402 }
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403 if (txbd == txfirst) {
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404 #ifdef CYGPKG_NET
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405 panic ("No free xmit buffers");
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406 #else
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407 printf("QUICC Ethernet: No free xmit buffers\n");
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408 #endif
82
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409 }
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410 }
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411 // Remember the next buffer to try
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412 if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
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413 qi->txbd = qi->tbase;
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414 } else {
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415 qi->txbd = txbd+1;
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416 }
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417 txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
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418 qi->txkey[txindex] = key;
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419 // Set up buffer
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420 txbd->length = total_len;
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421 bp = txbd->buffer;
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422 for (i = 0; i < sg_len; i++) {
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423 memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len);
82
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424 bp += sg_list[i].len;
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425 }
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426 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
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427 HAL_DCACHE_IS_ENABLED(cache_state);
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428 if (cache_state) {
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429 HAL_DCACHE_INVALIDATE(txbd->buffer, txbd->length); // Make sure no stale data
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430 }
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431 // Send it on it's way
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432 txbd->ctrl |= QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int |
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433 QUICC_BD_TX_PAD | QUICC_BD_TX_LAST | QUICC_BD_TX_TC;
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434 }
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435
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436 //
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437 // This function is called when a packet has been received. It's job is
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438 // to prepare to unload the packet from the hardware. Once the length of
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439 // the packet is known, the upper layer of the driver can be told. When
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440 // the upper layer is ready to unload the packet, the internal function
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441 // 'quicc_eth_recv' will be called to actually fetch it from the hardware.
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442 //
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443 static void
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444 quicc_eth_RxEvent(struct eth_drv_sc *sc)
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445 {
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446 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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447 volatile struct cp_bufdesc *rxbd;
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448 rxbd = qi->rnext;
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449 while ((rxbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) {
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450 qi->rxbd = rxbd; // Save for callback
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451 (sc->funs->eth_drv->recv)(sc, rxbd->length);
82
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452 rxbd->ctrl |= QUICC_BD_CTL_Ready;
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453 if (rxbd->ctrl & QUICC_BD_CTL_Wrap) {
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454 rxbd = qi->rbase;
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455 } else {
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456 rxbd++;
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457 }
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458 }
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459 // Remember where we left off
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460 qi->rnext = (struct cp_bufdesc *)rxbd;
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461 }
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462
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463 //
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464 // This function is called as a result of the "eth_drv_recv()" call above.
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465 // It's job is to actually fetch data for a packet from the hardware once
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466 // memory buffers have been allocated for the packet. Note that the buffers
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467 // may come in pieces, using a scatter-gather list. This allows for more
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468 // efficient processing in the upper layers of the stack.
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469 //
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470 static void
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471 quicc_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
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472 {
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473 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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474 unsigned char *bp;
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475 int i, cache_state;
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476 bp = (unsigned char *)qi->rxbd->buffer;
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477 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
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478 HAL_DCACHE_IS_ENABLED(cache_state);
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479 if (cache_state) {
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480 HAL_DCACHE_INVALIDATE(qi->rxbd->buffer, qi->rxbd->length); // Make sure no stale data
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481 }
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482 for (i = 0; i < sg_len; i++) {
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483 if (sg_list[i].buf != 0) {
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484 memcpy((void *)sg_list[i].buf, bp, sg_list[i].len);
82
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485 bp += sg_list[i].len;
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486 }
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487 }
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488 }
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489
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490 static void
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491 quicc_eth_TxEvent(struct eth_drv_sc *sc, int stat)
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492 {
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493 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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494 volatile struct cp_bufdesc *txbd;
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495 int txindex;
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496 txbd = qi->tnext;
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497 while ((txbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) {
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498 txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
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499 txbd->ctrl &= ~QUICC_BD_CTL_Int; // Reset int pending bit
115
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500 (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0);
82
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501 if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
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502 txbd = qi->tbase;
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503 } else {
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504 txbd++;
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505 }
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506 }
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507 // Remember where we left off
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508 qi->tnext = (struct cp_bufdesc *)txbd;
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509 }
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510
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511 //
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512 // Interrupt processing
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513 //
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514 static void
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515 quicc_eth_int(struct eth_drv_sc *sc)
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516 {
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517 struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
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518 volatile struct scc_regs *scc = qi->ctl;
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519 unsigned short scce;
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520 while ((scce = (scc->scc_scce & QUICC_SCCE_INTS)) != 0) {
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521 if ((scce & (QUICC_SCCE_TXE | QUICC_SCCE_TX)) != 0) {
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522 quicc_eth_TxEvent(sc, scce);
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523 }
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524 if ((scce & QUICC_SCCE_RXF) != 0) {
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525 quicc_eth_RxEvent(sc);
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526 }
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527 scc->scc_scce = scce; // Reset the bits we handled
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528 }
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529 }
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530
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531 //
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532 // Interrupt vector
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533 //
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534 static int
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535 quicc_eth_int_vector(struct eth_drv_sc *sc)
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536 {
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537 return (CYGNUM_HAL_INTERRUPT_CPM_SCC1);
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538 }