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1 //============================================================================= |
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2 // |
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3 // hal_diag.c |
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4 // |
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5 // HAL diagnostic I/O code |
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6 // |
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7 //============================================================================= |
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8 //####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
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12 // Copyright (C) 2002 Gary Thomas |
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13 // |
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14 // eCos is free software; you can redistribute it and/or modify it under |
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15 // the terms of the GNU General Public License as published by the Free |
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16 // Software Foundation; either version 2 or (at your option) any later version. |
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17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
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22 // |
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23 // You should have received a copy of the GNU General Public License along |
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24 // with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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26 // |
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27 // As a special exception, if other files instantiate templates or use macros |
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28 // or inline functions from this file, or you compile this file and link it |
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29 // with other works to produce a work based on this file, this file does not |
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30 // by itself cause the resulting work to be covered by the GNU General Public |
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31 // License. However the source code for this file must still be made available |
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32 // in accordance with section (3) of the GNU General Public License. |
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33 // |
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34 // This exception does not invalidate any other reasons why a work based on |
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35 // this file might be covered by the GNU General Public License. |
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36 // |
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37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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38 // at http://sources.redhat.com/ecos/ecos-license/ |
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39 // ------------------------------------------- |
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40 //####ECOSGPLCOPYRIGHTEND#### |
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41 //============================================================================= |
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42 //#####DESCRIPTIONBEGIN#### |
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43 // |
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44 // Author(s): hmt |
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45 // Contributors:hmt, gthomas |
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46 // Date: 1999-06-08 |
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47 // Purpose: HAL diagnostic output |
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48 // Description: Implementations of HAL diagnostic I/O support. |
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49 // |
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50 //####DESCRIPTIONEND#### |
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51 // |
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52 //============================================================================= |
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53 |
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54 #include <pkgconf/hal.h> |
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55 |
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56 #include <cyg/infra/cyg_type.h> // base types |
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57 #include <cyg/infra/cyg_trac.h> // tracing macros |
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58 #include <cyg/infra/cyg_ass.h> // assertion macros |
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59 |
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60 #include <cyg/hal/hal_io.h> // IO macros |
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61 #include <cyg/hal/hal_diag.h> |
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62 #include <cyg/hal/hal_intr.h> // Interrupt macros |
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63 #include <cyg/hal/drv_api.h> |
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64 |
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65 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) |
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66 #include <cyg/hal/hal_stub.h> // hal_output_gdb_string |
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67 #endif |
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68 |
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69 #include <cyg/hal/ppc_regs.h> |
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70 |
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71 //============================================================================= |
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72 // Serial driver |
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73 //============================================================================= |
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74 |
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75 //----------------------------------------------------------------------------- |
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76 // There are two serial ports. |
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77 #define CYG_DEV_SERIAL_BASE_A 0xF0004500 // port A |
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78 #define CYG_DEV_SERIAL_BASE_B 0xF0004600 // port B |
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79 |
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80 //----------------------------------------------------------------------------- |
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81 // Default baud rate is 38400 |
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82 #define _MEMCLK (CYGHWR_HAL_POWERPC_MEM_SPEED*1000000) |
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83 #define _BAUD CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD |
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84 #define CYG_DEV_SERIAL_RS232_T1_VALUE_B38400 (((_MEMCLK/16)/_BAUD) >> 8) |
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85 #define CYG_DEV_SERIAL_RS232_T2_VALUE_B38400 (((_MEMCLK/16)/_BAUD) & 0xFF) |
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86 |
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87 //----------------------------------------------------------------------------- |
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88 // Define the serial registers. The 8245 has a 16552 UART builtin. |
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89 // |
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90 #define CYG_DEV_SERIAL_RBR 0x00 // receiver buffer register, read, dlab = 0 |
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91 #define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0 |
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92 #define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 |
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93 #define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0 |
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94 #define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1 |
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95 #define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0 |
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96 #define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0 |
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97 #define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1 |
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98 #define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write |
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99 #define CYG_DEV_SERIAL_MCR 0x04 |
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100 #define CYG_DEV_SERIAL_MCR_A 0x04 |
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101 #define CYG_DEV_SERIAL_MCR_B 0x04 |
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102 #define CYG_DEV_SERIAL_LSR 0x05 // line status register, read |
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103 #define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read |
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104 #define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register |
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105 |
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106 // The interrupt enable register bits. |
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107 #define SIO_IER_ERDAI 0x01 // enable received data available irq |
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108 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt |
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109 #define SIO_IER_ELSI 0x04 // enable receiver line status irq |
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110 #define SIO_IER_EMSI 0x08 // enable modem status interrupt |
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111 |
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112 // The interrupt identification register bits. |
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113 #define SIO_IIR_IP 0x01 // 0 if interrupt pending |
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114 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits |
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115 #define ISR_Tx 0x02 |
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116 #define ISR_Rx 0x04 |
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117 |
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118 // The line status register bits. |
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119 #define SIO_LSR_DR 0x01 // data ready |
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120 #define SIO_LSR_OE 0x02 // overrun error |
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121 #define SIO_LSR_PE 0x04 // parity error |
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122 #define SIO_LSR_FE 0x08 // framing error |
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123 #define SIO_LSR_BI 0x10 // break interrupt |
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124 #define SIO_LSR_THRE 0x20 // transmitter holding register empty |
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125 #define SIO_LSR_TEMT 0x40 // transmitter register empty |
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126 #define SIO_LSR_ERR 0x80 // any error condition |
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127 |
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128 // The modem status register bits. |
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129 #define SIO_MSR_DCTS 0x01 // delta clear to send |
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130 #define SIO_MSR_DDSR 0x02 // delta data set ready |
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131 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator |
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132 #define SIO_MSR_DDCD 0x08 // delta data carrier detect |
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133 #define SIO_MSR_CTS 0x10 // clear to send |
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134 #define SIO_MSR_DSR 0x20 // data set ready |
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135 #define SIO_MSR_RI 0x40 // ring indicator |
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136 #define SIO_MSR_DCD 0x80 // data carrier detect |
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137 |
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138 // The line control register bits. |
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139 #define SIO_LCR_WLS0 0x01 // word length select bit 0 |
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140 #define SIO_LCR_WLS1 0x02 // word length select bit 1 |
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141 #define SIO_LCR_STB 0x04 // number of stop bits |
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142 #define SIO_LCR_PEN 0x08 // parity enable |
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143 #define SIO_LCR_EPS 0x10 // even parity select |
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144 #define SIO_LCR_SP 0x20 // stick parity |
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145 #define SIO_LCR_SB 0x40 // set break |
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146 #define SIO_LCR_DLAB 0x80 // divisor latch access bit |
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147 |
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148 // The FIFO control register |
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149 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos |
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150 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO |
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151 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO |
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152 |
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153 |
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154 //----------------------------------------------------------------------------- |
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155 typedef struct { |
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156 cyg_uint8* base; |
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157 cyg_int32 msec_timeout; |
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158 int isr_vector; |
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159 } channel_data_t; |
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160 |
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161 //----------------------------------------------------------------------------- |
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162 static void |
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163 init_serial_channel(const channel_data_t* __ch_data) |
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164 { |
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165 cyg_uint8* base = __ch_data->base; |
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166 cyg_uint8 lcr; |
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167 |
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168 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_IER, 0); |
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169 |
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170 // Disable and clear FIFOs (need to enable to clear). |
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171 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, |
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172 (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2)); |
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173 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0); |
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174 |
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175 // 8-1-no parity. |
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176 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1); |
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177 |
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178 // Set speed to 38400. |
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179 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LCR, lcr); |
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180 lcr |= SIO_LCR_DLAB; |
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181 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr); |
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182 |
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183 |
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184 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, |
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185 CYG_DEV_SERIAL_RS232_T2_VALUE_B38400); |
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186 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, |
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187 CYG_DEV_SERIAL_RS232_T1_VALUE_B38400); |
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188 lcr &= ~SIO_LCR_DLAB; |
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189 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr); |
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190 |
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191 #if 0 // Necessary? |
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192 { |
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193 // Special initialization for ST16C552 on CMA102 |
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194 cyg_uint8 mcr; |
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195 |
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196 HAL_READ_UINT8(base+CYG_DEV_SERIAL_MCR_A, mcr); |
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197 mcr |= 8; |
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198 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR_A, mcr); |
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199 |
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200 HAL_READ_UINT8(base+CYG_DEV_SERIAL_MCR_B, mcr); |
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201 mcr |= 8; |
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202 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR_B, mcr); |
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203 } |
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204 #endif |
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205 |
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206 // Enable FIFOs (and clear them). |
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207 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, |
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208 (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2)); |
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209 } |
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210 |
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211 static cyg_bool |
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212 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) |
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213 { |
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214 cyg_uint8* base = ((channel_data_t*)__ch_data)->base; |
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215 cyg_uint8 lsr; |
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216 |
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217 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr); |
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218 if ((lsr & SIO_LSR_DR) == 0) |
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219 return false; |
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220 |
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221 HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch); |
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222 |
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223 return true; |
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224 } |
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225 |
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226 |
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227 cyg_uint8 |
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228 cyg_hal_plf_serial_getc(void* __ch_data) |
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229 { |
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230 cyg_uint8 ch; |
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231 CYGARC_HAL_SAVE_GP(); |
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232 |
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233 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); |
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234 |
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235 CYGARC_HAL_RESTORE_GP(); |
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236 return ch; |
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237 } |
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238 |
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239 void |
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240 cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c) |
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241 { |
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242 cyg_uint8* base = ((channel_data_t*)__ch_data)->base; |
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243 cyg_uint8 lsr; |
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244 CYGARC_HAL_SAVE_GP(); |
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245 |
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246 do { |
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247 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr); |
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248 } while ((lsr & SIO_LSR_THRE) == 0); |
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249 |
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250 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_THR, c); |
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251 |
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252 // Hang around until the character has been safely sent. |
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253 do { |
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254 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr); |
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255 } while ((lsr & SIO_LSR_THRE) == 0); |
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256 |
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257 CYGARC_HAL_RESTORE_GP(); |
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258 } |
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259 |
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260 static const channel_data_t channels[2] = { |
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261 { (cyg_uint8*)CYG_DEV_SERIAL_BASE_A, 1000, CYGNUM_HAL_INTERRUPT_UART0}, |
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262 #if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1) |
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263 { (cyg_uint8*)CYG_DEV_SERIAL_BASE_B, 1000, CYGNUM_HAL_INTERRUPT_UART1}, |
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264 #endif |
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265 }; |
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266 |
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267 static void |
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268 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, |
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269 cyg_uint32 __len) |
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270 { |
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271 CYGARC_HAL_SAVE_GP(); |
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272 |
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273 while(__len-- > 0) |
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274 cyg_hal_plf_serial_putc(__ch_data, *__buf++); |
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275 |
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276 CYGARC_HAL_RESTORE_GP(); |
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277 } |
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278 |
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279 static void |
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280 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) |
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281 { |
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282 CYGARC_HAL_SAVE_GP(); |
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283 |
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284 while(__len-- > 0) |
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285 *__buf++ = cyg_hal_plf_serial_getc(__ch_data); |
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286 |
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287 CYGARC_HAL_RESTORE_GP(); |
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288 } |
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289 |
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290 cyg_bool |
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291 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) |
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292 { |
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293 int delay_count; |
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294 channel_data_t* chan = (channel_data_t*)__ch_data; |
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295 cyg_bool res; |
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296 CYGARC_HAL_SAVE_GP(); |
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297 |
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298 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps |
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299 for(;;) { |
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300 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); |
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301 if (res || 0 == delay_count--) |
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302 break; |
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303 |
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304 CYGACC_CALL_IF_DELAY_US(100); |
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305 } |
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306 |
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307 CYGARC_HAL_RESTORE_GP(); |
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308 return res; |
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309 } |
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310 |
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311 static int |
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312 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) |
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313 { |
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314 static int irq_state = 0; |
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315 channel_data_t* chan = (channel_data_t*)__ch_data; |
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316 cyg_uint8 ier; |
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317 int ret = 0; |
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318 CYGARC_HAL_SAVE_GP(); |
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319 |
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320 switch (__func) { |
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321 case __COMMCTL_IRQ_ENABLE: |
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322 HAL_INTERRUPT_UNMASK(chan->isr_vector); |
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323 HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); |
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324 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier); |
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325 ier |= SIO_IER_ERDAI; |
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326 HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier); |
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327 irq_state = 1; |
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328 break; |
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329 case __COMMCTL_IRQ_DISABLE: |
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330 ret = irq_state; |
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331 irq_state = 0; |
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332 HAL_INTERRUPT_MASK(chan->isr_vector); |
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333 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier); |
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334 ier &= ~SIO_IER_ERDAI; |
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335 HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier); |
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336 break; |
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337 case __COMMCTL_DBG_ISR_VECTOR: |
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338 ret = chan->isr_vector; |
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339 break; |
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340 case __COMMCTL_SET_TIMEOUT: |
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341 { |
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342 va_list ap; |
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343 |
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344 va_start(ap, __func); |
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345 |
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346 ret = chan->msec_timeout; |
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347 chan->msec_timeout = va_arg(ap, cyg_uint32); |
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348 |
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349 va_end(ap); |
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350 } |
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351 default: |
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352 break; |
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353 } |
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354 CYGARC_HAL_RESTORE_GP(); |
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355 return ret; |
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356 } |
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357 |
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358 static int |
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359 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, |
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360 CYG_ADDRWORD __vector, CYG_ADDRWORD __data) |
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361 { |
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362 channel_data_t* chan = (channel_data_t*)__ch_data; |
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363 cyg_uint8 _iir; |
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364 int res = 0; |
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365 CYGARC_HAL_SAVE_GP(); |
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366 |
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367 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IIR, _iir); |
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368 _iir &= SIO_IIR_ID_MASK; |
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369 |
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370 *__ctrlc = 0; |
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371 if ( ISR_Rx == _iir ) { |
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372 cyg_uint8 c, lsr; |
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373 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_LSR, lsr); |
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374 if (lsr & SIO_LSR_DR) { |
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375 |
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376 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_RBR, c); |
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377 |
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378 if( cyg_hal_is_break( &c , 1 ) ) |
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379 *__ctrlc = 1; |
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380 } |
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381 |
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382 // Acknowledge the interrupt |
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383 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); |
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384 res = CYG_ISR_HANDLED; |
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385 } |
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386 |
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387 CYGARC_HAL_RESTORE_GP(); |
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388 return res; |
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389 } |
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390 |
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391 static void |
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392 cyg_hal_plf_serial_init(void) |
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393 { |
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394 hal_virtual_comm_table_t* comm; |
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395 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); |
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396 |
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397 // Disable interrupts. |
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398 HAL_INTERRUPT_MASK(channels[0].isr_vector); |
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399 #if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1) |
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400 HAL_INTERRUPT_MASK(channels[1].isr_vector); |
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401 #endif |
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402 |
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403 // Init channels |
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404 init_serial_channel(&channels[0]); |
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405 #if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1) |
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406 init_serial_channel(&channels[1]); |
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407 #endif |
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408 |
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409 // Setup procs in the vector table |
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410 |
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411 // Set channel 0 |
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412 CYGACC_CALL_IF_SET_CONSOLE_COMM(0); |
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413 comm = CYGACC_CALL_IF_CONSOLE_PROCS(); |
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414 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]); |
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415 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); |
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416 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); |
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417 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); |
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418 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); |
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419 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); |
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420 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); |
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421 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); |
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422 |
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423 #if (CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1) |
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424 // Set channel 1 |
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425 CYGACC_CALL_IF_SET_CONSOLE_COMM(1); |
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426 comm = CYGACC_CALL_IF_CONSOLE_PROCS(); |
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427 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]); |
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428 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); |
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429 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); |
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430 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); |
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431 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); |
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432 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); |
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433 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); |
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434 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); |
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435 #endif |
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436 |
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437 // Restore original console |
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438 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); |
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439 } |
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440 |
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441 void |
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442 cyg_hal_plf_comms_init(void) |
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443 { |
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444 static int initialized = 0; |
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445 |
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446 if (initialized) |
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447 return; |
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448 initialized = 1; |
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449 |
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450 cyg_hal_plf_serial_init(); |
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451 } |
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452 |
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453 // EOF hal_diag.c |
