Mercurial > flash_v2

annotate packages/hal/sh/sh4/current/cdl/hal_sh_sh4.cdl @ 171:42f843b391aa

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Merge from eCos master repository on 2001-07-18-03:13:25-BST
author jlarmour
date Wed, 18 Jul 2001 11:38:39 +0000
parents 25e238959bae
children 022f1e506033
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1 # ====================================================================
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2 #
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3 # hal_sh_sh4.cdl
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4 #
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5 # SH4 architectural HAL package configuration data
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6 #
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7 # ====================================================================
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8 #####COPYRIGHTBEGIN####
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Red Hat eCos Public License
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12 # Version 1.1 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://www.redhat.com/
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15 #
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16 # Software distributed under the License is distributed on an "AS IS"
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Configurable Operating System,
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22 # released September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Red Hat.
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25 # Portions created by Red Hat are
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26 # Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
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27 # All Rights Reserved.
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28 # -------------------------------------------
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29 #
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30 #####COPYRIGHTEND####
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31 # ====================================================================
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32 ######DESCRIPTIONBEGIN####
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33 #
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34 # Author(s): jskov
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35 # Original data: jskov
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36 # Contributors:
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37 # Date: 1999-10-29
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38 #
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39 #####DESCRIPTIONEND####
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40 #
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41 # ====================================================================
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42
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43 cdl_package CYGPKG_HAL_SH_SH4 {
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44 display "SH4 architecture"
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45 parent CYGPKG_HAL_SH
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46
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47 hardware
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48 include_dir cyg/hal
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49 define_header hal_sh_sh4.h
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50 description "
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51 The SH4 (SuperH 4) architecture HAL package provides generic
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52 support for this processor architecture. It is also
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53 necessary to select a specific target platform HAL
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54 package."
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55
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56 compile sh4_scif.c var_misc.c variant.S
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57
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58 define_proc {
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59 puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_sh_sh4.h>"
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60 }
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61
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62 # The "-o file" is a workaround for CR100958 - without it the
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63 # output file would end up in the source directory under CygWin.
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64 # n.b. grep does not behave itself under win32
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65 make -priority 1 {
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66 <PREFIX>/include/cyg/hal/sh4_offsets.inc : <PACKAGE>/src/var_mk_defs.c
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67 $(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh4_offsets.tmp -o var_mk_defs.tmp -S $<
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68 fgrep .equ var_mk_defs.tmp | sed s/#// > $@
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69 @echo $@ ": \\" > $(notdir $@).deps
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70 @tail +2 sh4_offsets.tmp >> $(notdir $@).deps
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71 @echo >> $(notdir $@).deps
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72 @rm sh4_offsets.tmp var_mk_defs.tmp
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73 }
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74
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75 # CPU variant supported
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76 cdl_component CYGPKG_HAL_SH_7750 {
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77 display "SH 7750 microprocessor"
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78 parent CYGPKG_HAL_SH_CPU
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79 implements CYGINT_HAL_SH_VARIANT
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80 implements CYGINT_HAL_SH_CPG_T1
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81 default_value 0
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82 no_define
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83 define -file=system.h CYGPKG_HAL_SH_7750
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84 description "
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85 The SH4 7750 microprocessor. This is an embedded part that in
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86 addition to the SH4 processor core has built in peripherals
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87 such as memory controllers, DMA controllers, serial ports and
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88 timers/counters."
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89 define_proc {
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90 puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7750.h>"
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91 }
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92 }
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93
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94 cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS {
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95 display "SH on-chip generic clock controls"
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96 description "
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97 The various clocks used by the system are controlled by
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98 these options, some of which are derived from platform
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99 settings."
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100 flavor none
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101 no_define
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102
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103 cdl_interface CYGINT_HAL_SH_CPG_T1 {
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104 display "Clock pulse generator type 1"
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105 }
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106
134
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107 cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 {
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108 display "TMU counter 0 prescaling"
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109 description "
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110 The peripheral clock is driving the counter used for
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111 the real-time clock, prescaled by this factor."
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112 flavor data
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113 legal_values { 4 16 64 256 }
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114 default_value 4
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115 }
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116
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117 cdl_option CYGHWR_HAL_SH_CLOCK_CKIO {
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118 display "CKIO clock"
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119 no_define
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120 flavor data
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121 calculated { CYGHWR_HAL_SH_PLL2_OUTPUT }
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122 }
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123
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124 cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT {
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125 display "The clock output from PLL1"
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126 no_define
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127 flavor data
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128 calculated { CYGHWR_HAL_SH_DIVIDER1_OUTPUT * CYGHWR_HAL_SH_OOC_PLL_1 }
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129 }
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130
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131 cdl_option CYGHWR_HAL_SH_DIVIDER1_OUTPUT {
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132 display "The clock output from divider 1"
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133 no_define
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134 flavor data
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135 # DIV1 output is either 1 or 1/2 XTAL
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136 calculated { (CYGHWR_HAL_SH_OOC_DIVIDER_1 == 1)
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137 ? CYGHWR_HAL_SH_OOC_XTAL
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138 : CYGHWR_HAL_SH_OOC_XTAL / 2 }
134
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139 }
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140
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141 cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED {
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142 display "Processor clock speed (MHz)"
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143 flavor data
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144 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_IFC }
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145 description "
171
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146 The peripheral speed is computed from the PLL2 output clock
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147 speed and the IFC divider settings."
134
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148 }
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149
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150 cdl_option CYGHWR_HAL_SH_BOARD_SPEED {
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151 display "Platform bus clock speed (MHz)"
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152 flavor data
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153 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_BFC }
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154 description "
171
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155 The peripheral speed is computed from the PLL2 output clock
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156 speed and the BFC divider settings."
134
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157 }
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158
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159 cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED {
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160 display "Processor on-chip peripheral clock speed (MHz)"
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161 flavor data
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162 calculated { CYGHWR_HAL_SH_PLL1_OUTPUT / CYGHWR_HAL_SH_OOC_DIVIDER_PFC }
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163 description "
171
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164 The peripheral speed is computed from the PLL2 output clock
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165 speed and the PFC divider settings."
134
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166 }
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167 }
151
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168
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169 cdl_option CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE {
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170 display "SCIF serial ports default baud rate"
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171 flavor data
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172 legal_values { 4800 9600 14400 19200 38400 57600 115200 }
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173 default_value { CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE_DEFAULT ? \
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174 CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE_DEFAULT : 38400 }
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175 description "
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176 This controls the default baud rate used for communicating
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177 with GDB / displaying diagnostic output."
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178 }
171
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179
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180 cdl_component CYGPKG_HAL_SH_INTERRUPT {
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181 display "Interrupt controls"
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182 flavor none
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183 no_define
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184 description "
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185 Initial interrupt settings can be specified using these option."
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186
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187 cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL {
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188 display "Use IRL0-3 pins as IRL input"
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189 default_value 0
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190 description "
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191 It is possible for the IRL0-3 pins to be used as IRL
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192 inputs by enabling this option."
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193 }
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194 }
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195
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196 # Cache settings
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197 cdl_option CYGHWR_HAL_SH_CACHE_MODE_P0 {
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198 display "Select cache mode set for P0/U0/P3 at startup"
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199 parent CYGPKG_HAL_SH_CACHE
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200 default_value { "WRITE_BACK" }
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201 legal_values { "WRITE_BACK" "WRITE_THROUGH" }
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202 flavor data
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203 description "
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204 Controls what cache mode the cache should be put in at
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205 startup for areas P0, U0 and P3. Write-back mode improves
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206 performance by letting dirty data to be kept in the
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207 cache for a period of time, allowing mutiple writes to
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208 the same cache line to be written back to memory in
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209 one memory transaction. In Write-through mode, each
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210 individual write will cause a memory transaction."
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211 }
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212
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213 cdl_option CYGHWR_HAL_SH_CACHE_MODE_P1 {
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214 display "Select cache mode set for P1 at startup"
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215 parent CYGPKG_HAL_SH_CACHE
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216 default_value { "WRITE_BACK" }
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217 legal_values { "WRITE_BACK" "WRITE_THROUGH" }
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218 flavor data
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219 description "
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220 Controls what cache mode the cache should be put in at
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221 startup for area P1. Write-back mode improves
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222 performance by letting dirty data to be kept in the
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223 cache for a period of time, allowing mutiple writes to
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224 the same cache line to be written back to memory in
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225 one memory transaction. In Write-through mode, each
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226 individual write will cause a memory transaction."
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227 }
134
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228 }