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annotate packages/hal/mips/arch/current/include/arch.inc @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents bf00f99aec69
children afdeb44241de
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1 #ifndef CYGONCE_HAL_ARCH_INC
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2 #define CYGONCE_HAL_ARCH_INC
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3 ##=============================================================================
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4 ##
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5 ## arch.inc
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6 ##
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7 ## MIPS assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.1 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://www.redhat.com/
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17 #
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18 # Software distributed under the License is distributed on an "AS IS"
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): nickg
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37 ## Contributors: nickg
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38 ## Date: 1997-10-16
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39 ## Purpose: Architecture definitions.
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40 ## Description: This file contains various definitions and macros that are
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41 ## useful for writing assembly code for the MIPS CPU family.
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42 ## Usage:
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43 ## #include <cyg/hal/arch.inc>
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44 ## ...
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45 ##
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46 ##
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47 ######DESCRIPTIONEND####
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48 ##
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49 ##=============================================================================
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50
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51 #include <cyg/hal/mips.inc>
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52
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53 #include <cyg/hal/variant.inc>
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54
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55 ##-----------------------------------------------------------------------------
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56 ## Set up the value for the initial status register
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57
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58 #ifndef INITIAL_SR
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59
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60 #if defined(CYG_HAL_STARTUP_RAM)
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61 # if defined(CYGPKG_HAL_MIPS_SIM) || !defined(CYGSEM_HAL_USE_ROM_MONITOR)
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62 # define INITIAL_SR 0x1000ff00 /* CP0 usable, Ints enabled */
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63 # else
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64 # define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */
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65 # endif
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66 #elif defined(CYG_HAL_STARTUP_ROM)
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67 # define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */
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68 #endif
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69
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70 #endif
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71
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72 ##-----------------------------------------------------------------------------
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73 ## Setup the initial value for the config0 register
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74
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75 #ifndef INITIAL_CONFIG0
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76
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77 #define INITIAL_CONFIG0 0x00000002
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78
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79 #endif
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80
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81 ##-----------------------------------------------------------------------------
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82 ## MIPS thread and interrupt saved state. This must match the layout of the
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83 ## HAL_SavedRegisters in hal_arch.h. Do not change this without changing the
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84 ## layout there, or viceversa.
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85
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86 #ifdef CYGHWR_HAL_MIPS_64BIT
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87 # define mips_regsize 8
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88 #else
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89 # define mips_regsize 4
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90 #endif
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91
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92 # define mips_regsize32 4
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93
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94 #if defined(CYGHWR_HAL_MIPS_FPU)
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95 # if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
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96 # define mips_fpuregsize 8
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97 # elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
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98 # define mips_fpuregsize 4
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99 # else
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100 # error MIPS FPU register size not defined
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101 # endif
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102 #endif
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103
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104
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105 #define mipsreg_regs 0
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106 #define mipsreg_hi (mips_regsize*32)
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107 #define mipsreg_lo (mipsreg_hi+mips_regsize)
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108 #ifdef CYGHWR_HAL_MIPS_FPU
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109 # define mipsreg_fpureg (mipsreg_lo+mips_regsize)
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110 # define mipsreg_fcr31 (mipsreg_fpureg+(mips_fpuregsize*32))
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111 # define mipsreg_fppad (mipsreg_fcr31+mips_regsize32)
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112 # define mipsreg_vector (mipsreg_fppad+mips_regsize32)
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113 #else
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114 # define mipsreg_vector (mipsreg_lo+mips_regsize32)
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115 #endif
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116 #define mipsreg_pc (mipsreg_vector+mips_regsize32)
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117 #define mipsreg_sr (mipsreg_pc+mips_regsize32)
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118 #define mipsreg_cachectrl (mipsreg_sr+mips_regsize32)
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119 #define mipsreg_cause (mipsreg_cachectrl+mips_regsize32)
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120 #define mipsreg_badvr (mipsreg_cause+mips_regsize32)
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121 #define mipsreg_prid (mipsreg_badvr+mips_regsize32)
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122 #define mipsreg_config (mipsreg_prid+mips_regsize32)
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123 #define mipsreg_size (mipsreg_config+mips_regsize32)
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124
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125 #define mips_exception_decrement (mipsreg_size*2)
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126
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127 ##-----------------------------------------------------------------------------
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128 ## Minimal stack frame size uses to call functions from asm.
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129
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130 #define mips_stack_frame_size 32 // 4 (64 bit) args worth
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131
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132 ##-----------------------------------------------------------------------------
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133 ## Load Address and Relocate. This macro is used in code that may be linked
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134 ## to execute out of RAM but is actually executed from ROM. If that is the
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135 ## case a suitable version of this macro will have been defined elsewhere.
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136 ## This is just a default version for use when that does not happen.
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137
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138 #ifndef CYGPKG_HAL_MIPS_LAR_DEFINED
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139
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140 .macro lar reg,addr
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141 la \reg,\addr
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142 .endm
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143
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144 #define CYGPKG_HAL_MIPS_LAR_DEFINED
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145
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146 #endif
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147
6
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148 ##-----------------------------------------------------------------------------
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149 ## CPU specific macros. These provide a common assembler interface to
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150 ## operations that may have CPU specific implementations on different
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151 ## variants of the architecture.
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152
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153 # Initialize CPU
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154 .macro hal_cpu_init
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155 mtc0 zero,cause # zero cause reg
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156 nop
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157 la v0,INITIAL_SR # initialize status register
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158 mtc0 v0,status
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159 nop
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160 nop
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161 nop
8
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162 la v0,INITIAL_CONFIG0
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163 mtc0 v0,config0
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164 nop
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165 nop
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166 nop
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167 .endm
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168
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169 # Enable interrupts
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170 #ifdef CYG_HAL_MIPS_R3900
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171 .macro hal_cpu_int_enable
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172 mfc0 v0,status
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173 nop
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174 nop
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175 ori v0,v0,0x0001 # set IE bit
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176 mtc0 v0,status
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177 nop
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178 nop
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179 nop
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180 .endm
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181 #else
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182 .macro hal_cpu_int_enable
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183 mfc0 v0,status
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184 la v1,0xFFFFFFF9
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185 and v0,v0,v1 # clear EXL and ERL bits
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186 ori v0,v0,0x0001 # set IE bit
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187 mtc0 v0,status
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188 nop
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189 nop
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190 nop
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191 .endm
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192 #endif
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193
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194
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195 # Disable interrupts
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196 .macro hal_cpu_int_disable
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197 mfc0 v0,status
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198 la v1,0xFFFFFFFE
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199 and v0,v0,v1
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200 mtc0 v0,status
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201 nop
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202 nop
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203 nop
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204 .endm
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205
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206 # Merge the interrupt enable state of the status register in
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207 # \sr with the current sr.
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208 #ifdef CYG_HAL_MIPS_R3900
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209 #define HAL_SR_INT_MASK 0x00000001 // IEc only
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210 #else
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211 #define HAL_SR_INT_MASK 0x00000007 // IE, EXL, ERL
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212 #endif
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213 .macro hal_cpu_int_merge sr
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214 mfc0 v0,status # V0 = current SR
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215 la v1,HAL_SR_INT_MASK # V1 = SR interrupt bits mask
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216 and \sr,\sr,v1 # Isolate interrupt bits of \sr
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217 nor v1,v1,zero # Invert mask
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218 and v0,v0,v1 # V0 = current SR except int bits
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219 or v0,v0,\sr # V0 = New SR
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220 mtc0 v0,status # Return to SR
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221 .endm
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222
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223 # Enable further exception processing, and disable
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224 # interrupt processing.
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225 #ifdef CYG_HAL_MIPS_R3900
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226 .macro hal_cpu_except_enable
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227 hal_cpu_int_disable
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228 .endm
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229 #else
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230 .macro hal_cpu_except_enable
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231 mfc0 v0,status
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232 la v1,0xFFFFFFF0
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233 and v0,v0,v1 # clear EXL, ERL and IE bits
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234 mtc0 v0,status
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235 nop
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236 nop
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237 nop
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238 .endm
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239 #endif
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240
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241 # Return from exception.
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242 #ifdef CYG_HAL_MIPS_R3900
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243 .macro hal_cpu_eret pc,sr
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244 mtc0 \sr,status # Load status register
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245 nop
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246 nop
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247 nop
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248 sync # settle things down
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249 jr \pc # jump back to interrupted code
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250 rfe # restore state (delay slot)
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251 .endm
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252 #else
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253 .macro hal_cpu_eret pc,sr
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254 mtc0 \pc,epc # put PC in EPC
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255 nop
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256 nop
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257 nop
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258 mtc0 \sr,status # put SR back
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259 nop
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260 nop
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261 nop
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262 sync # settle things down
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263 eret # return
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264 nop # just to be safe
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265 .endm
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266 #endif
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267
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268 ##-----------------------------------------------------------------------------
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269 # Default MIPS interrupt decoding macros. This uses the basic interrupt
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270 # support provided by CP0 in the cause and status registers. If there is
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271 # a more complex external interrupt controller, or the default stuff is
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272 # interpreted differently (as in the TX3904) then these macros will be
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273 # overridden and CYGPKG_HAL_MIPS_INTC_DEFINED will be defined.
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274
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275 #ifndef CYGPKG_HAL_MIPS_INTC_DEFINED
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276
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277 #ifndef CYGPKG_HAL_MIPS_INTC_INIT_DEFINED
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278 # initialize all interrupts to disabled
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279 .macro hal_intc_init
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280 mfc0 v0,status
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281 nop
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282 lui v1,0xFFFF
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283 ori v1,v1,0x00FF
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284 and v0,v0,v1 # clear the IntMask bits
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285 mtc0 v0,status
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286 nop
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287 nop
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288 nop
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289 .endm
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290 #endif
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291
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292 .macro hal_intc_decode vnum
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293 mfc0 v0,cause # get cause register
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294 nop # delay slot
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295 srl v0,v0,10 # shift interrupt bits down
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296 andi v0,v0,0x7f # isolate 6 interrupt bits
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297 la v1,hal_intc_translation_table
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298 add v0,v0,v1 # index into table
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299 lb \vnum,0(v0) # pick up vector number
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300 .endm
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301
48
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302 #ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
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303 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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304 .macro hal_intc_translate inum,vnum
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305 move \vnum,zero # Just vector zero is supported
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306 .endm
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307 #else
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308 .macro hal_intc_translate inum,vnum
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309 move \vnum,\inum # Vector == interrupt number
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310 .endm
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311 #endif
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312 #endif
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313
6
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314 .macro hal_intc_decode_data
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315 hal_intc_translation_table:
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316 .byte 0, 0, 1, 0
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317 .byte 2, 0, 1, 0
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318 .byte 3, 0, 1, 0
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319 .byte 2, 0, 1, 0
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320 .byte 4, 0, 1, 0
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321 .byte 2, 0, 1, 0
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322 .byte 3, 0, 1, 0
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323 .byte 2, 0, 1, 0
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324 .byte 5, 0, 1, 0
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325 .byte 2, 0, 1, 0
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326 .byte 3, 0, 1, 0
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327 .byte 2, 0, 1, 0
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328 .byte 4, 0, 1, 0
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329 .byte 2, 0, 1, 0
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330 .byte 3, 0, 1, 0
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331 .byte 2, 0, 1, 0
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332 .endm
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333 #endif
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334
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335 #------------------------------------------------------------------------------
62
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336 # Register save and restore macros. These expect a pointer to a CPU save state
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337 # area in the register \ptr. The GPR indicated by \reg will be saved into its
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338 # slot in that structure.
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339
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340 #ifdef CYGHWR_HAL_MIPS_64BIT
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341
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342 .macro sgpr reg,ptr
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343 sd $\reg,(mipsreg_regs+\reg*mips_regsize)(\ptr)
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344 .endm
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345
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346 .macro lgpr reg,ptr
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347 ld $\reg,(mipsreg_regs+\reg*mips_regsize)(\ptr)
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348 .endm
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349
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350 .macro slo reg,ptr
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351 sd \reg,(mipsreg_lo)(\ptr)
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352 .endm
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353
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354 .macro shi reg,ptr
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355 sd \reg,(mipsreg_hi)(\ptr)
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356 .endm
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357
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358 .macro llo reg,ptr
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359 ld \reg,(mipsreg_lo)(\ptr)
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360 .endm
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361
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362 .macro lhi reg,ptr
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363 ld \reg,(mipsreg_hi)(\ptr)
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364 .endm
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365
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366 .macro ssp reg,ptr
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367 sd \reg,(mipsreg_regs+29*mips_regsize)(\ptr)
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368 .endm
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369
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370 .macro lsp reg,ptr
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371 ld \reg,(mipsreg_regs+29*mips_regsize)(\ptr)
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372 .endm
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373
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374 #else
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375
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376 .macro sgpr reg,ptr
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377 sw $\reg,(mipsreg_regs+\reg*mips_regsize)(\ptr)
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378 .endm
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379
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380 .macro lgpr reg,ptr
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381 lw $\reg,(mipsreg_regs+\reg*mips_regsize)(\ptr)
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382 .endm
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383
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384 .macro slo reg,ptr
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385 sw \reg,(mipsreg_lo)(\ptr)
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386 .endm
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387
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388 .macro shi reg,ptr
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389 sw \reg,(mipsreg_hi)(\ptr)
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390 .endm
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391
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392 .macro llo reg,ptr
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393 lw \reg,(mipsreg_lo)(\ptr)
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394 .endm
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395
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396 .macro lhi reg,ptr
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397 lw \reg,(mipsreg_hi)(\ptr)
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398 .endm
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399
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400 .macro ssp reg,ptr
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401 sw \reg,(mipsreg_regs+29*mips_regsize)(\ptr)
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402 .endm
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403
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404 .macro lsp reg,ptr
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405 lw \reg,(mipsreg_regs+29*mips_regsize)(\ptr)
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406 .endm
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407
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408 #endif
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409
76
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410 # PC is always 32-bit for us
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411
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412 .macro lpc reg,ptr
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413 lw \reg,(mipsreg_pc)(\ptr)
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414 .endm
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415
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416 .macro spc reg,ptr
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417 sw \reg,(mipsreg_pc)(\ptr)
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418 .endm
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419
62
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420 #------------------------------------------------------------------------------
6
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421 # FPU macros.
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422 # The MIPS floating point unit essentially operates in two modes. In the first
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423 # it supplies 32 32bit FP registers that may be paired into 16 64 bit registers.
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424 # In the second it supplies 32 64bit registers. Which mode is to be used depends
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425 # not only on the specific implementation in use, but also on the setting of the
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426 # FR bit in the status register (if it is implemented) and on the expectations of
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427 # the toolchain.
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428
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429 #ifndef CYGPKG_HAL_MIPS_FPU_DEFINED
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430
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431 #ifdef CYGHWR_HAL_MIPS_FPU
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432
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433 #if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
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434 #define sfpr sdc1
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435 #define lfpr ldc1
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436 #define CYG_HAL_MIPS_FPU_SR_INIT 0x24000000
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437 #elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
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438 #define sfpr swc1
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439 #define lfpr lwc1
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440 #define CYG_HAL_MIPS_FPU_SR_INIT 0x20000000
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441 #else
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442 #error MIPS FPU register size not defined
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443 #endif
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444
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445 #ifndef CYG_HAL_MIPS_FCSR_INIT
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446 #define CYG_HAL_MIPS_FCSR_INIT 0
18
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447 #endif
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448
6
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449 .macro hal_fpu_init
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450 mfc0 v0,status # Get sr
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451 la v1,0xDBFFFFFF # Clear bits to be changed
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452 and v0,v0,v1
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453 la v1,CYG_HAL_MIPS_FPU_SR_INIT # Set the bits we want
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454 or v0,v0,v1 # Set sr to required value
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455 mtc0 v0,status # return to sr
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456 nop
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457 nop
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458 nop
26
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459 la v0,CYG_HAL_MIPS_FCSR_INIT # Get initial value for FCR31
18
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460 ctc1 v0,$31 # set Fp control reg
6
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461 nop
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462 .endm
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463
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464 # Save the caller-saved registers as defined by the ABI.
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465 # These only really need saving during interrupts.
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466 .macro hal_fpu_save_caller regs
26
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467 cfc1 v0,$31
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468 sw v0,mipsreg_fcr31(\regs)
6
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469 sfpr f0,(mipsreg_fpureg+0*mips_fpuregsize)(\regs)
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470 sfpr f1,(mipsreg_fpureg+1*mips_fpuregsize)(\regs)
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471 sfpr f2,(mipsreg_fpureg+2*mips_fpuregsize)(\regs)
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472 sfpr f3,(mipsreg_fpureg+3*mips_fpuregsize)(\regs)
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473 sfpr f4,(mipsreg_fpureg+4*mips_fpuregsize)(\regs)
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474 sfpr f5,(mipsreg_fpureg+5*mips_fpuregsize)(\regs)
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475 sfpr f6,(mipsreg_fpureg+6*mips_fpuregsize)(\regs)
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476 sfpr f7,(mipsreg_fpureg+7*mips_fpuregsize)(\regs)
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477 sfpr f8,(mipsreg_fpureg+8*mips_fpuregsize)(\regs)
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478 sfpr f9,(mipsreg_fpureg+9*mips_fpuregsize)(\regs)
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479 sfpr f10,(mipsreg_fpureg+10*mips_fpuregsize)(\regs)
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480 sfpr f11,(mipsreg_fpureg+11*mips_fpuregsize)(\regs)
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481 sfpr f12,(mipsreg_fpureg+12*mips_fpuregsize)(\regs)
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482 sfpr f13,(mipsreg_fpureg+13*mips_fpuregsize)(\regs)
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483 sfpr f14,(mipsreg_fpureg+14*mips_fpuregsize)(\regs)
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484 sfpr f15,(mipsreg_fpureg+15*mips_fpuregsize)(\regs)
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485 sfpr f16,(mipsreg_fpureg+16*mips_fpuregsize)(\regs)
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486 sfpr f17,(mipsreg_fpureg+17*mips_fpuregsize)(\regs)
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487 sfpr f18,(mipsreg_fpureg+18*mips_fpuregsize)(\regs)
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488 sfpr f19,(mipsreg_fpureg+19*mips_fpuregsize)(\regs)
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489 sfpr f31,(mipsreg_fpureg+31*mips_fpuregsize)(\regs)
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490 .endm
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491
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492 # Save the callee-saved registers as defined by the ABI.
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493 # These are the only registers that need to be saved
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494 # across thread switches.
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495 .macro hal_fpu_save_callee regs
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496 sfpr f20,(mipsreg_fpureg+20*mips_fpuregsize)(\regs)
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497 sfpr f21,(mipsreg_fpureg+21*mips_fpuregsize)(\regs)
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498 sfpr f22,(mipsreg_fpureg+22*mips_fpuregsize)(\regs)
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499 sfpr f23,(mipsreg_fpureg+23*mips_fpuregsize)(\regs)
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500 sfpr f24,(mipsreg_fpureg+24*mips_fpuregsize)(\regs)
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501 sfpr f25,(mipsreg_fpureg+25*mips_fpuregsize)(\regs)
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502 sfpr f26,(mipsreg_fpureg+26*mips_fpuregsize)(\regs)
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503 sfpr f27,(mipsreg_fpureg+27*mips_fpuregsize)(\regs)
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504 sfpr f28,(mipsreg_fpureg+28*mips_fpuregsize)(\regs)
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505 sfpr f29,(mipsreg_fpureg+29*mips_fpuregsize)(\regs)
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506 sfpr f30,(mipsreg_fpureg+30*mips_fpuregsize)(\regs)
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507 .endm
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508
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509 # General macro to save everything
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510 .macro hal_fpu_save regs
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511 hal_fpu_save_caller \regs
6
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512 hal_fpu_save_callee \regs
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513 .endm
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514
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515 # Reload the caller-saved registers.
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516 .macro hal_fpu_load_caller regs
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517 lfpr f0,(mipsreg_fpureg+0*mips_fpuregsize)(\regs)
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518 lfpr f1,(mipsreg_fpureg+1*mips_fpuregsize)(\regs)
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519 lfpr f2,(mipsreg_fpureg+2*mips_fpuregsize)(\regs)
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520 lfpr f3,(mipsreg_fpureg+3*mips_fpuregsize)(\regs)
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521 lfpr f4,(mipsreg_fpureg+4*mips_fpuregsize)(\regs)
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522 lfpr f5,(mipsreg_fpureg+5*mips_fpuregsize)(\regs)
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523 lfpr f6,(mipsreg_fpureg+6*mips_fpuregsize)(\regs)
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524 lfpr f7,(mipsreg_fpureg+7*mips_fpuregsize)(\regs)
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525 lfpr f8,(mipsreg_fpureg+8*mips_fpuregsize)(\regs)
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526 lfpr f9,(mipsreg_fpureg+9*mips_fpuregsize)(\regs)
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527 lfpr f10,(mipsreg_fpureg+10*mips_fpuregsize)(\regs)
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528 lfpr f11,(mipsreg_fpureg+11*mips_fpuregsize)(\regs)
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529 lfpr f12,(mipsreg_fpureg+12*mips_fpuregsize)(\regs)
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530 lfpr f13,(mipsreg_fpureg+13*mips_fpuregsize)(\regs)
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531 lfpr f14,(mipsreg_fpureg+14*mips_fpuregsize)(\regs)
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532 lfpr f15,(mipsreg_fpureg+15*mips_fpuregsize)(\regs)
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533 lfpr f16,(mipsreg_fpureg+16*mips_fpuregsize)(\regs)
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534 lfpr f17,(mipsreg_fpureg+17*mips_fpuregsize)(\regs)
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535 lfpr f18,(mipsreg_fpureg+18*mips_fpuregsize)(\regs)
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536 lfpr f19,(mipsreg_fpureg+19*mips_fpuregsize)(\regs)
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537 lfpr f31,(mipsreg_fpureg+31*mips_fpuregsize)(\regs)
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538 lw v0,mipsreg_fcr31(\regs)
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539 ctc1 v0,$31
6
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540 .endm
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541
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542 # Reload the callee-saved registers.
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543 .macro hal_fpu_load_callee regs
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544 lfpr f20,(mipsreg_fpureg+20*mips_fpuregsize)(\regs)
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545 lfpr f21,(mipsreg_fpureg+21*mips_fpuregsize)(\regs)
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546 lfpr f22,(mipsreg_fpureg+22*mips_fpuregsize)(\regs)
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547 lfpr f23,(mipsreg_fpureg+23*mips_fpuregsize)(\regs)
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548 lfpr f24,(mipsreg_fpureg+24*mips_fpuregsize)(\regs)
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549 lfpr f25,(mipsreg_fpureg+25*mips_fpuregsize)(\regs)
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550 lfpr f26,(mipsreg_fpureg+26*mips_fpuregsize)(\regs)
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551 lfpr f27,(mipsreg_fpureg+27*mips_fpuregsize)(\regs)
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552 lfpr f28,(mipsreg_fpureg+28*mips_fpuregsize)(\regs)
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553 lfpr f29,(mipsreg_fpureg+29*mips_fpuregsize)(\regs)
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554 lfpr f30,(mipsreg_fpureg+30*mips_fpuregsize)(\regs)
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555 .endm
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556
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557 # Reload everything.
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558 .macro hal_fpu_load regs
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559 hal_fpu_load_caller \regs
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560 hal_fpu_load_callee \regs
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561 .endm
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562 #else
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563
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564 # Default macros for non-fpu implementations
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565
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566 .macro hal_fpu_init
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567 .endm
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568
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569 .macro hal_fpu_save regs
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570 .endm
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571
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572 .macro hal_fpu_save_caller regs
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573 .endm
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574
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575 .macro hal_fpu_save_callee regs
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576 .endm
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577
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578 .macro hal_fpu_load_caller regs
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579 .endm
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580
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581 .macro hal_fpu_load_callee regs
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582 .endm
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583
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584 .macro hal_fpu_load regs
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585 .endm
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586
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587 #endif
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588
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589 #endif
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590
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591 #------------------------------------------------------------------------------
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592 # MMU macros.
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593
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594 #ifndef CYGPKG_HAL_MIPS_MMU_DEFINED
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595
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596 .macro hal_mmu_init
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597 .endm
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598
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599 #endif
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600
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601 #------------------------------------------------------------------------------
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602 # MEMC macros.
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603
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604 #ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED
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605
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606 .macro hal_memc_init
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607 .endm
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608
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609 #endif
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610
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611 #------------------------------------------------------------------------------
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612 # Cache macros.
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613
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614 #ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
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615
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616 #ifdef CYG_HAL_MIPS_R3900
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617 .macro hal_cache_init
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618 mfc0 v0,config # disable cache in config register
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619 nop
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620 nop
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621 la v1,0xffffffcf
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622 and v0,v0,v1
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623 mtc0 v0,config
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624 nop
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625 nop
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626 nop
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627 .endm
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628 #else
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629 .macro hal_cache_init
36
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630
6
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631 mfc0 v0,config0 # disable Kseg0 caching in config0 register
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632 nop
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633 nop
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634 la v1,0xfffffff8
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635 and v0,v0,v1
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636 ori v0,v0,2
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637 mtc0 v0,config0
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638 nop
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639 nop
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640 nop
24
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641
6
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642 .endm
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643 #endif
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644
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645 #endif
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646
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647 #------------------------------------------------------------------------------
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648 # Diagnostics macros.
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649
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650 #ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
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651
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652 .macro hal_diag_init
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653 .endm
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654
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655 .macro hal_diag_excpt_start
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656 .endm
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657
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658 .macro hal_diag_intr_start
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659 .endm
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660
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661 .macro hal_diag_restore
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662 .endm
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663 #endif
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664
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665 #------------------------------------------------------------------------------
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666 # Timer initialization.
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667
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668 #ifndef CYGPKG_HAL_MIPS_TIMER_DEFINED
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669
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670 .macro hal_timer_init
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671 .endm
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672
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673 #endif
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674
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675 #------------------------------------------------------------------------------
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676 # Monitor initialization.
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677
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678 #ifndef CYGPKG_HAL_MIPS_MON_DEFINED
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679
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680 .macro hal_mon_init
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681 .endm
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682
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683 #endif
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684
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685 #------------------------------------------------------------------------------
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686 #endif // ifndef CYGONCE_HAL_ARCH_INC
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687 # end of arch.inc