|
2
|
1 //========================================================================== |
|
|
2 // |
|
|
3 // aeb_misc.c |
|
|
4 // |
|
|
5 // HAL misc board support code for ARM AEB-1 |
|
|
6 // |
|
|
7 //========================================================================== |
|
|
8 //####COPYRIGHTBEGIN#### |
|
|
9 // |
|
|
10 // ------------------------------------------- |
|
|
11 // The contents of this file are subject to the Cygnus eCos Public License |
|
|
12 // Version 1.0 (the "License"); you may not use this file except in |
|
|
13 // compliance with the License. You may obtain a copy of the License at |
|
|
14 // http://sourceware.cygnus.com/ecos |
|
|
15 // |
|
|
16 // Software distributed under the License is distributed on an "AS IS" |
|
|
17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
|
|
18 // License for the specific language governing rights and limitations under |
|
|
19 // the License. |
|
|
20 // |
|
|
21 // The Original Code is eCos - Embedded Cygnus Operating System, released |
|
|
22 // September 30, 1998. |
|
|
23 // |
|
|
24 // The Initial Developer of the Original Code is Cygnus. Portions created |
|
|
25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
|
|
26 // ------------------------------------------- |
|
|
27 // |
|
|
28 //####COPYRIGHTEND#### |
|
|
29 //========================================================================== |
|
|
30 //#####DESCRIPTIONBEGIN#### |
|
|
31 // |
|
|
32 // Author(s): gthomas |
|
|
33 // Contributors: gthomas |
|
|
34 // Date: 1999-02-20 |
|
|
35 // Purpose: HAL board support |
|
|
36 // Description: Implementations of HAL board interfaces |
|
|
37 // |
|
|
38 //####DESCRIPTIONEND#### |
|
|
39 // |
|
|
40 //========================================================================*/ |
|
|
41 |
|
|
42 #include <pkgconf/hal.h> |
|
|
43 |
|
|
44 #include <cyg/infra/cyg_type.h> // base types |
|
|
45 #include <cyg/infra/cyg_trac.h> // tracing macros |
|
|
46 #include <cyg/infra/cyg_ass.h> // assertion macros |
|
|
47 |
|
|
48 #include <cyg/hal/hal_io.h> // IO macros |
|
|
49 #include <cyg/hal/hal_arch.h> // Register state info |
|
|
50 #include <cyg/hal/hal_diag.h> |
|
|
51 #include <cyg/hal/hal_intr.h> // necessary? |
|
|
52 #include <cyg/hal/hal_cache.h> |
|
|
53 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
|
|
54 #include <cyg/hal/drv_api.h> // HAL ISR support |
|
|
55 #endif |
|
|
56 |
|
|
57 /*------------------------------------------------------------------------*/ |
|
|
58 // On-board timer |
|
|
59 /*------------------------------------------------------------------------*/ |
|
|
60 |
|
|
61 // Timer registers |
|
|
62 #define CYG_DEVICE_TIMER0 ((volatile cyg_uint8 *)0xFFFF1800) |
|
|
63 #define CYG_DEVICE_TIMER1 ((volatile cyg_uint8 *)0xFFFF1804) |
|
|
64 #define CYG_DEVICE_TIMER2 ((volatile cyg_uint8 *)0xFFFF1808) |
|
|
65 #define CYG_DEVICE_TIMER_CTL ((volatile cyg_uint8 *)0xFFFF180C) |
|
|
66 #define CYG_DEVICE_IOCR ((volatile cyg_uint32 *)0xFFFFA410) |
|
|
67 #define CYG_DEVICE_CPM_PCSR ((volatile cyg_uint32 *)0xFFFFAC04) |
|
|
68 #define CYG_DEVICE_CPM_CT0CCR ((volatile cyg_uint32 *)0xFFFFAC18) |
|
|
69 #define CYG_DEVICE_CPM_CT1CCR ((volatile cyg_uint32 *)0xFFFFAC1C) |
|
|
70 #define CYG_DEVICE_CPM_CT2CCR ((volatile cyg_uint32 *)0xFFFFAC20) |
|
|
71 |
|
|
72 #define IOCR_CT0G (0x3<<9) |
|
|
73 #define IOCR_CT0G_EXTERNAL (0x0<<9) |
|
|
74 #define IOCR_CT0G_PWM0 (0x1<<9) |
|
|
75 #define IOCR_CT0G_LOW (0x2<<9) |
|
|
76 #define IOCR_CT0G_HIGH (0x3<<9) |
|
|
77 |
|
|
78 #define IOCR_CT1G (0x3<<11) |
|
|
79 #define IOCR_CT1G_EXTERNAL (0x0<<11) |
|
|
80 #define IOCR_CT1G_PWM0 (0x1<<11) |
|
|
81 #define IOCR_CT1G_LOW (0x2<<11) |
|
|
82 #define IOCR_CT1G_HIGH (0x3<<11) |
|
|
83 |
|
|
84 #define IOCR_CT2G (0x3<<13) |
|
|
85 #define IOCR_CT2G_EXTERNAL (0x0<<13) |
|
|
86 #define IOCR_CT2G_PWM0 (0x1<<13) |
|
|
87 #define IOCR_CT2G_LOW (0x2<<13) |
|
|
88 #define IOCR_CT2G_HIGH (0x3<<13) |
|
|
89 |
|
|
90 #define TIMER_CTL_TYPE (0x1<<0) |
|
|
91 #define TIMER_CTL_TYPE_BIN (0x0<<0) |
|
|
92 #define TIMER_CTL_TYPE_BCD (0x1<<0) |
|
|
93 #define TIMER_CTL_MODE (0x7<<1) |
|
|
94 #define TIMER_CTL_MODE_IOTC (0x0<<1) // Interrupt on terminal count |
|
|
95 #define TIMER_CTL_MODE_HROS (0x1<<1) // Hardware retriggerable one-shot |
|
|
96 #define TIMER_CTL_MODE_RG (0x2<<1) // Rate generator |
|
|
97 #define TIMER_CTL_MODE_SWG (0x3<<1) // Square-wave generator |
|
|
98 #define TIMER_CTL_MODE_STS (0x4<<1) // Software triggered strobe |
|
|
99 #define TIMER_CTL_MODE_HTS (0x5<<1) // Hardware triggered strobe |
|
|
100 #define TIMER_CTL_RW (0x3<<4) |
|
|
101 #define TIMER_CTL_RW_LATCH (0x0<<4) // Counter latch |
|
|
102 #define TIMER_CTL_RW_LSB (0x1<<4) |
|
|
103 #define TIMER_CTL_RW_MSB (0x2<<4) |
|
|
104 #define TIMER_CTL_RW_BOTH (0x3<<4) |
|
|
105 #define TIMER_CTL_SC (0x3<<6) |
|
|
106 #define TIMER_CTL_SC_CTR0 (0x0<<6) |
|
|
107 #define TIMER_CTL_SC_CTR1 (0x1<<6) |
|
|
108 #define TIMER_CTL_SC_CTR2 (0x2<<6) |
|
|
109 #define TIMER_CTL_SC_RBC (0x3<<6) |
|
|
110 |
|
|
111 // Interrupt controller registers |
|
|
112 #define CYG_DEVICE_ICTL_ICR0 ((volatile cyg_uint32 *)0xFFFFA800) |
|
|
113 #define CYG_DEVICE_ICTL_ICR1 ((volatile cyg_uint32 *)0xFFFFA804) |
|
|
114 #define CYG_DEVICE_ICTL_ICLR ((volatile cyg_uint32 *)0xFFFFA808) |
|
|
115 #define CYG_DEVICE_ICTL_IRQER ((volatile cyg_uint32 *)0xFFFFA80C) |
|
|
116 #define CYG_DEVICE_ICTL_FIQER ((volatile cyg_uint32 *)0xFFFFA810) |
|
|
117 #define CYG_DEVICE_ICTL_IRQSR ((volatile cyg_uint32 *)0xFFFFA814) |
|
|
118 #define CYG_DEVICE_ICTL_FIQSR ((volatile cyg_uint32 *)0xFFFFA818) |
|
|
119 #define CYG_DEVICE_ICTL_IPR ((volatile cyg_uint32 *)0xFFFFA81C) |
|
|
120 |
|
|
121 #define ICTL_ICR0_CH0 (0x3<<0) |
|
|
122 #define ICTL_ICR0_CH0_HL (0x1<<0) |
|
|
123 #define ICTL_ICR0_CH0_HL_AL (0x0<<0) // Active low |
|
|
124 #define ICTL_ICR0_CH0_HL_AH (0x1<<0) // Active high |
|
|
125 #define ICTL_ICR0_CH0_EL (0x2<<0) |
|
|
126 #define ICTL_ICR0_CH0_EL_LT (0x0<<0) // Level triggered |
|
|
127 #define ICTL_ICR0_CH0_EL_ET (0x2<<0) // Edge triggered |
|
|
128 #define ICTL_ICR0_CH1 (0x3<<2) |
|
|
129 #define ICTL_ICR0_CH1_HL (0x1<<2) |
|
|
130 #define ICTL_ICR0_CH1_HL_AL (0x0<<2) // Active low |
|
|
131 #define ICTL_ICR0_CH1_HL_AH (0x1<<2) // Active high |
|
|
132 #define ICTL_ICR0_CH1_EL (0x2<<2) |
|
|
133 #define ICTL_ICR0_CH1_EL_LT (0x0<<2) // Level triggered |
|
|
134 #define ICTL_ICR0_CH1_EL_ET (0x2<<2) // Edge triggered |
|
|
135 #define ICTL_ICR0_CH2 (0x3<<4) |
|
|
136 #define ICTL_ICR0_CH2_HL (0x1<<4) |
|
|
137 #define ICTL_ICR0_CH2_HL_AL (0x0<<4) // Active low |
|
|
138 #define ICTL_ICR0_CH2_HL_AH (0x1<<4) // Active high |
|
|
139 #define ICTL_ICR0_CH2_EL (0x2<<4) |
|
|
140 #define ICTL_ICR0_CH2_EL_LT (0x0<<4) // Level triggered |
|
|
141 #define ICTL_ICR0_CH2_EL_ET (0x2<<4) // Edge triggered |
|
|
142 #define ICTL_ICR0_CH3 (0x3<<6) |
|
|
143 #define ICTL_ICR0_CH3_HL (0x1<<6) |
|
|
144 #define ICTL_ICR0_CH3_HL_AL (0x0<<6) // Active low |
|
|
145 #define ICTL_ICR0_CH3_HL_AH (0x1<<6) // Active high |
|
|
146 #define ICTL_ICR0_CH3_EL (0x2<<6) |
|
|
147 #define ICTL_ICR0_CH3_EL_LT (0x0<<6) // Level triggered |
|
|
148 #define ICTL_ICR0_CH3_EL_ET (0x2<<6) // Edge triggered |
|
|
149 #define ICTL_ICR0_CH4 (0x3<<8) |
|
|
150 #define ICTL_ICR0_CH4_HL (0x1<<8) |
|
|
151 #define ICTL_ICR0_CH4_HL_AL (0x0<<8) // Active low |
|
|
152 #define ICTL_ICR0_CH4_HL_AH (0x1<<8) // Active high |
|
|
153 #define ICTL_ICR0_CH4_EL (0x2<<8) |
|
|
154 #define ICTL_ICR0_CH4_EL_LT (0x0<<8) // Level triggered |
|
|
155 #define ICTL_ICR0_CH4_EL_ET (0x2<<8) // Edge triggered |
|
|
156 #define ICTL_ICR0_CH5 (0x3<<10) |
|
|
157 #define ICTL_ICR0_CH5_HL (0x1<<10) |
|
|
158 #define ICTL_ICR0_CH5_HL_AL (0x0<<10) // Active low |
|
|
159 #define ICTL_ICR0_CH5_HL_AH (0x1<<10) // Active high |
|
|
160 #define ICTL_ICR0_CH5_EL (0x2<<10) |
|
|
161 #define ICTL_ICR0_CH5_EL_LT (0x0<<10) // Level triggered |
|
|
162 #define ICTL_ICR0_CH5_EL_ET (0x2<<10) // Edge triggered |
|
|
163 #define ICTL_ICR1_CH6 (0x1<<0) |
|
|
164 #define ICTL_ICR1_CH6_HL (0x1<<0) |
|
|
165 #define ICTL_ICR1_CH6_HL_AL (0x0<<0) // Active low |
|
|
166 #define ICTL_ICR1_CH6_HL_AH (0x1<<0) // Active high |
|
|
167 #define ICTL_ICR1_CH7 (0x1<<1) |
|
|
168 #define ICTL_ICR1_CH7_HL (0x1<<1) |
|
|
169 #define ICTL_ICR1_CH7_HL_AL (0x0<<1) // Active low |
|
|
170 #define ICTL_ICR1_CH7_HL_AH (0x1<<1) // Active high |
|
|
171 #define ICTL_ICR1_CH8 (0x1<<2) |
|
|
172 #define ICTL_ICR1_CH8_HL (0x1<<2) |
|
|
173 #define ICTL_ICR1_CH8_HL_AL (0x0<<2) // Active low |
|
|
174 #define ICTL_ICR1_CH8_HL_AH (0x1<<2) // Active high |
|
|
175 |
|
|
176 // Clock control registers |
|
|
177 #define PCSR_CT0CS (1<<3) |
|
|
178 #define PCSR_CT1CS (1<<4) |
|
|
179 #define PCSR_CT2CS (1<<5) |
|
|
180 #define CT_X16 16 |
|
|
181 |
|
|
182 #undef _TIMERS_TESTING |
|
|
183 #ifdef _TIMERS_TESTING |
|
|
184 static void aeb_setup_timer1(cyg_uint32 period); |
|
|
185 #endif |
|
|
186 |
|
|
187 static cyg_uint32 _period; |
|
|
188 |
|
|
189 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
|
|
190 static cyg_interrupt abort_interrupt; |
|
|
191 static cyg_handle_t abort_interrupt_handle; |
|
|
192 |
|
|
193 // This ISR is called only for the Abort button interrupt |
|
|
194 static int |
|
|
195 aeb_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) |
|
|
196 { |
|
|
197 cyg_hal_gdb_interrupt (regs->pc); |
|
|
198 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0); |
|
|
199 return 0; // No need to run DSR |
|
|
200 } |
|
|
201 #endif |
|
|
202 |
|
|
203 void hal_clock_initialize(cyg_uint32 period) |
|
|
204 { |
|
|
205 cyg_uint32 iocr; |
|
|
206 |
|
|
207 // Set counter GATE input low (0) to halt counter while it's being setup |
|
|
208 HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr); |
|
|
209 iocr = (iocr & ~IOCR_CT0G) | IOCR_CT0G_LOW; |
|
|
210 HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr); |
|
|
211 |
|
|
212 // Scale timer0 clock |
|
|
213 HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT0CCR, CT_X16); |
|
|
214 |
|
|
215 // Initialize counter, mode 2 = rate generator |
|
|
216 HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, |
|
|
217 TIMER_CTL_TYPE_BIN| |
|
|
218 TIMER_CTL_MODE_RG| |
|
|
219 TIMER_CTL_RW_BOTH| |
|
|
220 TIMER_CTL_SC_CTR0); |
|
|
221 HAL_WRITE_UINT8(CYG_DEVICE_TIMER0, (period & 0xFF)); // LSB |
|
|
222 HAL_WRITE_UINT8(CYG_DEVICE_TIMER0, ((period >> 8) & 0xFF)); // MSB |
|
|
223 // Enable timer |
|
|
224 iocr = (iocr & ~IOCR_CT0G) | IOCR_CT0G_HIGH; |
|
|
225 HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr); |
|
|
226 _period = period; |
|
|
227 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
|
|
228 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0, |
|
|
229 99, // Priority |
|
|
230 0, // Data item passed to interrupt handler |
|
|
231 aeb_abort_isr, |
|
|
232 0, |
|
|
233 &abort_interrupt_handle, |
|
|
234 &abort_interrupt); |
|
|
235 cyg_drv_interrupt_attach(abort_interrupt_handle); |
|
|
236 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0); |
|
|
237 #endif |
|
|
238 #ifdef _TIMERS_TESTING |
|
|
239 aeb_setup_timer1(period/10); |
|
|
240 #endif |
|
|
241 } |
|
|
242 |
|
|
243 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) |
|
|
244 { |
|
|
245 _period = period; |
|
|
246 } |
|
|
247 |
|
|
248 void hal_clock_read(cyg_uint32 *pvalue) |
|
|
249 { |
|
|
250 cyg_uint32 value; |
|
|
251 cyg_uint8 reg; |
|
|
252 do { |
|
|
253 HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, |
|
|
254 TIMER_CTL_RW_LATCH|TIMER_CTL_SC_CTR0); |
|
|
255 HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB |
|
|
256 value = reg; |
|
|
257 HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB |
|
|
258 value |= (reg << 8); |
|
|
259 } while (value <= 2); // Hardware malfunction? |
|
|
260 *pvalue = _period - (value & 0xFFFF); // Note: counter is only 16 bits |
|
|
261 // and decreases |
|
|
262 } |
|
|
263 |
|
|
264 void hal_hardware_init(void) |
|
|
265 { |
|
|
266 // Any hardware/platform initialization that needs to be done. |
|
|
267 // Set all unknowns as edge triggered |
|
|
268 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR0, |
|
|
269 ICTL_ICR0_CH0_HL_AL|ICTL_ICR0_CH0_EL_ET| |
|
|
270 ICTL_ICR0_CH1_HL_AL|ICTL_ICR0_CH1_EL_ET| |
|
|
271 ICTL_ICR0_CH2_HL_AL|ICTL_ICR0_CH2_EL_ET| |
|
|
272 ICTL_ICR0_CH3_HL_AL|ICTL_ICR0_CH3_EL_ET| |
|
|
273 ICTL_ICR0_CH4_HL_AL|ICTL_ICR0_CH4_EL_ET| |
|
|
274 ICTL_ICR0_CH5_HL_AL|ICTL_ICR0_CH5_EL_ET); |
|
|
275 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR1, |
|
|
276 ICTL_ICR1_CH6_HL_AL| |
|
|
277 ICTL_ICR1_CH7_HL_AL| |
|
|
278 ICTL_ICR1_CH8_HL_AL); |
|
|
279 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, 0xFFFF); // CLear all interrupts |
|
|
280 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, 0x0000); // All disabled |
|
|
281 // Clear and initialize instruction cache |
|
|
282 HAL_ICACHE_INVALIDATE_ALL(); |
|
|
283 HAL_ICACHE_ENABLE(); |
|
|
284 } |
|
|
285 |
|
|
286 // |
|
|
287 // This routine is called to respond to a hardware interrupt (IRQ). It |
|
|
288 // should interrogate the hardware and return the IRQ vector number. |
|
|
289 |
|
|
290 int hal_IRQ_handler(void) |
|
|
291 { |
|
|
292 // Do hardware-level IRQ handling |
|
|
293 int irq_status, vector; |
|
|
294 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status); |
|
|
295 for (vector = 0; vector < 16; vector++) { |
|
|
296 if (irq_status & (1<<vector)) return vector; |
|
|
297 } |
|
|
298 return CYGNUM_HAL_INTERRUPT_unused; // This shouldn't happen! |
|
|
299 } |
|
|
300 |
|
|
301 // |
|
|
302 // Interrupt control |
|
|
303 // |
|
|
304 |
|
|
305 void hal_interrupt_mask(int vector) |
|
|
306 { |
|
|
307 cyg_uint32 mask, old_mask; |
|
|
308 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, mask); |
|
|
309 old_mask = mask; |
|
|
310 mask &= ~(1<<vector); |
|
|
311 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, mask); |
|
|
312 } |
|
|
313 |
|
|
314 #if 0 |
|
|
315 void hal_interrupt_status(void) |
|
|
316 { |
|
|
317 int irq_status, irq_enable, ipr_value, timer_value; |
|
|
318 cyg_uint8 reg; |
|
|
319 HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // LSB |
|
|
320 timer_value = reg; |
|
|
321 HAL_READ_UINT8(CYG_DEVICE_TIMER0, reg); // MSB |
|
|
322 timer_value |= (reg << 8); |
|
|
323 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQSR, irq_status); |
|
|
324 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, irq_enable); |
|
|
325 HAL_READ_UINT32(CYG_DEVICE_ICTL_IPR, ipr_value); |
|
|
326 diag_printf("Interrupt: IRQ: %x.%x.%x, Timer: %x\n", irq_status, |
|
|
327 irq_enable, ipr_value, timer_value); |
|
|
328 } |
|
|
329 #endif |
|
|
330 |
|
|
331 void hal_interrupt_unmask(int vector) |
|
|
332 { |
|
|
333 cyg_uint32 mask, old_mask; |
|
|
334 HAL_READ_UINT32(CYG_DEVICE_ICTL_IRQER, mask); |
|
|
335 old_mask = mask; |
|
|
336 mask |= (1<<vector); |
|
|
337 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, mask); |
|
|
338 } |
|
|
339 |
|
|
340 void hal_interrupt_acknowledge(int vector) |
|
|
341 { |
|
|
342 HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, (1<<vector)); |
|
|
343 } |
|
|
344 |
|
|
345 void hal_interrupt_configure(int vector, int level, int up) |
|
|
346 { |
|
|
347 // diag_printf("%s(%d,%d,%d)\n", __PRETTY_FUNCTION__, vector, level, up); |
|
|
348 } |
|
|
349 |
|
|
350 void hal_interrupt_set_level(int vector, int level) |
|
|
351 { |
|
|
352 // diag_printf("%s(%d,%d)\n", __PRETTY_FUNCTION__, vector, level); |
|
|
353 } |
|
|
354 |
|
|
355 void hal_show_IRQ(int vector, int data, int handler) |
|
|
356 { |
|
|
357 // diag_printf("IRQ - vector: %x, data: %x, handler: %x\n", vector, |
|
|
358 // data, handler); |
|
|
359 } |
|
|
360 |
|
|
361 #ifdef _TIMERS_TESTING |
|
|
362 #include <cyg/hal/drv_api.h> // HAL ISR support |
|
|
363 static cyg_interrupt timer1_interrupt; |
|
|
364 static cyg_handle_t timer1_interrupt_handle; |
|
|
365 static cyg_uint32 timer1_count; |
|
|
366 |
|
|
367 // This ISR is called only for the high speed timer under test |
|
|
368 static int |
|
|
369 aeb_timer1_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) |
|
|
370 { |
|
|
371 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_TIMER1); |
|
|
372 timer1_count++; |
|
|
373 return 0; // No need to run DSR |
|
|
374 } |
|
|
375 |
|
|
376 static void |
|
|
377 aeb_setup_timer1(cyg_uint32 period) |
|
|
378 { |
|
|
379 cyg_uint32 iocr; |
|
|
380 |
|
|
381 // Set counter GATE input low (0) to halt counter while it's being setup |
|
|
382 HAL_READ_UINT32(CYG_DEVICE_IOCR, iocr); |
|
|
383 iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_LOW; |
|
|
384 HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr); |
|
|
385 |
|
|
386 // Scale timer0 clock |
|
|
387 HAL_WRITE_UINT32(CYG_DEVICE_CPM_CT1CCR, CT_X16); |
|
|
388 |
|
|
389 // Initialize counter, mode 2 = rate generator |
|
|
390 HAL_WRITE_UINT8(CYG_DEVICE_TIMER_CTL, |
|
|
391 TIMER_CTL_TYPE_BIN| |
|
|
392 TIMER_CTL_MODE_RG| |
|
|
393 TIMER_CTL_RW_BOTH| |
|
|
394 TIMER_CTL_SC_CTR1); |
|
|
395 HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, (period & 0xFF)); // LSB |
|
|
396 HAL_WRITE_UINT8(CYG_DEVICE_TIMER1, ((period >> 8) & 0xFF)); // MSB |
|
|
397 // Enable timer |
|
|
398 iocr = (iocr & ~IOCR_CT1G) | IOCR_CT1G_HIGH; |
|
|
399 HAL_WRITE_UINT32(CYG_DEVICE_IOCR, iocr); |
|
|
400 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_TIMER1, |
|
|
401 99, // Priority |
|
|
402 0, // Data item passed to interrupt handler |
|
|
403 aeb_timer1_isr, |
|
|
404 0, |
|
|
405 &timer1_interrupt_handle, |
|
|
406 &timer1_interrupt); |
|
|
407 cyg_drv_interrupt_attach(timer1_interrupt_handle); |
|
|
408 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER1); |
|
|
409 } |
|
|
410 #endif |
|
|
411 |
|
|
412 /*------------------------------------------------------------------------*/ |
|
|
413 // EOF hal_misc.c |
