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annotate packages/hal/mn10300/am31/current/include/var_cache.h @ 30:641b639be825 ecos-sw-1999-08-16

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Merge from eCos master repository on 1999-08-16-22:01:37-BST
author jlarmour
date Mon, 16 Aug 1999 22:10:49 +0000
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children c38311975d4f
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // var_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Cygnus eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released
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25 // September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Cygnus. Portions created
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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29 // -------------------------------------------
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30 //
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31 //####COPYRIGHTEND####
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32 //=============================================================================
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33 //#####DESCRIPTIONBEGIN####
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34 //
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35 // Author(s): nickg
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36 // Contributors: nickg
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37 // Date: 1998-02-17
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38 // Purpose: Cache control API
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39 // Description: The macros defined here provide the HAL APIs for handling
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40 // cache control operations.
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41 // Usage:
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42 // #include <cyg/hal/var_cache.h>
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43 // ...
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44 //
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <pkgconf/hal.h>
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51 #include <cyg/infra/cyg_type.h>
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52
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53 //#include <cyg/hal/plf_cache.h>
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54
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55 //=============================================================================
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56 // MN103002 implementation
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57
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58 //-----------------------------------------------------------------------------
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59 // Cache dimensions
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60
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61
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62 // Data cache
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63 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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64 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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65 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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66
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67 // Instruction cache
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68 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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69 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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70 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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71
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72 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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73 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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74
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75 //-----------------------------------------------------------------------------
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76 // Control registers
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77
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78 #define HAL_CHCTR ((volatile CYG_ADDRWORD *)0x20000070)
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79
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80 #define HAL_CHCTR_ICEN 0x0001
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81 #define HAL_CHCTR_DCEN 0x0002
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82 #define HAL_CHCTR_ICBUSY 0x0004
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83 #define HAL_CHCTR_DCBUSY 0x0008
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84 #define HAL_CHCTR_ICINV 0x0010
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85 #define HAL_CHCTR_DCINV 0x0020
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86 #define HAL_CHCTR_DCWTMD 0x0040
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87 #define HAL_CHCTR_ICWMD 0x0300
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88 #define HAL_CHCTR_DCWMD 0x3000
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89
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90 #define HAL_DCACHE_PURGE_WAY0 ((volatile CYG_BYTE *)0x28400000)
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91 #define HAL_DCACHE_PURGE_WAY1 ((volatile CYG_BYTE *)0x28401000)
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92
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93 //-----------------------------------------------------------------------------
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94 // Global control of data cache
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95
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96 // Enable the data cache
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97 #define HAL_DCACHE_ENABLE() \
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98 { \
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99 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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100 chctr |= HAL_CHCTR_DCEN; \
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101 *HAL_CHCTR = chctr; \
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102 }
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103
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104 // Disable the data cache
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105 #define HAL_DCACHE_DISABLE() \
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106 { \
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107 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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108 chctr &= ~HAL_CHCTR_DCEN; \
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109 *HAL_CHCTR = chctr; \
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110 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
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111 }
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112
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113 // Query the state of the data cache
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114 #define HAL_DCACHE_IS_ENABLED(_state_) \
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115 { \
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116 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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117 _state_ = (0 != (chctr & HAL_CHCTR_DCEN)); \
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118 }
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119
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120 // Invalidate the entire cache
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121 #define HAL_DCACHE_INVALIDATE_ALL() \
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122 { \
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123 register CYG_ADDRWORD chctr; \
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124 register CYG_ADDRWORD state; \
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125 HAL_DCACHE_IS_ENABLED(state); \
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126 if (state) \
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127 HAL_DCACHE_DISABLE(); \
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128 chctr = *HAL_CHCTR; \
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129 chctr |= HAL_CHCTR_DCINV; \
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130 *HAL_CHCTR = chctr; \
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131 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
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132 if (state) \
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133 HAL_DCACHE_ENABLE(); \
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134 }
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135
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136 // Synchronize the contents of the cache with memory.
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137 #define HAL_DCACHE_SYNC() HAL_DCACHE_STORE( 0, HAL_DCACHE_SIZE/HAL_DCACHE_WAYS )
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138
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139 // Set the data cache refill burst size
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140 //#define HAL_DCACHE_BURST_SIZE(_size_)
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141
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142 // Set the data cache write mode
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143 #define HAL_DCACHE_WRITE_MODE( _mode_ ) \
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144 { \
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145 register CYG_ADDRWORD chctr; \
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146 register CYG_ADDRWORD state; \
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147 HAL_DCACHE_IS_ENABLED(state); \
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148 if (state) \
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149 HAL_DCACHE_DISABLE(); \
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150 chctr = *HAL_CHCTR; \
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151 chctr |= HAL_CHCTR_DCWTMD*(_mode_); \
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152 *HAL_CHCTR = chctr; \
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153 while( HAL_CHCTR_DCBUSY & *HAL_CHCTR ); \
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154 if (state) \
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155 HAL_DCACHE_ENABLE(); \
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156 }
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157
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158 #define HAL_DCACHE_WRITEBACK_MODE 0
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159 #define HAL_DCACHE_WRITETHRU_MODE 1
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160
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161 // Load the contents of the given address range into the data cache
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162 // and then lock the cache so that it stays there.
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163 //#define HAL_DCACHE_LOCK(_base_, _size_)
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164
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165 // Undo a previous lock operation
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166 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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167
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168 // Unlock entire cache
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169 //#define HAL_DCACHE_UNLOCK_ALL()
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170
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171 //-----------------------------------------------------------------------------
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172 // Data cache line control
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173
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174 // Allocate cache lines for the given address range without reading its
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175 // contents from memory.
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176 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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177
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178 // Write dirty cache lines to memory and invalidate the cache entries
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179 // for the given address range.
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180 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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181
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182 // Invalidate cache lines in the given range without writing to memory.
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183 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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184
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185 // Write dirty cache lines to memory for the given address range.
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186
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187 // This functionality requires 4 register variables. To prevent register
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188 // spilling, put the code in a separate function.
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189 externC void cyg_hal_dcache_store(CYG_ADDRWORD base, int size);
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190
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191 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
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192 cyg_hal_dcache_store((_base_), (_size_))
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193
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194 // Preread the given range into the cache with the intention of reading
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195 // from it later.
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196 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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197
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198 // Preread the given range into the cache with the intention of writing
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199 // to it later.
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200 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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201
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202 // Allocate and zero the cache lines associated with the given range.
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203 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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204
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205 //-----------------------------------------------------------------------------
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206 // Global control of Instruction cache
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207
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208 // Enable the instruction cache
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209 #define HAL_ICACHE_ENABLE() \
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210 { \
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211 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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212 chctr |= HAL_CHCTR_ICEN; \
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213 *HAL_CHCTR = chctr; \
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214 }
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215
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216 // Disable the instruction cache
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217 #define HAL_ICACHE_DISABLE() \
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218 { \
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219 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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220 chctr &= ~HAL_CHCTR_ICEN; \
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221 *HAL_CHCTR = chctr; \
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222 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
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223 }
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224
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225 // Query the state of the instruction cache
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226 #define HAL_ICACHE_IS_ENABLED(_state_) \
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227 { \
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228 register CYG_ADDRWORD chctr = *HAL_CHCTR; \
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229 _state_ = (0 != (chctr & HAL_CHCTR_ICEN)); \
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230 }
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231
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232 // Invalidate the entire cache
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233 #define HAL_ICACHE_INVALIDATE_ALL() \
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234 { \
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235 register CYG_ADDRWORD chctr; \
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236 register CYG_ADDRWORD state; \
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237 HAL_ICACHE_IS_ENABLED(state); \
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238 if (state) \
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239 HAL_ICACHE_DISABLE(); \
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240 chctr = *HAL_CHCTR; \
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241 chctr |= HAL_CHCTR_ICINV; \
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242 *HAL_CHCTR = chctr; \
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243 while( HAL_CHCTR_ICBUSY & *HAL_CHCTR ); \
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244 if (state) \
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245 HAL_ICACHE_ENABLE(); \
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246 }
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247
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248 // Synchronize the contents of the cache with memory.
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249 #define HAL_ICACHE_SYNC()
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250
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251 // Set the instruction cache refill burst size
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252 //#define HAL_ICACHE_BURST_SIZE(_size_)
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253
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254 // Load the contents of the given address range into the instruction cache
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255 // and then lock the cache so that it stays there.
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256 //#define HAL_ICACHE_LOCK(_base_, _size_)
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257
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258 // Undo a previous lock operation
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259 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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260
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261 // Unlock entire cache
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262 //#define HAL_ICACHE_UNLOCK_ALL()
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263
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264 //-----------------------------------------------------------------------------
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265 // Instruction cache line control
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266
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267 // Invalidate cache lines in the given range without writing to memory.
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268 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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269
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270 //-----------------------------------------------------------------------------
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271 #endif // ifndef CYGONCE_VAR_CACHE_H
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272 // End of var_cache.h