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annotate packages/hal/arm/ebsa285/current/src/ebsa285_misc.c @ 143:6b5f480c6929 ecos-sw-2000-12-08

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Merge from eCos master repository on 2000-12-08-02:09:36-GMT
author jlarmour
date Fri, 08 Dec 2000 03:30:06 +0000
parents 6ed91473a1cd
children d397fc472bcf
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1 //==========================================================================
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2 //
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3 // ebsa285_misc.c
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4 //
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5 // HAL misc board support code for StrongARM EBSA285-1
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: gthomas
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36 // Date: 1999-02-20
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37 // Purpose: HAL board support
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38 // Description: Implementations of HAL board interfaces
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //========================================================================*/
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43
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44 #include <pkgconf/hal.h>
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45 #include <pkgconf/system.h>
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46 #include CYGBLD_HAL_PLATFORM_H
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47 #include CYGHWR_MEMORY_LAYOUT_H
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48
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49 #include <cyg/infra/cyg_type.h> // base types
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50 #include <cyg/infra/cyg_trac.h> // tracing macros
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51 #include <cyg/infra/cyg_ass.h> // assertion macros
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52
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53 #include <cyg/hal/hal_io.h> // IO macros
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54 #include <cyg/hal/hal_if.h> // calling interface API
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55 #include <cyg/hal/hal_arch.h> // Register state info
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56 #include <cyg/hal/hal_diag.h>
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57 #include <cyg/hal/hal_intr.h> // Interrupt names
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58 #include <cyg/hal/hal_cache.h>
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59 #include <cyg/hal/hal_ebsa285.h> // Hardware definitions
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60
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61 #include <cyg/infra/diag.h> // diag_printf
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62
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63 /*
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64 * Toggle LED for debugging purposes.
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65 */
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66 /*
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67 * EBSA-285 Soft I/O Register
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68 */
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69 #define EBSA_285_SOFT_IO_REGISTER ((cyg_uint32 *)0x40012000)
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70
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71 /*
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72 * EBSA-285 Soft I/O Register Bit Field definitions
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73 */
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74 #define EBSA_285_SOFT_IO_TOGGLE 0x80
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75 #define EBSA_285_SOFT_IO_RED_LED 0x04
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76 #define EBSA_285_SOFT_IO_GREEN_LED 0x02
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77 #define EBSA_285_SOFT_IO_AMBER_LED 0x01
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78 #define EBSA_285_SOFT_IO_J9_9_10_MASK 0x40
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79 #define EBSA_285_SOFT_IO_J9_11_12_MASK 0x20
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80 #define EBSA_285_SOFT_IO_J9_13_14_MASK 0x10
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81 #define EBSA_285_SOFT_IO_SWITCH_L_MASK 0x0F
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82
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83 static void
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84 hal_bsp_mmu_init(int sdram_size);
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85
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86 // Some initialization has already been done before we get here.
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87 //
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88 // Set up the interrupt environment.
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89 // Set up the MMU so that we can use caches.
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90 // Enable caches.
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91 // - All done!
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92
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93
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94 void hal_hardware_init(void)
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95 {
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96 // Disable all interrupt sources:
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97 *SA110_IRQCONT_IRQENABLECLEAR = 0xffffffff;
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98 *SA110_IRQCONT_FIQENABLECLEAR = 0xffffffff; // including FIQ
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99 // Disable the timers
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100 *SA110_TIMER1_CONTROL = 0;
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101 *SA110_TIMER2_CONTROL = 0;
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102 *SA110_TIMER3_CONTROL = 0;
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103 *SA110_TIMER4_CONTROL = 0;
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104
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105 *SA110_TIMER1_CLEAR = 0; // Clear any pending interrupt
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106 *SA110_TIMER2_CLEAR = 0; // (Data: don't care)
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107 *SA110_TIMER3_CLEAR = 0;
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108 *SA110_TIMER4_CLEAR = 0;
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109
115
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110 // Let the timer run at a default rate (for delays)
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111 hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
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112
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113 // Set up MMU so that we can use caches
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114 hal_bsp_mmu_init( hal_dram_size );
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115
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116 // Enable caches
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117 HAL_DCACHE_ENABLE();
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118 HAL_ICACHE_ENABLE();
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119
110
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120 // Set up eCos/ROM interfaces
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121 hal_if_init();
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122 }
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123
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124 // -------------------------------------------------------------------------
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125 // MMU initialization:
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126
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127 static void
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128 hal_bsp_mmu_init(int sdram_size)
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129 {
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130 unsigned long ttb_base = ((unsigned long)0x4000); // could be external
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131 unsigned long i;
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132
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133 *EBSA_285_SOFT_IO_REGISTER = ~EBSA_285_SOFT_IO_RED_LED; // Red LED on
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134
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135
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136 // For if we assign the ttb base dynamically:
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137 // if ((ttb_base & ARM_TRANSLATION_TABLE_MASK) != ttb_base) {
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138 // // we cannot do this:
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139 // while ( 1 ) {
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140 // *EBSA_285_SOFT_IO_REGISTER = 0; // All LEDs on
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141 // for ( i = 100000; i > 0 ; i++ ) ;
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142 // *EBSA_285_SOFT_IO_REGISTER = 7; // All LEDs off
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143 // for ( i = 100000; i > 0 ; i++ ) ;
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144 //#ifdef CYG_HAL_STARTUP_RAM
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145 // return; // Do not bother looping forever...
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146 //#endif
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147 // }
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148 // }
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149
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150 /*
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151 * Set the TTB register
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152 */
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153 asm volatile ("mcr p15,0,%0,c2,c0,0"
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154 :
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155 : "r"(ttb_base)
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156 /*:*/
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157 );
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158 /*
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159 * Set the Domain Access Control Register
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160 */
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161 i = ARM_ACCESS_TYPE_MANAGER(0) |
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162 ARM_ACCESS_TYPE_NO_ACCESS(1) |
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163 ARM_ACCESS_TYPE_NO_ACCESS(2) |
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164 ARM_ACCESS_TYPE_NO_ACCESS(3) |
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165 ARM_ACCESS_TYPE_NO_ACCESS(4) |
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166 ARM_ACCESS_TYPE_NO_ACCESS(5) |
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167 ARM_ACCESS_TYPE_NO_ACCESS(6) |
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168 ARM_ACCESS_TYPE_NO_ACCESS(7) |
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169 ARM_ACCESS_TYPE_NO_ACCESS(8) |
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170 ARM_ACCESS_TYPE_NO_ACCESS(9) |
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171 ARM_ACCESS_TYPE_NO_ACCESS(10) |
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172 ARM_ACCESS_TYPE_NO_ACCESS(11) |
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173 ARM_ACCESS_TYPE_NO_ACCESS(12) |
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174 ARM_ACCESS_TYPE_NO_ACCESS(13) |
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175 ARM_ACCESS_TYPE_NO_ACCESS(14) |
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176 ARM_ACCESS_TYPE_NO_ACCESS(15);
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177
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178 asm volatile ("mcr p15,0,%0,c3,c0,0"
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179 :
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180 : "r"(i)
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181 /*:*/
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182 );
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183
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184 /*
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185 * First clear all TT entries - ie Set them to Faulting
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186 */
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187 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
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188
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189 /*
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190 * We only do direct mapping for the EBSA board. That is, all
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191 * virt_addr == phys_addr.
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192 */
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193
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194 /*
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195 * Actual Base = 0x000(00000)
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196 * Virtual Base = 0x000(00000)
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197 * Size = Max SDRAM
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198 * SDRAM
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199 */
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200 for (i = 0x000; i < (sdram_size >> 20); i++) {
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201 ARM_MMU_SECTION(ttb_base, i, i,
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202 ARM_CACHEABLE, ARM_BUFFERABLE,
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203 ARM_ACCESS_PERM_RW_RW);
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204 }
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205
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206 #ifdef CYGPKG_IO_PCI
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207 /*
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208 * Actual Base = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE
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209 * Virtual Base = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE
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210 * Size = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE
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211 * Memory accessible from PCI space. Overrides part of the above mapping.
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212 */
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213 for (i = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE >> 20;
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214 i < ((CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE+CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE) >> 20);
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215 i++) {
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216 ARM_MMU_SECTION(ttb_base, i, i,
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217 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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218 ARM_ACCESS_PERM_RW_RW);
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219 }
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220 #endif
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221
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222 /*
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223 * Actual Base = 0x400(00000)
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224 * Virtual Base = 0x400(00000)
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225 * Size = 1M
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226 * 21285 Registers
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227 *
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228 * Actual Base = 0x400(10000)
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229 * Virtual Base = 0x400(10000)
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230 * Size = 1M
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231 * Soft I/O port and XBus IO
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232 */
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233 ARM_MMU_SECTION(ttb_base, 0x400, 0x400,
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234 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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235 ARM_ACCESS_PERM_RW_RW);
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236
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237 /*
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238 * Actual Base = 0x410(00000) - 0x413(FFFFF)
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239 * Virtual Base = 0x410(00000) - 0x413(FFFFF)
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240 * Size = 4M
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241 * FLASH ROM
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242 */
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243 for (i = 0x410; i <= 0x413; i++) {
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244 ARM_MMU_SECTION(ttb_base, i, i,
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245 ARM_CACHEABLE, ARM_UNBUFFERABLE,
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246 ARM_ACCESS_PERM_RW_RW);
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247 }
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248
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249 /*
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250 * Actual Base = 0x420(00000)
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251 * Virtual Base = 0x420(00000)
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252 * Size = 1M
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253 * 21285 CSR Space
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254 */
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255 ARM_MMU_SECTION(ttb_base, 0x420, 0x420,
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256 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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257 ARM_ACCESS_PERM_RW_RW);
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258
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259 /*
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260 * Actual Base = 0x500(00000)-0x50F(FFFFF)
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261 * Virtual Base = 0x500(00000)-0x50F(FFFFF)
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262 * Size = 16M
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263 * Zeros (Cache Clean) Bank
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264 */
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265 for (i = 0x500; i <= 0x50F; i++) {
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266 ARM_MMU_SECTION(ttb_base, i, i,
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267 ARM_CACHEABLE, ARM_BUFFERABLE,
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268 ARM_ACCESS_PERM_RW_RW);
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269 }
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270
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271 /*
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272 * Actual Base = 0x780(00000)-0x78F(FFFFF)
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273 * Virtual Base = 0x780(00000)-0x78F(FFFFF)
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274 * Size = 16M
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275 * Outbound Write Flush
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276 */
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277 for (i = 0x780; i <= 0x78F; i++) {
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278 ARM_MMU_SECTION(ttb_base, i, i,
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279 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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280 ARM_ACCESS_PERM_RW_RW);
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281 }
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282
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283 /*
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284 * Actual Base = 0x790(00000)-0x7C0(FFFFF)
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285 * Virtual Base = 0x790(00000)-0x7C0(FFFFF)
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286 * Size = 65M
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287 * PCI IACK/Config/IO Space
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288 */
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289 for (i = 0x790; i <= 0x7C0; i++) {
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290 ARM_MMU_SECTION(ttb_base, i, i,
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291 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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292 ARM_ACCESS_PERM_RW_RW);
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293 }
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294
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295 /*
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296 * Actual Base = 0x800(00000) - 0xFFF(FFFFF)
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297 * Virtual Base = 0x800(00000) - 0xFFF(FFFFF)
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298 * Size = 2G
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299 * PCI Memory Space
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300 */
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301 for (i = 0x800; i <= 0xFFF; i++) {
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302 ARM_MMU_SECTION(ttb_base, i, i,
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303 ARM_UNCACHEABLE, ARM_BUFFERABLE,
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304 ARM_ACCESS_PERM_RW_RW);
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305 }
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306
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307 *EBSA_285_SOFT_IO_REGISTER = ~EBSA_285_SOFT_IO_AMBER_LED; // AmberLED on
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308
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309 }
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310
115
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311 /*------------------------------------------------------------------------*/
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312
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313 //
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314 // Memory layout
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315 //
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316
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317 externC cyg_uint8 *
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318 hal_arm_mem_real_region_top( cyg_uint8 *regionend )
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319 {
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320 CYG_ASSERT( hal_dram_size > 0, "Didn't detect DRAM size!" );
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321 CYG_ASSERT( hal_dram_size <= 256<<20,
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322 "More than 256MB reported - that can't be right" );
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323
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324 // is it the "normal" end of the DRAM region? If so, it should be
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325 // replaced by the real size
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326 if ( regionend ==
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327 ((cyg_uint8 *)CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE) ) {
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328 regionend = (cyg_uint8 *)CYGMEM_REGION_ram + hal_dram_size;
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329 }
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330 return regionend;
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331 } // hal_arm_mem_real_region_top()
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332
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333
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334
76
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335 // -------------------------------------------------------------------------
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336 static cyg_uint32 _period;
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337
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338 void hal_clock_initialize(cyg_uint32 period)
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339 {
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340 _period = period;
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341
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342 *SA110_TIMER3_CONTROL = 0; // Disable while we are setting up
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343
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344 *SA110_TIMER3_LOAD = period; // Reload value
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345
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346 *SA110_TIMER3_CLEAR = 0; // Clear any pending interrupt
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347 // (Data: don't care)
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348
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349 *SA110_TIMER3_CONTROL = 0x000000cc; // Enable, Periodic (auto-reload),
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350 // External clock (3.68MHz on irq_in_l[2] for Timer 3)
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351
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352 *SA110_TIMER3_CLEAR = 0; // Clear any pending interrupt again
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353
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354 // That's all.
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355 }
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356
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357 // This routine is called during a clock interrupt.
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358
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359 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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360 {
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361 *SA110_TIMER3_CLEAR = period; // Clear any pending interrupt (Data: don't care)
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362 }
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363
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364 // Read the current value of the clock, returning the number of hardware
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365 // "ticks" that have occurred (i.e. how far away the current value is from
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366 // the start)
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367
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368 void hal_clock_read(cyg_uint32 *pvalue)
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369 {
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370 *pvalue = (cyg_uint32)(_period) - *SA110_TIMER3_VALUE;
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371 }
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372
115
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373 //
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374 // Delay for some number of micro-seconds
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375 //
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376 void hal_delay_us(cyg_int32 usecs)
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377 {
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378 int diff, diff2;
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379 cyg_uint32 val1, val2;
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380 while (usecs-- > 0) {
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381 diff = 0;
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382 while (diff < 3) {
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383 val1 = *SA110_TIMER3_VALUE;
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384 while ((val2 = *SA110_TIMER3_VALUE) == val1) ;
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385 if (*SA110_TIMER3_LOAD) {
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386 // A kernel is running, the counter may get reset as we watch
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387 diff2 = val2 - val1;
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388 if (diff2 < 0) diff2 += *SA110_TIMER3_LOAD;
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389 diff += diff2;
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390 } else {
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391 diff += val2 - val1;
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392 }
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393 }
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394 }
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395 }
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396
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397 // -------------------------------------------------------------------------
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398
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399 // This routine is called to respond to a hardware interrupt (IRQ). It
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400 // should interrogate the hardware and return the IRQ vector number.
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401 int hal_IRQ_handler(void)
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402 {
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403 int sources;
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404 int index;
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405
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406 #if 0 // test FIQ and print alert if active - really for debugging
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407 sources = *SA110_IRQCONT_FIQSTATUS;
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408 if ( 0 != sources )
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409 diag_printf( "FIQ source active!!! - fiqstatus %08x irqstatus %08x\n",
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410 sources, *SA110_IRQCONT_IRQSTATUS );
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411 else
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412 #endif // Scan FIQ sources also
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413
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414 sources = *SA110_IRQCONT_IRQSTATUS;
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415
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416 // if we come to support FIQ properly...
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417 // if ( 0 == sources )
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418 // sources = *SA110_IRQCONT_FIQSTATUS;
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419
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420 // Nothing wrong with scanning them in the order provided...
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421 // and it'll make the serial device steal fewer cycles.
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422 // So, knowing this is an ARM:
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423 if ( sources & 0xff )
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424 index = 0;
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425 else if ( sources & 0xff00 )
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426 index = 8;
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427 else if ( sources & 0xff0000 )
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428 index = 16;
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429 else // if ( sources & 0xff000000 )
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430 index = 24;
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431
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432 do {
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433 if ( (1 << index) & sources )
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434 return index;
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435 index++;
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436 } while ( index & 7 );
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437
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438 return CYGNUM_HAL_INTERRUPT_reserved0; // This shouldn't happen!
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439 }
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440
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441 //
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442 // Interrupt control
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443 //
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444
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445 void hal_interrupt_mask(int vector)
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446 {
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447 *SA110_IRQCONT_IRQENABLECLEAR = 1 << vector;
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448 }
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449
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450 void hal_interrupt_unmask(int vector)
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451 {
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452 *SA110_IRQCONT_IRQENABLESET = 1 << vector;
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453 }
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454
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455 void hal_interrupt_acknowledge(int vector)
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456 {
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457 // Nothing to do here.
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458 }
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459
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460 void hal_interrupt_configure(int vector, int level, int up)
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461 {
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462 // No interrupts are configurable on this hardware
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463 }
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464
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465 void hal_interrupt_set_level(int vector, int level)
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466 {
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467 // No interrupts are configurable on this hardware
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468 }
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469
143
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470 #include CYGHWR_MEMORY_LAYOUT_H
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471 typedef void code_fun(void);
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472 void ebsa285_program_new_stack(void *func)
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473 {
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474 register CYG_ADDRESS stack_ptr asm("sp");
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475 register CYG_ADDRESS old_stack asm("r4");
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476 register code_fun *new_func asm("r0");
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477 old_stack = stack_ptr;
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478 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
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479 new_func = (code_fun*)func;
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480 new_func();
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481 stack_ptr = old_stack;
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482 return;
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483 }
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484
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485 /*------------------------------------------------------------------------*/
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486 // EOF ebsa285_misc.c