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annotate packages/hal/arm/arch/current/include/hal_arch.h @ 66:bf00f99aec69 ecos-sw-2000-02-02
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| author | jlarmour |
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| date | Wed, 02 Feb 2000 19:57:02 +0000 |
| parents | c38311975d4f |
| children | 435cced73e2f |
| rev | line source |
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| 2 | 1 #ifndef CYGONCE_HAL_ARCH_H |
| 2 #define CYGONCE_HAL_ARCH_H | |
| 3 | |
| 4 //========================================================================== | |
| 5 // | |
| 6 // hal_arch.h | |
| 7 // | |
| 8 // Architecture specific abstractions | |
| 9 // | |
| 10 //========================================================================== | |
| 11 //####COPYRIGHTBEGIN#### | |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Red Hat eCos Public License |
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15 // Version 1.1 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://www.redhat.com/ |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Configurable Operating System, |
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25 // released September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Red Hat. |
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28 // Portions created by Red Hat are |
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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30 // All Rights Reserved. |
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31 // ------------------------------------------- |
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32 // |
| 2 | 33 //####COPYRIGHTEND#### |
| 34 //========================================================================== | |
| 35 //#####DESCRIPTIONBEGIN#### | |
| 36 // | |
| 37 // Author(s): nickg, gthomas | |
| 38 // Contributors: nickg, gthomas | |
| 39 // Date: 1999-02-20 | |
| 40 // Purpose: Define architecture abstractions | |
| 41 // Usage: #include <cyg/hal/hal_arch.h> | |
| 42 | |
| 43 // | |
| 44 //####DESCRIPTIONEND#### | |
| 45 // | |
| 46 //========================================================================== | |
| 47 | |
| 48 #include <pkgconf/hal.h> // To decide on stack usage | |
| 49 #include <cyg/infra/cyg_type.h> | |
| 50 | |
| 51 // | |
| 52 // CPSR Register defines | |
| 53 // | |
| 54 | |
| 55 #define CPSR_IRQ_DISABLE 0x80 // IRQ disabled when =1 | |
| 56 #define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 | |
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57 #define CPSR_FIQ_MODE 0x11 |
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58 #define CPSR_IRQ_MODE 0x12 |
| 2 | 59 #define CPSR_SUPERVISOR_MODE 0x13 |
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60 #define CPSR_UNDEF_MODE 0x1B |
| 2 | 61 |
| 62 #define CPSR_MODE_BITS 0x1F | |
| 63 | |
| 64 #define CPSR_INITIAL (CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) | |
| 65 #define CPSR_THREAD_INITIAL (CPSR_SUPERVISOR_MODE) | |
| 66 | |
| 67 //-------------------------------------------------------------------------- | |
| 68 // Processor saved states: | |
| 69 // The layout of this structure is also defined in "arm.inc", for assembly | |
| 70 // code, which will be generated automatically if this file changes. | |
| 71 | |
| 72 #define HAL_THREAD_CONTEXT_FIRST 0 | |
| 73 #define HAL_THREAD_CONTEXT_R0 (0-HAL_THREAD_CONTEXT_FIRST) | |
| 74 #define HAL_THREAD_CONTEXT_R4 (4-HAL_THREAD_CONTEXT_FIRST) | |
| 75 #define HAL_THREAD_CONTEXT_R10 (10-HAL_THREAD_CONTEXT_FIRST) | |
| 76 #define HAL_THREAD_CONTEXT_LAST 10 | |
| 77 #define HAL_NUM_THREAD_CONTEXT_REGS (HAL_THREAD_CONTEXT_LAST - \ | |
| 78 HAL_THREAD_CONTEXT_FIRST+1) | |
| 79 | |
| 80 // It seems that r0-r3,r12 are considered scratch by function calls | |
| 81 | |
| 82 typedef struct | |
| 83 { | |
| 84 // These are common to all saved states | |
| 85 cyg_uint32 d[HAL_NUM_THREAD_CONTEXT_REGS] ; // Data regs (r0..r10) | |
| 86 cyg_uint32 fp; // (r11) Frame pointer | |
| 87 cyg_uint32 sp; // (r13) Stack pointer | |
| 88 cyg_uint32 lr; // (r14) Link Reg | |
| 89 cyg_uint32 pc; // (r15) PC place holder | |
| 90 // (never used) | |
| 91 cyg_uint32 cpsr; // Condition Reg | |
| 92 cyg_uint32 ip; // (r12) Previous stack | |
| 93 // pointer | |
| 94 // These are only saved for exceptions and interrupts | |
| 95 cyg_uint32 vector; // Vector number | |
| 96 cyg_uint32 msr; // Machine State Reg | |
| 97 | |
| 98 } HAL_SavedRegisters; | |
| 99 | |
| 100 //------------------------------------------------------------------------- | |
| 101 // Exception handling function. | |
| 102 // This function is defined by the kernel according to this prototype. It is | |
| 103 // invoked from the HAL to deal with any CPU exceptions that the HAL does | |
| 104 // not want to deal with itself. It usually invokes the kernel's exception | |
| 105 // delivery mechanism. | |
| 106 | |
| 107 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); | |
| 108 | |
| 109 //------------------------------------------------------------------------- | |
| 110 // Bit manipulation macros | |
| 111 | |
| 112 externC int hal_lsbindex(int); | |
| 113 externC int hal_msbindex(int); | |
| 114 | |
| 115 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask) | |
| 116 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask) | |
| 117 | |
| 118 //------------------------------------------------------------------------- | |
| 119 // Context Initialization | |
| 120 // Initialize the context of a thread. | |
| 121 // Arguments: | |
| 122 // _sparg_ name of variable containing current sp, will be changed to new sp | |
| 123 // _thread_ thread object address, passed as argument to entry point | |
| 124 // _entry_ entry point address. | |
| 125 // _id_ bit pattern used in initializing registers, for debugging. | |
| 126 | |
| 127 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ | |
| 128 CYG_MACRO_START \ | |
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129 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_) &~15; \ |
| 2 | 130 register HAL_SavedRegisters *_regs_; \ |
| 131 int _i_; \ | |
| 132 _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \ | |
| 133 for( _i_ = HAL_THREAD_CONTEXT_FIRST; _i_ <= HAL_THREAD_CONTEXT_LAST; \ | |
| 134 _i_++ ) \ | |
| 135 (_regs_)->d[_i_] = (_id_)|_i_; \ | |
| 136 (_regs_)->d[00] = (CYG_WORD)(_thread_); /* R0 = arg1 = thread ptr */ \ | |
| 137 (_regs_)->sp = (CYG_WORD)(_sp_); /* SP = top of stack */ \ | |
| 138 (_regs_)->lr = (CYG_WORD)(_entry_); /* LR = entry point */ \ | |
| 139 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = [initial] entry point */\ | |
| 140 (_regs_)->cpsr = (CPSR_THREAD_INITIAL); /* PSR = Interrupt enabled */ \ | |
| 141 _sparg_ = (CYG_ADDRESS)_regs_; \ | |
| 142 CYG_MACRO_END | |
| 143 | |
| 144 //-------------------------------------------------------------------------- | |
| 145 // Context switch macros. | |
| 146 // The arguments are pointers to locations where the stack pointer | |
| 147 // of the current thread is to be stored, and from where the sp of the | |
| 148 // next thread is to be fetched. | |
| 149 | |
| 150 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); | |
| 151 externC void hal_thread_load_context( CYG_ADDRESS to ) | |
| 152 __attribute__ ((noreturn)); | |
| 153 | |
| 154 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ | |
| 155 hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \ | |
| 156 (CYG_ADDRESS)_fspptr_); | |
| 157 | |
| 158 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ | |
| 159 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); | |
| 160 | |
| 161 //-------------------------------------------------------------------------- | |
| 162 // Execution reorder barrier. | |
| 163 // When optimizing the compiler can reorder code. In multithreaded systems | |
| 164 // where the order of actions is vital, this can sometimes cause problems. | |
| 165 // This macro may be inserted into places where reordering should not happen. | |
| 166 | |
| 167 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) | |
| 168 | |
| 169 //-------------------------------------------------------------------------- | |
| 170 // Breakpoint support | |
| 171 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen | |
| 172 // if executed. | |
| 173 // HAL_BREAKINST is the value of the breakpoint instruction and | |
| 174 // HAL_BREAKINST_SIZE is its size in bytes. | |
| 175 | |
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176 #define _stringify1(__arg) #__arg |
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177 #define _stringify(__arg) _stringify1(__arg) |
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178 |
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179 #define HAL_BREAKINST_ARM 0xE7FFDEFE |
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180 #define HAL_BREAKINST_ARM_SIZE 4 |
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181 |
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182 #define HAL_BREAKPOINT(_label_) \ |
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183 asm volatile (" .globl " #_label_ ";" \ |
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184 #_label_":" \ |
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185 " .word " _stringify(HAL_BREAKINST_ARM) \ |
| 2 | 186 ); |
| 187 | |
| 188 //#define HAL_BREAKINST {0xFE, 0xDE, 0xFF, 0xE7} | |
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189 #define HAL_BREAKINST HAL_BREAKINST_ARM |
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190 #define HAL_BREAKINST_SIZE HAL_BREAKINST_ARM_SIZE |
| 2 | 191 |
| 192 //-------------------------------------------------------------------------- | |
| 193 // Thread register state manipulation for GDB support. | |
| 194 | |
| 195 // GDB expects the registers in this structure: | |
| 196 // r0..r10, fp, ip, sp, lr, pc - 4 bytes each | |
| 197 // f0..f7 - 12 bytes each (N/A on ARM7) | |
| 198 // fps - 4 bytes (N/A on ARM7) | |
| 199 // ps - 4 bytes | |
| 200 | |
| 201 // Translate a stack pointer as saved by the thread context macros above into | |
| 202 // a pointer to a HAL_SavedRegisters structure. | |
| 203 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ | |
| 204 (_regs_) = (HAL_SavedRegisters *)(_sp_) | |
| 205 | |
| 206 // Copy a set of registers from a HAL_SavedRegisters structure into a | |
| 207 // GDB ordered array. | |
| 208 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ | |
| 209 CYG_MACRO_START \ | |
| 210 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ | |
| 211 int _i_; \ | |
| 212 \ | |
| 213 for( _i_ = 0; _i_ <= 10; _i_++ ) \ | |
| 214 _regval_[_i_] = (_regs_)->d[_i_]; \ | |
| 215 \ | |
| 216 _regval_[11] = (_regs_)->fp; \ | |
| 217 _regval_[12] = (_regs_)->ip; \ | |
| 218 _regval_[13] = (_regs_)->sp; \ | |
| 219 _regval_[14] = (_regs_)->lr; \ | |
| 220 _regval_[15] = (_regs_)->pc; \ | |
| 221 _regval_[25] = (_regs_)->cpsr; \ | |
| 222 for( _i_ = 0; _i_ < 8; _i_++ ) \ | |
| 223 _regval_[_i_+16] = 0; \ | |
| 224 CYG_MACRO_END | |
| 225 | |
| 226 // Copy a GDB ordered array into a HAL_SavedRegisters structure. | |
| 227 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ | |
| 228 CYG_MACRO_START \ | |
| 229 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ | |
| 230 int _i_; \ | |
| 231 \ | |
| 232 for( _i_ = 0; _i_ <= 10; _i_++ ) \ | |
| 233 (_regs_)->d[_i_] = _regval_[_i_]; \ | |
| 234 \ | |
| 235 (_regs_)->fp = _regval_[11]; \ | |
| 236 (_regs_)->ip = _regval_[12]; \ | |
| 237 (_regs_)->sp = _regval_[13]; \ | |
| 238 (_regs_)->lr = _regval_[14]; \ | |
| 239 (_regs_)->pc = _regval_[15]; \ | |
| 240 (_regs_)->cpsr = _regval_[25]; \ | |
| 241 CYG_MACRO_END | |
| 242 | |
| 243 //-------------------------------------------------------------------------- | |
| 244 // HAL setjmp | |
| 245 | |
| 246 #define CYGARC_JMP_BUF_SIZE 16 // Actually 11, but some room left over | |
| 247 | |
| 248 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; | |
| 249 | |
| 250 externC int hal_setjmp(hal_jmp_buf env); | |
| 251 externC void hal_longjmp(hal_jmp_buf env, int val); | |
| 252 | |
| 253 | |
| 254 //-------------------------------------------------------------------------- | |
| 255 // Idle thread code. | |
| 256 // This macro is called in the idle thread loop, and gives the HAL the | |
| 257 // chance to insert code. Typical idle thread behaviour might be to halt the | |
| 258 // processor. | |
| 259 | |
| 260 externC void hal_idle_thread_action(cyg_uint32 loop_count); | |
| 261 | |
| 262 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) | |
| 263 | |
| 264 //--------------------------------------------------------------------------- | |
| 265 | |
| 266 // Minimal and sensible stack sizes: the intention is that applications | |
| 267 // will use these to provide a stack size in the first instance prior to | |
| 268 // proper analysis. Idle thread stack should be this big. | |
| 269 | |
| 270 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. | |
| 271 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. | |
| 272 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! | |
| 273 | |
| 274 // This is not a config option because it should not be adjusted except | |
| 275 // under "enough rope" sort of disclaimers. | |
| 276 | |
| 277 // A minimal, optimized stack frame, rounded up - no autos | |
| 278 #define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 20) | |
| 279 | |
| 280 // Stack needed for a context switch: this is implicit in the estimate for | |
| 281 // interrupts so not explicitly used below: | |
| 282 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 20) | |
| 283 | |
| 284 // Interrupt + call to ISR, interrupt_end() and the DSR | |
| 285 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ | |
| 286 ((4 * 20) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) | |
| 287 | |
| 288 // Space for the maximum number of nested interrupts, plus room to call functions | |
| 289 #define CYGNUM_HAL_MAX_INTERRUPT_NESTING 4 | |
| 290 | |
| 291 #define CYGNUM_HAL_STACK_SIZE_MINIMUM \ | |
| 292 (CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \ | |
| 293 2 * CYGNUM_HAL_STACK_FRAME_SIZE) | |
| 294 | |
| 295 #define CYGNUM_HAL_STACK_SIZE_TYPICAL \ | |
| 296 (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ | |
| 297 16 * CYGNUM_HAL_STACK_FRAME_SIZE) | |
| 298 | |
| 299 //----------------------------------------------------------------------------- | |
| 300 | |
| 301 #endif // CYGONCE_HAL_ARCH_H | |
| 302 // End of hal_arch.h |