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annotate packages/hal/mn10300/am31/current/include/var_intr.h @ 64:c38311975d4f ecos-sw-2000-01-28

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Merge from eCos master repository on 2000-01-28-04:28:11-GMT
author jlarmour
date Fri, 28 Jan 2000 04:59:39 +0000
parents 641b639be825
children bf00f99aec69
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1 #ifndef CYGONCE_HAL_VAR_INTR_H
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2 #define CYGONCE_HAL_VAR_INTR_H
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3
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4 //==========================================================================
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5 //
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6 // var_intr.h
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7 //
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8 // AM31 Interrupt and clock support
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9 //
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10 //==========================================================================
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11 //####COPYRIGHTBEGIN####
64
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //==========================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg
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38 // Contributors: nickg, jskov,
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39 // gthomas, jlarmour
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40 // Date: 1999-02-16
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41 // Purpose: AM31 Interrupt support
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42 // Description: The macros defined here provide the HAL APIs for handling
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43 // interrupts and the clock for AM31 variants of the MN10300
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44 // architecture.
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45 //
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46 // Usage:
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47 // #include <cyg/hal/var_intr.h>
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48 // ...
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49 //
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50 //
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51 //####DESCRIPTIONEND####
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52 //
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53 //==========================================================================
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54
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55 #include <pkgconf/hal.h>
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56
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57 #include <cyg/infra/cyg_type.h>
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58
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59 #include <cyg/hal/plf_intr.h>
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60
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61 //--------------------------------------------------------------------------
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62
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63 // The MN10300 has a somewhat complex interrupt structure. Besides the
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64 // reset and NMI vectors there are seven maskable interrupt vectors
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65 // which must point to code in the 64k starting at 0x40000000. There
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66 // are also 25 Interrupt control groups, each of which can have 4
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67 // interrupt lines attached, for a theoretical total of 100 interrupts
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68 // (!). Some of these are dedicated to specific devices, other to
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69 // external pins, and others are not connected to anything, resulting
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70 // in only 45 that can actually be delivered. Each control group may
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71 // be assigned one of seven interrupt levels, and is delivered to the
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72 // corresponding vector. Software can then use a register to determine
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73 // the delivering group and detect from there which interrupt has been
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74 // delivered.
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75 //
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76 // The approach we will adopt at present is for the code attached to
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77 // each vector to save state and jump via a table to a VSR. The
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78 // default VSR will fully decode the delivered interrupt into a table
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79 // of isr/data/object entries. VSR replacement will operate on the
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80 // first level indirection table rather than the hardware
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81 // vectors. This is the fastest mechanism, however it needs 100*3*4 +
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82 // 7*4 = 1228 bytes for the tables.
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83 //
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84
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85 //--------------------------------------------------------------------------
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86 // Interrupt vectors.
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87
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88 // The level-specific hardware vectors
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89 // These correspond to VSRs and are the values to use for HAL_VSR_GET/SET
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90 #define CYGNUM_HAL_VECTOR_0 0
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91 #define CYGNUM_HAL_VECTOR_1 1
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92 #define CYGNUM_HAL_VECTOR_2 2
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93 #define CYGNUM_HAL_VECTOR_3 3
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94 #define CYGNUM_HAL_VECTOR_4 4
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95 #define CYGNUM_HAL_VECTOR_5 5
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96 #define CYGNUM_HAL_VECTOR_6 6
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97 #define CYGNUM_HAL_VECTOR_NMI_ENTRY 7
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98 #define CYGNUM_HAL_VECTOR_TRAP 8
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99 #define CYGNUM_HAL_VECTOR_NMI 9
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100 #define CYGNUM_HAL_VECTOR_WATCHDOG 10
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101 #define CYGNUM_HAL_VECTOR_SYSTEM_ERROR 11
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102
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103 #define CYGNUM_HAL_VSR_MIN 0
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104 #define CYGNUM_HAL_VSR_MAX 11
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105 #define CYGNUM_HAL_VSR_COUNT 12
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106
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107 // Exception numbers. These are the values used when passed out to an
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108 // external exception handler using cyg_hal_deliver_exception()
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109
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110 #define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI
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111 #define CYGNUM_HAL_EXCEPTION_WATCHDOG CYGNUM_HAL_VECTOR_WATCHDOG
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112 #define CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR CYGNUM_HAL_VECTOR_SYSTEM_ERROR
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113
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114 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR
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115
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116 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VSR_MIN
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117 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
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118 #define CYGNUM_HAL_EXCEPTION_COUNT CYGNUM_HAL_VSR_COUNT
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119
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120 // The decoded interrupts
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121
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122 #define CYGNUM_HAL_INTERRUPT_NMIRQ 0
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123 #define CYGNUM_HAL_INTERRUPT_WATCHDOG 1
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124 #define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR 2
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125 #define CYGNUM_HAL_INTERRUPT_RESERVED_3 3
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126
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127 #define CYGNUM_HAL_INTERRUPT_RESERVED_4 4
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128 #define CYGNUM_HAL_INTERRUPT_RESERVED_5 5
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129 #define CYGNUM_HAL_INTERRUPT_RESERVED_6 6
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130 #define CYGNUM_HAL_INTERRUPT_RESERVED_7 7
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131
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132 #define CYGNUM_HAL_INTERRUPT_TIMER_0 8
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133 #define CYGNUM_HAL_INTERRUPT_RESERVED_9 9
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134 #define CYGNUM_HAL_INTERRUPT_RESERVED_10 10
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135 #define CYGNUM_HAL_INTERRUPT_RESERVED_11 11
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136
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137 #define CYGNUM_HAL_INTERRUPT_TIMER_1 12
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138 #define CYGNUM_HAL_INTERRUPT_RESERVED_13 13
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139 #define CYGNUM_HAL_INTERRUPT_RESERVED_14 14
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140 #define CYGNUM_HAL_INTERRUPT_RESERVED_15 15
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141
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142 #define CYGNUM_HAL_INTERRUPT_TIMER_2 16
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143 #define CYGNUM_HAL_INTERRUPT_RESERVED_17 17
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144 #define CYGNUM_HAL_INTERRUPT_RESERVED_18 18
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145 #define CYGNUM_HAL_INTERRUPT_RESERVED_19 19
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146
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147 #define CYGNUM_HAL_INTERRUPT_TIMER_3 20
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148 #define CYGNUM_HAL_INTERRUPT_RESERVED_21 21
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149 #define CYGNUM_HAL_INTERRUPT_RESERVED_22 22
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150 #define CYGNUM_HAL_INTERRUPT_RESERVED_23 23
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151
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152 #define CYGNUM_HAL_INTERRUPT_TIMER_4 24
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153 #define CYGNUM_HAL_INTERRUPT_RESERVED_25 25
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154 #define CYGNUM_HAL_INTERRUPT_RESERVED_26 26
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155 #define CYGNUM_HAL_INTERRUPT_RESERVED_27 27
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156
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157 #define CYGNUM_HAL_INTERRUPT_TIMER_5 28
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158 #define CYGNUM_HAL_INTERRUPT_RESERVED_29 29
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159 #define CYGNUM_HAL_INTERRUPT_RESERVED_30 30
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160 #define CYGNUM_HAL_INTERRUPT_RESERVED_31 31
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161
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162 #define CYGNUM_HAL_INTERRUPT_TIMER_6 32
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163 #define CYGNUM_HAL_INTERRUPT_RESERVED_33 33
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164 #define CYGNUM_HAL_INTERRUPT_RESERVED_34 34
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165 #define CYGNUM_HAL_INTERRUPT_RESERVED_35 35
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166
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167 #define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_A 36
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168 #define CYGNUM_HAL_INTERRUPT_RESERVED_37 37
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169 #define CYGNUM_HAL_INTERRUPT_RESERVED_38 38
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170 #define CYGNUM_HAL_INTERRUPT_RESERVED_39 39
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171
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172 #define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_B 40
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173 #define CYGNUM_HAL_INTERRUPT_RESERVED_41 41
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174 #define CYGNUM_HAL_INTERRUPT_RESERVED_42 42
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175 #define CYGNUM_HAL_INTERRUPT_RESERVED_43 43
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176
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177 #define CYGNUM_HAL_INTERRUPT_RESERVED_44 44
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178 #define CYGNUM_HAL_INTERRUPT_RESERVED_45 45
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179 #define CYGNUM_HAL_INTERRUPT_RESERVED_46 46
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180 #define CYGNUM_HAL_INTERRUPT_RESERVED_47 47
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181
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182 #define CYGNUM_HAL_INTERRUPT_DMA0 48
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183 #define CYGNUM_HAL_INTERRUPT_RESERVED_49 49
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184 #define CYGNUM_HAL_INTERRUPT_RESERVED_50 50
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185 #define CYGNUM_HAL_INTERRUPT_RESERVED_51 51
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186
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187 #define CYGNUM_HAL_INTERRUPT_DMA1 52
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188 #define CYGNUM_HAL_INTERRUPT_RESERVED_53 53
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189 #define CYGNUM_HAL_INTERRUPT_RESERVED_54 54
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190 #define CYGNUM_HAL_INTERRUPT_RESERVED_55 55
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191
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192 #define CYGNUM_HAL_INTERRUPT_DMA2 56
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193 #define CYGNUM_HAL_INTERRUPT_RESERVED_57 57
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194 #define CYGNUM_HAL_INTERRUPT_RESERVED_58 58
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195 #define CYGNUM_HAL_INTERRUPT_RESERVED_59 59
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196
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197 #define CYGNUM_HAL_INTERRUPT_DMA3 60
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198 #define CYGNUM_HAL_INTERRUPT_RESERVED_61 61
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199 #define CYGNUM_HAL_INTERRUPT_RESERVED_62 62
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200 #define CYGNUM_HAL_INTERRUPT_RESERVED_63 63
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201
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202 #define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX 64
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203 #define CYGNUM_HAL_INTERRUPT_RESERVED_65 65
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204 #define CYGNUM_HAL_INTERRUPT_RESERVED_66 66
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205 #define CYGNUM_HAL_INTERRUPT_RESERVED_67 67
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206
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207 #define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX 68
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208 #define CYGNUM_HAL_INTERRUPT_RESERVED_69 69
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209 #define CYGNUM_HAL_INTERRUPT_RESERVED_70 70
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210 #define CYGNUM_HAL_INTERRUPT_RESERVED_71 71
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211
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212 #define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX 72
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213 #define CYGNUM_HAL_INTERRUPT_RESERVED_73 73
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214 #define CYGNUM_HAL_INTERRUPT_RESERVED_74 74
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215 #define CYGNUM_HAL_INTERRUPT_RESERVED_75 75
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216
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217 #define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX 76
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218 #define CYGNUM_HAL_INTERRUPT_RESERVED_77 77
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219 #define CYGNUM_HAL_INTERRUPT_RESERVED_78 78
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220 #define CYGNUM_HAL_INTERRUPT_RESERVED_79 79
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221
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222 #define CYGNUM_HAL_INTERRUPT_SERIAL_2_RX 80
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223 #define CYGNUM_HAL_INTERRUPT_RESERVED_81 81
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224 #define CYGNUM_HAL_INTERRUPT_RESERVED_82 82
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225 #define CYGNUM_HAL_INTERRUPT_RESERVED_83 83
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226
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227 #define CYGNUM_HAL_INTERRUPT_SERIAL_2_TX 84
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228 #define CYGNUM_HAL_INTERRUPT_RESERVED_85 85
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229 #define CYGNUM_HAL_INTERRUPT_RESERVED_86 86
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230 #define CYGNUM_HAL_INTERRUPT_RESERVED_87 87
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231
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232 #define CYGNUM_HAL_INTERRUPT_RESERVED_88 88
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233 #define CYGNUM_HAL_INTERRUPT_RESERVED_89 89
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234 #define CYGNUM_HAL_INTERRUPT_RESERVED_90 90
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235 #define CYGNUM_HAL_INTERRUPT_RESERVED_91 91
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236
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237 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_0 92
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238 #define CYGNUM_HAL_INTERRUPT_RESERVED_93 93
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239 #define CYGNUM_HAL_INTERRUPT_RESERVED_94 94
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240 #define CYGNUM_HAL_INTERRUPT_RESERVED_95 95
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241
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242 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_1 96
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243 #define CYGNUM_HAL_INTERRUPT_RESERVED_97 97
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244 #define CYGNUM_HAL_INTERRUPT_RESERVED_98 98
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245 #define CYGNUM_HAL_INTERRUPT_RESERVED_99 99
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246
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247 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_2 100
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248 #define CYGNUM_HAL_INTERRUPT_RESERVED_101 101
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249 #define CYGNUM_HAL_INTERRUPT_RESERVED_102 102
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250 #define CYGNUM_HAL_INTERRUPT_RESERVED_103 103
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251
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252 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_3 104
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253 #define CYGNUM_HAL_INTERRUPT_RESERVED_105 105
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254 #define CYGNUM_HAL_INTERRUPT_RESERVED_106 106
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255 #define CYGNUM_HAL_INTERRUPT_RESERVED_107 107
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256
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257 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_4 108
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258 #define CYGNUM_HAL_INTERRUPT_RESERVED_109 109
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259 #define CYGNUM_HAL_INTERRUPT_RESERVED_110 110
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260 #define CYGNUM_HAL_INTERRUPT_RESERVED_111 111
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261
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262 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_5 112
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263 #define CYGNUM_HAL_INTERRUPT_RESERVED_113 113
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264 #define CYGNUM_HAL_INTERRUPT_RESERVED_114 114
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265 #define CYGNUM_HAL_INTERRUPT_RESERVED_115 115
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266
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267 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_6 116
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268 #define CYGNUM_HAL_INTERRUPT_RESERVED_117 117
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269 #define CYGNUM_HAL_INTERRUPT_RESERVED_118 118
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270 #define CYGNUM_HAL_INTERRUPT_RESERVED_119 119
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271
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272 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_7 120
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273 #define CYGNUM_HAL_INTERRUPT_RESERVED_121 121
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274 #define CYGNUM_HAL_INTERRUPT_RESERVED_122 122
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275 #define CYGNUM_HAL_INTERRUPT_RESERVED_123 123
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276
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277 #define CYGNUM_HAL_ISR_MIN 0
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278 #define CYGNUM_HAL_ISR_MAX 123
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279
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280 #define CYGNUM_HAL_ISR_COUNT (3+((CYGNUM_HAL_ISR_MAX+1)/4))
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281
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282 // The vector used by the Real time clock
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283
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284 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_5
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285
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286 //--------------------------------------------------------------------------
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287 // Interrupt vector translation.
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288
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289 #if !defined(HAL_TRANSLATE_VECTOR) && !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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290
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291 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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292 _index_ = (((_vector_)<=CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR) ? \
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293 (_vector_) : \
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294 (((_vector_)>>2)+CYGNUM_HAL_INTERRUPT_RESERVED_3))
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295
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296 #endif
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297
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298 //--------------------------------------------------------------------------
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299 // MN10300 specific version of HAL_INTERRUPT_CONFIGURE
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300
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301 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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302 CYG_MACRO_START \
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303 if( _vector_ >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 ) \
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304 { \
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305 cyg_uint32 _v_ = _vector_; \
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306 cyg_uint16 _val_ = 0; \
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307 cyg_uint16 _reg_; \
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308 \
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309 /* adjust vector to bit offset in EXTMD */ \
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310 _v_ -= CYGNUM_HAL_INTERRUPT_EXTERNAL_0; \
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311 _v_ >>= 1; \
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312 \
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313 /* set bits according to requirements */ \
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314 if( _up_ ) _val_ |= 1; \
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315 if( !(_level_) ) _val_ |= 2; \
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316 \
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317 /* get EXTMD */ \
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318 _reg_ = mn10300_interrupt_control[0x180>>1]; \
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319 \
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320 /* clear old value and set new */ \
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321 _reg_ &= ~(3<<_v_); \
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322 _reg_ |= _val_<<_v_; \
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323 \
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324 /* restore EXTMD */ \
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325 mn10300_interrupt_control[0x180>>1] = _reg_; \
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326 } \
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327 CYG_MACRO_END
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328
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329 #define HAL_INTERRUPT_CONFIGURE_DEFINED
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330
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331 //--------------------------------------------------------------------------
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332 // Timer control registers.
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333 // On the mn103002 we use timers 4 and 5
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334
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335 #define TIMER4_CR 0x340010a0
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336 #define TIMER4_BR 0x34001090
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337 #define TIMER4_MD 0x34001080
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338
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339 #define TIMER5_CR 0x340010a2
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340 #define TIMER5_BR 0x34001092
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341 #define TIMER5_MD 0x34001082
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342
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343 #define TIMER_CR TIMER5_CR
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344 #define TIMER_BR TIMER5_BR
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345 #define TIMER_MD TIMER5_MD
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346
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347 #define TIMER0_MD 0x34001000
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348 #define TIMER0_BR 0x34001010
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349 #define TIMER0_CR 0x34001020
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350
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351 //--------------------------------------------------------------------------
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352 // Clock control.
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353
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354 #define HAL_CLOCK_INITIALIZE( _period_ ) \
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355 { \
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356 volatile cyg_uint16 *timer4_br = (cyg_uint16 *)TIMER4_BR; \
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357 volatile cyg_uint8 *timer4_md = (cyg_uint8 *)TIMER4_MD; \
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358 volatile cyg_uint16 *timer5_br = (cyg_uint16 *)TIMER5_BR; \
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359 volatile cyg_uint8 *timer5_md = (cyg_uint8 *)TIMER5_MD; \
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360 \
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361 /* Set timers 4 and 5 into cascade mode */ \
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362 \
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363 *timer5_br = (_period_)>>16; \
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364 \
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365 *timer5_md = 0x40; \
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366 *timer5_md = 0x83; \
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367 \
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368 *timer4_br = (_period_)&0x0000FFFF; \
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369 \
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370 *timer4_md = 0x40; \
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371 *timer4_md = 0x80; \
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372 }
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373
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374 #define HAL_CLOCK_RESET( _vector_, _period_ )
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375
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376 #define HAL_CLOCK_READ( _pvalue_ ) \
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377 { \
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378 volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR; \
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379 volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR; \
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380 \
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381 cyg_uint16 t5; \
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382 cyg_uint16 t4; \
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383 \
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384 /* Loop reading the two timers until we can read t5 twice */ \
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385 /* with the same value. This avoids getting silly times if */ \
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386 /* the timers carry between reading the two regs. */ \
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387 do { \
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388 t5 = *timer5_cr; \
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389 t4 = *timer4_cr; \
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390 } while( t5 != *timer5_cr ); \
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391 \
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392 *(_pvalue_) = CYGNUM_KERNEL_COUNTERS_RTC_PERIOD - ((t5<<16) + t4); \
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393 }
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394
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395 // FIXME: above line should not use CYGNUM_KERNEL_COUNTERS_RTC_PERIOD since
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396 // this means the HAL gets configured by kernel options even when the
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397 // kernel is disabled!
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398
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399
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400 //--------------------------------------------------------------------------
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401 #endif // ifndef CYGONCE_HAL_VAR_INTR_H
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402 // End of var_intr.h