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annotate packages/hal/powerpc/mpc8xx/current/include/var_cache.h @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children 047f0d36832a
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3 //=============================================================================
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4 //
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5 // var_cache.h
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6 //
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7 // Variant HAL cache control API
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8 //
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9 //=============================================================================
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10 //####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later version.
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18 //
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19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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22 // for more details.
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23 //
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24 // You should have received a copy of the GNU General Public License along
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25 // with eCos; if not, write to the Free Software Foundation, Inc.,
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 //
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28 // As a special exception, if other files instantiate templates or use macros
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29 // or inline functions from this file, or you compile this file and link it
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30 // with other works to produce a work based on this file, this file does not
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31 // by itself cause the resulting work to be covered by the GNU General Public
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32 // License. However the source code for this file must still be made available
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33 // in accordance with section (3) of the GNU General Public License.
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34 //
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35 // This exception does not invalidate any other reasons why a work based on
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36 // this file might be covered by the GNU General Public License.
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37 //
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38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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39 // at http://sources.redhat.com/ecos/ecos-license/
208
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40 // -------------------------------------------
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41 //####ECOSGPLCOPYRIGHTEND####
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42 //=============================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors:nickg, jskov
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47 // Date: 2000-04-02
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48 // Purpose: Variant cache control API
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49 // Description: The macros defined here provide the HAL APIs for handling
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50 // cache control operations on the MPC8xx variant CPUs.
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51 // Usage: Is included via the architecture cache header:
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52 // #include <cyg/hal/hal_cache.h>
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53 // ...
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54 //
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55 //####DESCRIPTIONEND####
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56 //
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57 //=============================================================================
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58
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59 #include <pkgconf/hal.h>
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60 #include <cyg/infra/cyg_type.h>
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61
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62 #include <cyg/hal/ppc_regs.h>
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63
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64 #include <cyg/hal/plf_cache.h>
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65
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66
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67 //-----------------------------------------------------------------------------
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68 // Cache dimensions - these vary between the 8xx sub-models
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69
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70 #if defined(CYGPKG_HAL_POWERPC_MPC860)
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71 // Data cache
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72 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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73 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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74 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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75
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76 // Instruction cache
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77 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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78 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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79 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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80 #endif // defined(CYGPKG_HAL_POWERPC_MPC860)
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81
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82 #if defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
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83 // Data cache
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84 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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85 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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86 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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87
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88 // Instruction cache
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89 #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes
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90 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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91 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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92 #endif // defined(CYGPKG_HAL_POWERPC_MPC823) || defined(CYGPKG_HAL_POWERPC_MPC850)
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93
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94 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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95 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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96
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97 //-----------------------------------------------------------------------------
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98 // Global control of data cache
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99
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100 // Enable the data cache
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101 #define HAL_DCACHE_ENABLE() \
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102 asm volatile ("sync;" \
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103 "mtspr %0, %1;" \
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104 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE))
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105
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106 // Disable the data cache
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107 #define HAL_DCACHE_DISABLE() \
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108 asm volatile ("sync;" \
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109 "mtspr %0, %1;" \
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110 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD))
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111
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112 // Invalidate the entire cache
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113 // Note: Any locked lines will not be invalidated.
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114 #define HAL_DCACHE_INVALIDATE_ALL() \
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115 asm volatile ("sync;" \
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116 "mtspr %0, %1;" \
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117 : : "I" (CYGARC_REG_DC_CST), \
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118 "r" (CYGARC_REG_DC_CMD_IA))
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119
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120 // Synchronize the contents of the cache with memory.
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121 #define HAL_DCACHE_SYNC() \
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122 CYG_MACRO_START \
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123 cyg_int32 i; \
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124 for (i = 0; i < HAL_DCACHE_SETS; i++){ \
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125 asm volatile ("sync;" \
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126 "mtspr %0, %2;" \
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127 "mtspr %1, %4;" \
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128 "mtspr %0, %3;" \
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129 "mtspr %1, %4;" \
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130 : /* no output */ \
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131 : /* %0 */ "I" (CYGARC_REG_DC_ADR), \
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132 /* %1 */ "I" (CYGARC_REG_DC_CST), \
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133 /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
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134 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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135 /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \
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136 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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137 /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \
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138 } \
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139 CYG_MACRO_END
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140
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141 // Query the state of the data cache
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142 #define HAL_DCACHE_IS_ENABLED(_state_) \
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143 asm volatile ("mfspr %0, %1;" \
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144 "rlwinm %0,%0,1,31,31;" \
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145 : "=r" (_state_) : "I" (CYGARC_REG_DC_CST))
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146
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147 // Set the data cache refill burst size
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148 //#define HAL_DCACHE_BURST_SIZE(_size_)
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149
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150 // Set the data cache write mode
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151 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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152
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153 //#define HAL_DCACHE_WRITETHRU_MODE 0
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154 //#define HAL_DCACHE_WRITEBACK_MODE 1
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155
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156
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157 // Load the contents of the given address range into the data cache
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158 // and then lock the cache so that it stays there.
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159
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160 // Restrictions: This implementation only allows a single area to be
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161 // locked at any one time. This area must be 2kB or less in size.
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162
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163 // Implementation: Flush entire cache, then invalidate it. This
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164 // ensures that the fetched data go into way0.
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165
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166 #define HAL_DCACHE_LOCK(_base_, _size_) \
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167 CYG_MACRO_START \
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168 cyg_int32 __scratch; \
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169 cyg_uint32 __base = (cyg_uint32)(_base_); \
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170 cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \
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171 cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \
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172 HAL_DCACHE_DISABLE(); \
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173 HAL_DCACHE_SYNC (); \
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174 HAL_DCACHE_INVALIDATE_ALL (); \
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175 HAL_DCACHE_ENABLE(); \
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176 do { \
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177 asm volatile ("lbz %0,0(%1);" \
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178 "sync;" \
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179 "mtspr %2, %4;" \
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180 "mtspr %3, %5;" \
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181 : /* %0 */ "=&r" (__scratch) \
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182 : /* %1 */ "b" (__base), \
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183 /* %2 */ "I" (CYGARC_REG_DC_ADR), \
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184 /* %3 */ "I" (CYGARC_REG_DC_CST), \
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185 /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
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186 |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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187 /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \
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188 __l++; \
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189 __base += HAL_DCACHE_LINE_SIZE; \
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190 } while (__count--); \
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191 CYG_MACRO_END
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192
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193
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194 // Undo a previous lock operation
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195
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196 // Implementation: Unlocks entire cache.
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197
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198 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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199 HAL_DCACHE_UNLOCK_ALL()
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200
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201
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202 // Unlock entire cache
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203 #define HAL_DCACHE_UNLOCK_ALL() \
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204 CYG_MACRO_START \
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205 asm volatile ("sync;" \
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206 "mtspr %0, %1;" \
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207 : : "I" (CYGARC_REG_DC_CST), \
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208 "r" (CYGARC_REG_DC_CMD_UA)); \
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209 CYG_MACRO_END
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210
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211
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212
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213 //-----------------------------------------------------------------------------
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214 // Data cache line control
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215
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216 // Allocate cache lines for the given address range without reading its
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217 // contents from memory.
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218 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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219
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220 // Write dirty cache lines to memory and invalidate the cache entries
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221 // for the given address range.
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222 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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223 CYG_MACRO_START \
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224 cyg_uint32 __base = (cyg_uint32) (_base_); \
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225 cyg_int32 __size = (cyg_int32) (_size_); \
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226 while (__size > 0) { \
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227 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
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228 __base += HAL_DCACHE_LINE_SIZE; \
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229 __size -= HAL_DCACHE_LINE_SIZE; \
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230 } \
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231 CYG_MACRO_END
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232
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233 // Invalidate cache lines in the given range without writing to memory.
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234 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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235 CYG_MACRO_START \
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236 cyg_uint32 __base = (cyg_uint32) (_base_); \
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237 cyg_int32 __size = (cyg_int32) (_size_); \
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238 while (__size > 0) { \
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239 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \
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240 __base += HAL_DCACHE_LINE_SIZE; \
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241 __size -= HAL_DCACHE_LINE_SIZE; \
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242 } \
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243 CYG_MACRO_END
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244
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245 // Write dirty cache lines to memory for the given address range.
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246 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
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247 CYG_MACRO_START \
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248 cyg_uint32 __base = (cyg_uint32) (_base_); \
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249 cyg_int32 __size = (cyg_int32) (_size_); \
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250 while (__size > 0) { \
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251 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
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252 __base += HAL_DCACHE_LINE_SIZE; \
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253 __size -= HAL_DCACHE_LINE_SIZE; \
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254 } \
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255 CYG_MACRO_END
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256
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257 // Preread the given range into the cache with the intention of reading
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258 // from it later.
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259 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \
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260 CYG_MACRO_START \
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261 cyg_uint32 __base = (cyg_uint32) (_base_); \
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262 cyg_int32 __size = (cyg_int32) (_size_); \
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263 while (__size > 0) { \
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264 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \
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265 __base += HAL_DCACHE_LINE_SIZE; \
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266 __size -= HAL_DCACHE_LINE_SIZE; \
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267 } \
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268 CYG_MACRO_END
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269
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270 // Preread the given range into the cache with the intention of writing
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271 // to it later.
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272 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \
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273 CYG_MACRO_START \
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274 cyg_uint32 __base = (cyg_uint32) (_base_); \
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275 cyg_int32 __size = (cyg_int32) (_size_); \
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276 while (__size > 0) { \
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277 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \
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278 __base += HAL_DCACHE_LINE_SIZE; \
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279 __size -= HAL_DCACHE_LINE_SIZE; \
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280 } \
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281 CYG_MACRO_END
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282
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283 // Allocate and zero the cache lines associated with the given range.
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284 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \
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285 CYG_MACRO_START \
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286 cyg_uint32 __base = (cyg_uint32) (_base_); \
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287 cyg_int32 __size = (cyg_int32) (_size_); \
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288 while (__size > 0) { \
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289 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \
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290 __base += HAL_DCACHE_LINE_SIZE; \
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291 __size -= HAL_DCACHE_LINE_SIZE; \
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292 } \
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293 CYG_MACRO_END
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294
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295 //-----------------------------------------------------------------------------
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296 // Global control of Instruction cache
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297
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298 // Enable the instruction cache
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299 #define HAL_ICACHE_ENABLE() \
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300 asm volatile ("isync;" \
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301 "mtspr %0, %1;" \
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302 "isync" \
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303 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))
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304
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305 // Disable the instruction cache
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306 #define HAL_ICACHE_DISABLE() \
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307 asm volatile ("isync;" \
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308 "mtspr %0, %1;" \
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309 "isync" \
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310 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD))
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311
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312 // Invalidate the entire cache
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313 #define HAL_ICACHE_INVALIDATE_ALL() \
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314 asm volatile ("isync;" \
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315 "mtspr %0, %1;" \
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316 "isync" \
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317 : : "I" (CYGARC_REG_IC_CST), \
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318 "r" (CYGARC_REG_IC_CMD_IA))
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319
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320 // Synchronize the contents of the cache with memory.
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321 #define HAL_ICACHE_SYNC() \
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322 HAL_ICACHE_INVALIDATE_ALL()
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323
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324 // Query the state of the instruction cache
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325 #define HAL_ICACHE_IS_ENABLED(_state_) \
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326 asm volatile ("mfspr %0, %1;" \
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327 "rlwinm %0,%0,1,31,31;" \
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328 : "=r" (_state_) : "I" (CYGARC_REG_IC_CST))
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329
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330 // Set the instruction cache refill burst size
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331 //#define HAL_ICACHE_BURST_SIZE(_size_)
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332
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333
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334 // Load the contents of the given address range into the instruction cache
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335 // and then lock the cache so that it stays there.
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336
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337 // Restrictions: This implementation only allows a single area to be
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338 // locked at any one time. This area must be 2kB or less in size.
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339
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340 // Implementation: Flush entire cache, then invalidate it. This
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341 // ensures that the fetched data go into way0.
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342
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343 #define HAL_ICACHE_LOCK(_base_, _size_) \
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344 CYG_MACRO_START \
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345 unsigned long __base = \
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346 ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \
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347 int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \
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348 do { \
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349 asm volatile ("mtspr %0, %2;" \
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350 "mtspr %1, %3;" \
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351 "isync;" \
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352 : /* no output */ \
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353 : /* %0 */ "I" (CYGARC_REG_IC_ADR), \
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354 /* %1 */ "I" (CYGARC_REG_IC_CST), \
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355 /* %2 */ "r" (__base), \
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356 /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \
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357 __base += HAL_ICACHE_LINE_SIZE; \
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358 } while (__count--); \
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359 CYG_MACRO_END
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360
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361 // Undo a previous lock operation
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362
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363 // Implementation: Unlocks entire cache.
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364 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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365 HAL_ICACHE_UNLOCK_ALL()
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366
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367 // Unlock entire cache
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368 #define HAL_ICACHE_UNLOCK_ALL() \
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369 CYG_MACRO_START \
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370 asm volatile ("sync;" \
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371 "mtspr %0, %1;" \
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372 : : "I" (CYGARC_REG_IC_CST), \
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373 "r" (CYGARC_REG_IC_CMD_UA)); \
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374 CYG_MACRO_END
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375
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376 //-----------------------------------------------------------------------------
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377 // Instruction cache line control
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378
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379 // Invalidate cache lines in the given range without writing to memory.
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380 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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381
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382 //-----------------------------------------------------------------------------
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383 #endif // ifndef CYGONCE_VAR_CACHE_H
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384 // End of var_cache.h