Mercurial > flash_v2
annotate packages/kernel/current/src/intr/intr.cxx @ 10:d3fbcdfa1b2f ecos-sw-1999-05-29
Merge from eCos master repository on 1999-05-29-00:13:11-BST
| author | jlarmour |
|---|---|
| date | Fri, 28 May 1999 16:43:09 +0000 |
| parents | ece80412419a |
| children | 7253dcc42a09 |
| rev | line source |
|---|---|
| 0 | 1 //========================================================================== |
| 2 // | |
| 2 | 3 // intr/intr.cxx |
| 0 | 4 // |
| 2 | 5 // Interrupt class implementations |
| 0 | 6 // |
| 7 //========================================================================== | |
| 8 //####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 26 // ------------------------------------------- |
| 27 // | |
| 28 //####COPYRIGHTEND#### | |
| 29 //========================================================================== | |
| 30 //#####DESCRIPTIONBEGIN#### | |
| 31 // | |
| 2 | 32 // Author(s): nickg |
| 33 // Contributors: nickg | |
| 34 // Date: 1999-02-17 | |
| 35 // Purpose: Interrupt class implementation | |
| 36 // Description: This file contains the definitions of the interrupt | |
| 37 // class. | |
| 0 | 38 // |
| 39 //####DESCRIPTIONEND#### | |
| 40 // | |
| 41 //========================================================================== | |
| 42 | |
| 43 #include <pkgconf/kernel.h> | |
| 44 | |
| 45 #include <cyg/kernel/ktypes.h> // base kernel types | |
| 46 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 47 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 48 #include <cyg/kernel/instrmnt.h> // instrumentation | |
| 49 | |
| 50 #include <cyg/kernel/intr.hxx> // our header | |
| 51 | |
| 52 #include <cyg/kernel/sched.hxx> // scheduler | |
| 53 | |
| 54 #include <cyg/kernel/sched.inl> | |
| 55 | |
| 56 // ------------------------------------------------------------------------- | |
| 2 | 57 // Statics |
| 58 | |
| 59 // Interrupt disable counter. Note that this is initialized to 1 since | |
| 60 // enable_interrupts() is called in Cyg_Scheduler::start(). | |
| 61 | |
| 62 cyg_int32 Cyg_Interrupt::disable_counter = 1; | |
| 63 | |
| 64 // ------------------------------------------------------------------------- | |
| 0 | 65 |
| 66 Cyg_Interrupt::Cyg_Interrupt( | |
| 67 cyg_vector vec, // Vector to attach to | |
| 68 cyg_priority pri, // Queue priority | |
| 69 CYG_ADDRWORD d, // Data pointer | |
| 70 cyg_ISR *ir, // Interrupt Service Routine | |
| 71 cyg_DSR *dr // Deferred Service Routine | |
| 72 ) | |
| 73 { | |
| 2 | 74 CYG_REPORT_FUNCTION(); |
| 75 CYG_REPORT_FUNCARG5("vector=%d, priority=%d, data=%08x, isr=%08x, " | |
| 76 "dsr=%08x", vec, pri, d, ir, dr); | |
| 77 | |
| 0 | 78 vector = vec; |
| 79 priority = pri; | |
| 80 isr = ir; | |
| 81 dsr = dr; | |
| 82 data = d; | |
| 83 | |
| 84 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 85 | |
| 86 dsr_count = 0; | |
| 87 next_dsr = NULL; | |
| 88 | |
| 89 #endif | |
| 90 | |
| 91 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 92 | |
| 93 next = NULL; | |
| 94 | |
| 95 #endif | |
| 2 | 96 |
| 97 CYG_REPORT_RETURN(); | |
| 0 | 98 |
| 99 }; | |
| 100 | |
| 101 // ------------------------------------------------------------------------- | |
| 102 | |
| 103 Cyg_Interrupt::~Cyg_Interrupt() | |
| 104 { | |
| 2 | 105 CYG_REPORT_FUNCTION(); |
| 0 | 106 detach(); |
| 2 | 107 CYG_REPORT_RETURN(); |
| 0 | 108 }; |
| 109 | |
| 110 // ------------------------------------------------------------------------- | |
| 111 // DSR handling statics: | |
| 112 | |
| 113 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 114 | |
| 2 | 115 Cyg_Interrupt * |
| 116 Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; | |
| 0 | 117 |
| 118 cyg_ucount32 Cyg_Interrupt::dsr_table_head = 0; | |
| 119 | |
| 120 cyg_ucount32 Cyg_Interrupt::dsr_table_tail = 0; | |
| 121 | |
| 122 #endif | |
| 123 | |
| 124 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 125 | |
| 126 Cyg_Interrupt *Cyg_Interrupt::dsr_list = NULL; | |
| 127 | |
| 128 #endif | |
| 129 | |
| 130 // ------------------------------------------------------------------------- | |
| 131 // Call any pending DSRs | |
| 132 | |
| 2 | 133 void |
| 134 Cyg_Interrupt::call_pending_DSRs_inner(void) | |
| 0 | 135 { |
| 136 // CYG_REPORT_FUNCTION(); | |
| 137 | |
| 138 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 139 | |
| 140 while( dsr_table_head != dsr_table_tail ) | |
| 141 { | |
| 142 Cyg_Interrupt *intr = dsr_table[dsr_table_head]; | |
| 143 | |
| 144 dsr_table_head++; | |
| 145 if( dsr_table_head >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 146 dsr_table_head = 0; | |
| 147 | |
| 148 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0); | |
| 149 | |
| 150 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data ); | |
| 151 } | |
| 152 | |
| 153 #endif | |
| 154 | |
| 155 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 156 | |
| 157 while( dsr_list != NULL ) | |
| 158 { | |
| 159 Cyg_Interrupt *intr; | |
| 160 cyg_uint32 old_intr; | |
| 161 cyg_count32 count; | |
| 162 | |
| 163 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 164 | |
| 165 intr = dsr_list; | |
| 166 dsr_list = intr->next_dsr; | |
| 167 count = intr->dsr_count; | |
| 168 intr->dsr_count = 0; | |
| 169 | |
| 170 HAL_RESTORE_INTERRUPTS(old_intr); | |
| 171 | |
| 172 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data ); | |
| 173 | |
| 174 } | |
| 175 | |
| 176 #endif | |
| 177 | |
| 178 }; | |
| 179 | |
| 2 | 180 externC void |
| 181 cyg_interrupt_call_pending_DSRs(void) | |
| 182 { | |
| 183 Cyg_Interrupt::call_pending_DSRs_inner(); | |
| 184 } | |
| 185 | |
|
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186 // |
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187 // Use HAL supported function to run through the DSRs, but executing using |
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188 // the separate interrupt stack if available. This function calls back |
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189 // into this module via 'cyg_interrupt_call_pending_DSRs' above, to keep |
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190 // the whole process as general as possible. |
| 2 | 191 |
| 192 void | |
| 193 Cyg_Interrupt::call_pending_DSRs(void) | |
| 194 { | |
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195 HAL_INTERRUPT_STACK_CALL_PENDING_DSRS(); |
| 2 | 196 } |
| 197 | |
| 198 | |
| 0 | 199 // ------------------------------------------------------------------------- |
| 200 | |
| 2 | 201 void |
| 202 Cyg_Interrupt::post_dsr(void) | |
| 0 | 203 { |
| 204 // CYG_REPORT_FUNCTION(); | |
| 205 | |
| 206 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0); | |
| 207 | |
| 208 cyg_uint32 old_intr; | |
| 209 | |
| 210 // We need to disable interrupts during this part to | |
| 211 // guard against nested interrupts. | |
| 212 | |
| 213 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 214 | |
| 215 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 216 | |
| 217 dsr_table[dsr_table_tail++] = this; | |
| 218 if( dsr_table_tail >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 219 dsr_table_tail = 0; | |
| 220 | |
| 221 #endif | |
| 222 | |
| 223 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 224 | |
| 225 // Only add the interrupt to the dsr list if this is | |
| 226 // the first DSR call. | |
| 227 // At present DSRs are pushed onto the list and will be | |
| 228 // called in reverse order. We do not define the order | |
| 229 // in which DSRs are called, so this is acceptable. | |
| 230 | |
| 231 if( dsr_count++ == 0 ) | |
| 232 { | |
| 233 next_dsr = dsr_list; | |
| 234 dsr_list = this; | |
| 235 } | |
| 236 | |
| 237 #endif | |
| 238 | |
| 239 HAL_RESTORE_INTERRUPTS(old_intr); | |
| 240 }; | |
| 241 | |
| 242 // ------------------------------------------------------------------------- | |
| 2 | 243 // A C callable interface to Cyg_Interrupt::post_dsr() that can be used from |
| 244 // the HAL. | |
| 0 | 245 |
| 2 | 246 externC void |
| 247 cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ) | |
| 248 { | |
| 249 Cyg_Interrupt* intr = (Cyg_Interrupt*) intr_obj; | |
| 250 intr->post_dsr (); | |
| 251 } | |
| 252 | |
| 253 // ------------------------------------------------------------------------- | |
| 254 | |
| 255 // FIXME: should have better name - Jifl | |
| 256 externC void | |
| 257 interrupt_end( | |
| 0 | 258 cyg_uint32 isr_ret, |
| 259 Cyg_Interrupt *intr, | |
| 260 HAL_SavedRegisters *regs | |
| 261 ) | |
| 262 { | |
| 263 // CYG_REPORT_FUNCTION(); | |
| 264 | |
| 2 | 265 // Sometimes we have a NULL intr object pointer. |
| 266 cyg_vector vector = (intr!=NULL)?intr->vector:0; | |
| 267 | |
| 268 CYG_INSTRUMENT_INTR(END, vector, isr_ret); | |
| 269 | |
| 270 | |
| 0 | 271 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
| 272 | |
| 273 // Only do this if we are in a non-chained configuration. | |
| 274 // If we are chained, then chain_isr below will do the DSR | |
| 275 // posting. | |
| 276 | |
| 2 | 277 if( isr_ret & Cyg_Interrupt::CALL_DSR && intr != NULL ) intr->post_dsr(); |
| 0 | 278 |
| 279 #endif | |
| 280 | |
| 281 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 282 | |
| 283 // If we have GDB support enabled, and there is the possibility | |
| 284 // that this thread will be context switched as a result of this | |
| 285 // interrupt, then save the pointer to the saved thread context in | |
| 286 // the thread object so that GDB can get a meaningful context to | |
| 287 // look at. | |
| 288 | |
| 289 Cyg_Scheduler::get_current_thread()->set_saved_context(regs); | |
| 290 | |
| 291 #endif | |
| 292 | |
| 293 // Now unlock the scheduler, which may also call DSRs | |
| 294 // and cause a thread switch to happen. | |
| 295 | |
| 296 Cyg_Scheduler::unlock(); | |
| 297 | |
| 298 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 299 | |
| 300 Cyg_Scheduler::get_current_thread()->set_saved_context(0); | |
| 301 | |
| 302 #endif | |
| 303 | |
| 2 | 304 CYG_INSTRUMENT_INTR(RESTORE, vector, 0); |
| 0 | 305 } |
| 306 | |
| 307 // ------------------------------------------------------------------------- | |
| 308 // Interrupt chaining statics. | |
| 309 | |
| 310 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 311 | |
| 2 | 312 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYGNUM_HAL_ISR_COUNT]; |
| 0 | 313 |
| 314 #endif | |
| 315 | |
| 316 // ------------------------------------------------------------------------- | |
| 317 // Chaining ISR inserted in HAL vector | |
| 318 | |
| 319 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 320 | |
| 2 | 321 cyg_uint32 |
| 322 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data) | |
| 0 | 323 { |
| 324 Cyg_Interrupt *p = *(Cyg_Interrupt **)data; | |
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325 register cyg_uint32 isr_ret = 0; |
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326 |
| 0 | 327 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0); |
| 328 | |
| 329 while( p != NULL ) | |
| 330 { | |
| 331 if( p->vector == vector ) | |
| 332 { | |
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333 isr_ret = p->isr(vector, p->data); |
| 0 | 334 |
| 2 | 335 if( isr_ret & Cyg_Interrupt::CALL_DSR ) p->post_dsr(); |
| 0 | 336 |
| 2 | 337 if( isr_ret & Cyg_Interrupt::HANDLED ) break; |
| 0 | 338 } |
| 339 | |
| 340 p = p->next; | |
| 341 } | |
| 342 | |
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343 #ifdef CYG_HAL_DEFAULT_ISR |
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344 if( (isr_ret & Cyg_Interrupt::HANDLED) == 0 ) |
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345 { |
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346 // If we finished the loop for some reason other than that an |
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347 // ISR has handled the interrupt, call any default ISR to either |
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348 // report the spurious interrupt, or do some other HAL level processing |
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349 // such as GDB interrupt detection etc. |
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350 |
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351 CYG_HAL_DEFAULT_ISR( vector, NULL ); |
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352 } |
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353 #endif |
| 0 | 354 return 0; |
| 355 } | |
| 356 | |
| 357 #endif | |
| 358 | |
| 359 // ------------------------------------------------------------------------- | |
| 360 // Attach an ISR to an interrupt vector. | |
| 361 | |
| 2 | 362 void |
| 363 Cyg_Interrupt::attach(void) | |
| 0 | 364 { |
| 365 CYG_REPORT_FUNCTION(); | |
| 366 | |
| 2 | 367 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 368 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 369 |
| 370 CYG_INSTRUMENT_INTR(ATTACH, vector, 0); | |
| 371 | |
| 372 HAL_INTERRUPT_SET_LEVEL( vector, priority ); | |
| 373 | |
| 374 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 375 | |
| 376 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list"); | |
| 377 | |
| 378 cyg_uint32 index; | |
| 379 | |
| 380 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 381 | |
| 382 if( chain_list[index] == NULL ) | |
| 383 { | |
| 2 | 384 int in_use; |
| 0 | 385 // First Interrupt on this chain, just assign it and register |
| 386 // the chain_isr with the HAL. | |
| 387 | |
| 388 chain_list[index] = this; | |
| 389 | |
| 2 | 390 HAL_INTERRUPT_IN_USE( vector, in_use ); |
| 391 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 0 | 392 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL ); |
| 393 } | |
| 394 else | |
| 395 { | |
| 396 // There are already interrupts chained, add this one into the | |
| 397 // chain in priority order. | |
| 398 | |
| 399 Cyg_Interrupt **p = &chain_list[index]; | |
| 400 | |
| 401 while( *p != NULL ) | |
| 402 { | |
| 403 Cyg_Interrupt *n = *p; | |
| 404 | |
| 405 if( n->priority < priority ) break; | |
| 406 | |
| 407 p = &n->next; | |
| 408 } | |
| 409 next = *p; | |
| 410 *p = this; | |
| 411 } | |
| 412 | |
| 413 #else | |
| 414 | |
| 2 | 415 { |
| 416 int in_use; | |
| 417 | |
| 418 | |
| 419 HAL_INTERRUPT_IN_USE( vector, in_use ); | |
| 420 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 421 | |
| 422 HAL_INTERRUPT_ATTACH( vector, isr, data, this ); | |
| 423 } | |
| 0 | 424 |
| 425 #endif | |
| 2 | 426 CYG_REPORT_RETURN(); |
| 0 | 427 } |
| 428 | |
| 429 // ------------------------------------------------------------------------- | |
| 430 // Detach the ISR from the vector | |
| 431 | |
| 2 | 432 void |
| 433 Cyg_Interrupt::detach(void) | |
| 0 | 434 { |
| 435 CYG_REPORT_FUNCTION(); | |
| 436 | |
| 2 | 437 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 438 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 439 |
| 440 CYG_INSTRUMENT_INTR(DETACH, vector, 0); | |
| 441 | |
| 442 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 443 | |
| 444 // Remove the interrupt object from the vector chain. | |
| 445 | |
| 2 | 446 cyg_uint32 index; |
| 447 | |
| 448 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 449 | |
| 450 Cyg_Interrupt **p = &chain_list[index]; | |
| 0 | 451 |
| 452 while( *p != NULL ) | |
| 453 { | |
| 454 Cyg_Interrupt *n = *p; | |
| 455 | |
| 456 if( n == this ) | |
| 457 { | |
| 458 *p = next; | |
| 459 break; | |
| 460 } | |
| 461 | |
| 462 p = &n->next; | |
| 463 } | |
| 464 | |
| 465 // If this was the last one, detach the vector. | |
| 466 | |
| 2 | 467 if( chain_list[index] == NULL ) |
| 0 | 468 HAL_INTERRUPT_DETACH( vector, chain_isr ); |
| 469 | |
| 470 #else | |
| 471 | |
| 472 HAL_INTERRUPT_DETACH( vector, isr ); | |
| 473 | |
| 474 #endif | |
| 2 | 475 |
| 476 CYG_REPORT_RETURN(); | |
| 0 | 477 |
| 478 } | |
| 479 | |
| 480 // ------------------------------------------------------------------------- | |
| 481 // Get the current service routine | |
| 482 | |
| 2 | 483 void |
| 484 Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr) | |
| 0 | 485 { |
| 486 CYG_REPORT_FUNCTION(); | |
| 2 | 487 CYG_REPORT_FUNCARG2("vector = %d, mem to put VSR in is at %08x", vector, |
| 488 vsr); | |
| 0 | 489 |
| 2 | 490 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 491 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 492 |
| 493 HAL_VSR_GET( vector, vsr ); | |
| 2 | 494 |
| 495 CYG_REPORT_RETURN(); | |
| 0 | 496 } |
| 497 | |
| 498 // ------------------------------------------------------------------------- | |
| 499 // Install a vector service routine | |
| 500 | |
| 2 | 501 void |
| 502 Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old) | |
| 0 | 503 { |
| 504 CYG_REPORT_FUNCTION(); | |
| 505 | |
| 2 | 506 CYG_REPORT_FUNCARG3( "vector = %d, new vsr is at %08x, mem to put " |
| 507 "old VSR in is at %08x", vector, vsr, old); | |
| 508 | |
| 0 | 509 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr); |
| 510 | |
| 2 | 511 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 512 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 513 |
| 514 CYG_INTERRUPT_STATE old_ints; | |
| 515 | |
| 516 HAL_DISABLE_INTERRUPTS(old_ints); | |
| 517 | |
| 518 HAL_VSR_SET( vector, vsr, old ); | |
| 519 | |
| 520 HAL_RESTORE_INTERRUPTS(old_ints); | |
| 2 | 521 |
| 522 CYG_REPORT_RETURN(); | |
| 0 | 523 } |
| 524 | |
| 525 // ------------------------------------------------------------------------- | |
| 526 // Disable interrupts at the CPU | |
| 527 | |
| 528 | |
| 2 | 529 void |
| 530 Cyg_Interrupt::disable_interrupts(void) | |
| 0 | 531 { |
| 532 CYG_REPORT_FUNCTION(); | |
| 533 | |
| 2 | 534 CYG_INSTRUMENT_INTR(DISABLE, disable_counter+1, 0); |
| 0 | 535 |
| 536 CYG_INTERRUPT_STATE dummy; | |
| 537 | |
| 538 HAL_DISABLE_INTERRUPTS(dummy); | |
| 539 | |
| 2 | 540 CYG_ASSERT( disable_counter >= 0 , "Disable counter negative"); |
| 541 | |
| 542 disable_counter++; | |
| 543 | |
| 544 CYG_REPORT_RETURN(); | |
| 0 | 545 } |
| 546 | |
| 547 | |
| 548 // ------------------------------------------------------------------------- | |
| 549 // Re-enable CPU interrupts | |
| 550 | |
| 2 | 551 void |
| 552 Cyg_Interrupt::enable_interrupts(void) | |
| 0 | 553 { |
| 554 CYG_REPORT_FUNCTION(); | |
| 555 | |
| 2 | 556 CYG_INSTRUMENT_INTR(ENABLE, disable_counter, 0); |
| 557 | |
| 558 CYG_ASSERT( disable_counter > 0 , "Disable counter not greater than zero"); | |
| 559 | |
| 560 disable_counter--; | |
| 0 | 561 |
| 2 | 562 if ( disable_counter == 0 ) |
| 563 { | |
| 564 HAL_ENABLE_INTERRUPTS(); | |
| 565 } | |
| 566 | |
| 567 CYG_REPORT_RETURN(); | |
| 0 | 568 } |
| 569 | |
| 570 // ------------------------------------------------------------------------- | |
| 571 // Mask a specific interrupt in a PIC | |
| 572 | |
| 2 | 573 void |
| 574 Cyg_Interrupt::mask_interrupt(cyg_vector vector) | |
| 0 | 575 { |
| 576 CYG_REPORT_FUNCTION(); | |
| 2 | 577 CYG_REPORT_FUNCARG1("vector=%d", vector); |
| 0 | 578 |
| 2 | 579 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 580 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 581 |
| 582 CYG_INSTRUMENT_INTR(MASK, vector, 0); | |
| 583 | |
| 2 | 584 HAL_INTERRUPT_MASK( vector ); |
| 585 | |
| 586 CYG_REPORT_RETURN(); | |
| 0 | 587 } |
| 588 | |
| 589 // ------------------------------------------------------------------------- | |
| 590 // Clear PIC mask | |
| 591 | |
| 2 | 592 void |
| 593 Cyg_Interrupt::unmask_interrupt(cyg_vector vector) | |
| 0 | 594 { |
| 595 CYG_REPORT_FUNCTION(); | |
| 596 | |
| 2 | 597 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 598 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 599 |
| 600 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); | |
| 601 | |
| 602 HAL_INTERRUPT_UNMASK( vector ); | |
| 2 | 603 |
| 604 CYG_REPORT_RETURN(); | |
| 0 | 605 } |
| 606 | |
| 607 | |
| 608 // ------------------------------------------------------------------------- | |
| 609 // Acknowledge interrupt at PIC | |
| 610 | |
| 2 | 611 void |
| 612 Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector) | |
| 0 | 613 { |
| 614 // CYG_REPORT_FUNCTION(); | |
| 615 | |
| 2 | 616 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 617 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 618 |
| 619 CYG_INSTRUMENT_INTR(ACK, vector, 0); | |
| 620 | |
| 621 HAL_INTERRUPT_ACKNOWLEDGE( vector ); | |
| 622 } | |
| 623 | |
| 624 // ------------------------------------------------------------------------- | |
| 625 // Change interrupt detection at PIC | |
| 626 | |
| 2 | 627 void |
| 628 Cyg_Interrupt::configure_interrupt( | |
| 0 | 629 cyg_vector vector, // vector to control |
| 630 cyg_bool level, // level or edge triggered | |
| 631 cyg_bool up // hi/lo level, rising/falling edge | |
| 632 ) | |
| 633 { | |
| 634 CYG_REPORT_FUNCTION(); | |
| 2 | 635 CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level, |
| 636 up); | |
| 0 | 637 |
| 2 | 638 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 639 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 640 |
| 641 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up); | |
| 642 | |
| 643 HAL_INTERRUPT_CONFIGURE( vector, level, up ); | |
| 2 | 644 |
| 645 CYG_REPORT_RETURN(); | |
| 0 | 646 } |
| 647 | |
| 648 // ------------------------------------------------------------------------- | |
| 649 // EOF intr/intr.cxx |