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* Added execute permissions to files missed in conversion from CVS
author alexs
date Mon, 12 Oct 2009 02:26:09 +0100
parents fb71b8d20fd9
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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76
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1 //==========================================================================
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2 //
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3 // ebsa285_misc.c
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4 //
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5 // HAL misc board support code for StrongARM EBSA285-1
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license/
208
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): gthomas
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44 // Contributors: gthomas
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45 // Date: 1999-02-20
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46 // Purpose: HAL board support
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47 // Description: Implementations of HAL board interfaces
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //========================================================================*/
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52
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53 #include <pkgconf/hal.h>
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54 #include <pkgconf/system.h>
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55 #include CYGBLD_HAL_PLATFORM_H
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56 #include CYGHWR_MEMORY_LAYOUT_H
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57
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58 #include <cyg/infra/cyg_type.h> // base types
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59 #include <cyg/infra/cyg_trac.h> // tracing macros
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60 #include <cyg/infra/cyg_ass.h> // assertion macros
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61
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62 #include <cyg/hal/hal_io.h> // IO macros
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63 #include <cyg/hal/hal_if.h> // calling interface API
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64 #include <cyg/hal/hal_arch.h> // Register state info
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65 #include <cyg/hal/hal_diag.h>
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66 #include <cyg/hal/hal_intr.h> // Interrupt names
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67 #include <cyg/hal/hal_cache.h>
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68 #include <cyg/hal/hal_ebsa285.h> // Hardware definitions
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69
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70 #include <cyg/infra/diag.h> // diag_printf
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71
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72 #include <string.h> // memset
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73
76
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74 /*
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75 * Toggle LED for debugging purposes.
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76 */
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77 /*
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78 * EBSA-285 Soft I/O Register
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79 */
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80 #define EBSA_285_SOFT_IO_REGISTER ((cyg_uint32 *)0x40012000)
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81
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82 /*
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83 * EBSA-285 Soft I/O Register Bit Field definitions
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84 */
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85 #define EBSA_285_SOFT_IO_TOGGLE 0x80
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86 #define EBSA_285_SOFT_IO_RED_LED 0x04
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87 #define EBSA_285_SOFT_IO_GREEN_LED 0x02
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88 #define EBSA_285_SOFT_IO_AMBER_LED 0x01
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89 #define EBSA_285_SOFT_IO_J9_9_10_MASK 0x40
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90 #define EBSA_285_SOFT_IO_J9_11_12_MASK 0x20
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91 #define EBSA_285_SOFT_IO_J9_13_14_MASK 0x10
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92 #define EBSA_285_SOFT_IO_SWITCH_L_MASK 0x0F
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93
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94 static void
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95 hal_bsp_mmu_init(int sdram_size);
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96
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97 // Some initialization has already been done before we get here.
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98 //
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99 // Set up the interrupt environment.
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100 // Set up the MMU so that we can use caches.
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101 // Enable caches.
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102 // - All done!
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103
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104
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105 void hal_hardware_init(void)
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106 {
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107 // Disable all interrupt sources:
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108 *SA110_IRQCONT_IRQENABLECLEAR = 0xffffffff;
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109 *SA110_IRQCONT_FIQENABLECLEAR = 0xffffffff; // including FIQ
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110 // Disable the timers
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111 *SA110_TIMER1_CONTROL = 0;
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112 *SA110_TIMER2_CONTROL = 0;
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113 *SA110_TIMER3_CONTROL = 0;
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114 *SA110_TIMER4_CONTROL = 0;
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115
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116 *SA110_TIMER1_CLEAR = 0; // Clear any pending interrupt
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117 *SA110_TIMER2_CLEAR = 0; // (Data: don't care)
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118 *SA110_TIMER3_CLEAR = 0;
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119 *SA110_TIMER4_CLEAR = 0;
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120
115
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121 // Let the timer run at a default rate (for delays)
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122 hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
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123
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124 // Set up MMU so that we can use caches
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125 hal_bsp_mmu_init( hal_dram_size );
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126
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127 // Enable caches
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128 HAL_DCACHE_ENABLE();
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129 HAL_ICACHE_ENABLE();
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130
110
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131 // Set up eCos/ROM interfaces
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132 hal_if_init();
76
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133 }
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134
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135 // -------------------------------------------------------------------------
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136 // MMU initialization:
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137
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138 static void
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139 hal_bsp_mmu_init(int sdram_size)
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140 {
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141 unsigned long ttb_base = ((unsigned long)0x4000); // could be external
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142 unsigned long i;
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143
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144 *EBSA_285_SOFT_IO_REGISTER = ~EBSA_285_SOFT_IO_RED_LED; // Red LED on
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145
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146
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147 // For if we assign the ttb base dynamically:
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148 // if ((ttb_base & ARM_TRANSLATION_TABLE_MASK) != ttb_base) {
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149 // // we cannot do this:
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150 // while ( 1 ) {
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151 // *EBSA_285_SOFT_IO_REGISTER = 0; // All LEDs on
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152 // for ( i = 100000; i > 0 ; i++ ) ;
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153 // *EBSA_285_SOFT_IO_REGISTER = 7; // All LEDs off
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154 // for ( i = 100000; i > 0 ; i++ ) ;
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155 //#ifdef CYG_HAL_STARTUP_RAM
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156 // return; // Do not bother looping forever...
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157 //#endif
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158 // }
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159 // }
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160
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161 /*
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162 * Set the TTB register
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163 */
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164 asm volatile ("mcr p15,0,%0,c2,c0,0"
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165 :
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166 : "r"(ttb_base)
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167 /*:*/
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168 );
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169 /*
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170 * Set the Domain Access Control Register
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171 */
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172 i = ARM_ACCESS_TYPE_MANAGER(0) |
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173 ARM_ACCESS_TYPE_NO_ACCESS(1) |
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174 ARM_ACCESS_TYPE_NO_ACCESS(2) |
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175 ARM_ACCESS_TYPE_NO_ACCESS(3) |
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176 ARM_ACCESS_TYPE_NO_ACCESS(4) |
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177 ARM_ACCESS_TYPE_NO_ACCESS(5) |
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178 ARM_ACCESS_TYPE_NO_ACCESS(6) |
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179 ARM_ACCESS_TYPE_NO_ACCESS(7) |
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180 ARM_ACCESS_TYPE_NO_ACCESS(8) |
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181 ARM_ACCESS_TYPE_NO_ACCESS(9) |
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182 ARM_ACCESS_TYPE_NO_ACCESS(10) |
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183 ARM_ACCESS_TYPE_NO_ACCESS(11) |
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184 ARM_ACCESS_TYPE_NO_ACCESS(12) |
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185 ARM_ACCESS_TYPE_NO_ACCESS(13) |
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186 ARM_ACCESS_TYPE_NO_ACCESS(14) |
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187 ARM_ACCESS_TYPE_NO_ACCESS(15);
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188
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189 asm volatile ("mcr p15,0,%0,c3,c0,0"
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190 :
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191 : "r"(i)
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192 /*:*/
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193 );
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194
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195 /*
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196 * First clear all TT entries - ie Set them to Faulting
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197 */
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198 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
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199
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200 /*
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201 * We only do direct mapping for the EBSA board. That is, all
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202 * virt_addr == phys_addr.
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203 */
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204
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205 /*
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206 * Actual Base = 0x000(00000)
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207 * Virtual Base = 0x000(00000)
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208 * Size = Max SDRAM
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209 * SDRAM
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210 */
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211 for (i = 0x000; i < (sdram_size >> 20); i++) {
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212 ARM_MMU_SECTION(ttb_base, i, i,
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213 ARM_CACHEABLE, ARM_BUFFERABLE,
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214 ARM_ACCESS_PERM_RW_RW);
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215 }
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216
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217 #ifdef CYGPKG_IO_PCI
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218 /*
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219 * Actual Base = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE
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220 * Virtual Base = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE
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221 * Size = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE
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222 * Memory accessible from PCI space. Overrides part of the above mapping.
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223 */
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224 for (i = CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE >> 20;
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225 i < ((CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE+CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE) >> 20);
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226 i++) {
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227 ARM_MMU_SECTION(ttb_base, i, i,
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228 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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229 ARM_ACCESS_PERM_RW_RW);
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230 }
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231 #endif
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232
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233 /*
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234 * Actual Base = 0x400(00000)
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235 * Virtual Base = 0x400(00000)
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236 * Size = 1M
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237 * 21285 Registers
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238 *
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239 * Actual Base = 0x400(10000)
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240 * Virtual Base = 0x400(10000)
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241 * Size = 1M
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242 * Soft I/O port and XBus IO
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243 */
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244 ARM_MMU_SECTION(ttb_base, 0x400, 0x400,
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245 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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246 ARM_ACCESS_PERM_RW_RW);
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247
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248 /*
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249 * Actual Base = 0x410(00000) - 0x413(FFFFF)
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250 * Virtual Base = 0x410(00000) - 0x413(FFFFF)
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251 * Size = 4M
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252 * FLASH ROM
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253 */
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254 for (i = 0x410; i <= 0x413; i++) {
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255 ARM_MMU_SECTION(ttb_base, i, i,
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256 ARM_CACHEABLE, ARM_UNBUFFERABLE,
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257 ARM_ACCESS_PERM_RW_RW);
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258 }
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259
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260 /*
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261 * Actual Base = 0x420(00000)
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262 * Virtual Base = 0x420(00000)
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263 * Size = 1M
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264 * 21285 CSR Space
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265 */
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266 ARM_MMU_SECTION(ttb_base, 0x420, 0x420,
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267 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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268 ARM_ACCESS_PERM_RW_RW);
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269
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270 /*
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271 * Actual Base = 0x500(00000)-0x50F(FFFFF)
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272 * Virtual Base = 0x500(00000)-0x50F(FFFFF)
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273 * Size = 16M
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274 * Zeros (Cache Clean) Bank
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275 */
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276 for (i = 0x500; i <= 0x50F; i++) {
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277 ARM_MMU_SECTION(ttb_base, i, i,
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278 ARM_CACHEABLE, ARM_BUFFERABLE,
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279 ARM_ACCESS_PERM_RW_RW);
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280 }
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281
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282 /*
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283 * Actual Base = 0x780(00000)-0x78F(FFFFF)
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284 * Virtual Base = 0x780(00000)-0x78F(FFFFF)
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285 * Size = 16M
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286 * Outbound Write Flush
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287 */
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288 for (i = 0x780; i <= 0x78F; i++) {
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289 ARM_MMU_SECTION(ttb_base, i, i,
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290 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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291 ARM_ACCESS_PERM_RW_RW);
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292 }
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293
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294 /*
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295 * Actual Base = 0x790(00000)-0x7C0(FFFFF)
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296 * Virtual Base = 0x790(00000)-0x7C0(FFFFF)
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297 * Size = 65M
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298 * PCI IACK/Config/IO Space
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299 */
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300 for (i = 0x790; i <= 0x7C0; i++) {
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301 ARM_MMU_SECTION(ttb_base, i, i,
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302 ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
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303 ARM_ACCESS_PERM_RW_RW);
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304 }
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305
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306 /*
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307 * Actual Base = 0x800(00000) - 0xFFF(FFFFF)
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308 * Virtual Base = 0x800(00000) - 0xFFF(FFFFF)
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309 * Size = 2G
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310 * PCI Memory Space
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311 */
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312 for (i = 0x800; i <= 0xFFF; i++) {
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313 ARM_MMU_SECTION(ttb_base, i, i,
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314 ARM_UNCACHEABLE, ARM_BUFFERABLE,
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315 ARM_ACCESS_PERM_RW_RW);
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316 }
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317
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318 *EBSA_285_SOFT_IO_REGISTER = ~EBSA_285_SOFT_IO_AMBER_LED; // AmberLED on
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319
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320 }
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321
115
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322 /*------------------------------------------------------------------------*/
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323
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324 //
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325 // Memory layout
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326 //
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327
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328 externC cyg_uint8 *
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329 hal_arm_mem_real_region_top( cyg_uint8 *regionend )
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330 {
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331 CYG_ASSERT( hal_dram_size > 0, "Didn't detect DRAM size!" );
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332 CYG_ASSERT( hal_dram_size <= 256<<20,
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333 "More than 256MB reported - that can't be right" );
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334
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335 // is it the "normal" end of the DRAM region? If so, it should be
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336 // replaced by the real size
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337 if ( regionend ==
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338 ((cyg_uint8 *)CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE) ) {
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339 regionend = (cyg_uint8 *)CYGMEM_REGION_ram + hal_dram_size;
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340 }
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341 return regionend;
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342 } // hal_arm_mem_real_region_top()
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343
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344
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345
76
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346 // -------------------------------------------------------------------------
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347 static cyg_uint32 _period;
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348
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349 void hal_clock_initialize(cyg_uint32 period)
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350 {
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351 _period = period;
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352
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353 *SA110_TIMER3_CONTROL = 0; // Disable while we are setting up
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354
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355 *SA110_TIMER3_LOAD = period; // Reload value
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356
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357 *SA110_TIMER3_CLEAR = 0; // Clear any pending interrupt
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358 // (Data: don't care)
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359
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360 *SA110_TIMER3_CONTROL = 0x000000cc; // Enable, Periodic (auto-reload),
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361 // External clock (3.68MHz on irq_in_l[2] for Timer 3)
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362
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363 *SA110_TIMER3_CLEAR = 0; // Clear any pending interrupt again
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364
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365 // That's all.
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366 }
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367
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368 // This routine is called during a clock interrupt.
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369
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370 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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371 {
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372 *SA110_TIMER3_CLEAR = period; // Clear any pending interrupt (Data: don't care)
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373 }
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374
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375 // Read the current value of the clock, returning the number of hardware
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376 // "ticks" that have occurred (i.e. how far away the current value is from
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377 // the start)
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378
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379 void hal_clock_read(cyg_uint32 *pvalue)
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380 {
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381 *pvalue = (cyg_uint32)(_period) - *SA110_TIMER3_VALUE;
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382 }
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383
115
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384 //
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385 // Delay for some number of micro-seconds
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386 //
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387 void hal_delay_us(cyg_int32 usecs)
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388 {
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389 int diff, diff2;
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390 cyg_uint32 val1, val2;
147
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391
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392 while (usecs-- > 0) {
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393 diff = 0;
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394 val1 = *SA110_TIMER3_VALUE;
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395 while (diff < 3) {
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396 while ((val2 = *SA110_TIMER3_VALUE) == val1) ;
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397 if (*SA110_TIMER3_LOAD) {
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398 // A kernel is running, the counter may get reset as we watch
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399 diff2 = val2 - val1;
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400 if (diff2 < 0) diff2 += *SA110_TIMER3_LOAD;
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401 diff += diff2;
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402 } else {
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403 diff += val2 - val1;
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404 }
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405 }
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406 }
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407 }
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408
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409 // -------------------------------------------------------------------------
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410
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411 // This routine is called to respond to a hardware interrupt (IRQ). It
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412 // should interrogate the hardware and return the IRQ vector number.
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413 int hal_IRQ_handler(void)
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414 {
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415 int sources;
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416 int index;
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417
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418 #if 0 // test FIQ and print alert if active - really for debugging
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419 sources = *SA110_IRQCONT_FIQSTATUS;
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420 if ( 0 != sources )
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421 diag_printf( "FIQ source active!!! - fiqstatus %08x irqstatus %08x\n",
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422 sources, *SA110_IRQCONT_IRQSTATUS );
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423 else
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424 #endif // Scan FIQ sources also
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425
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426 sources = *SA110_IRQCONT_IRQSTATUS;
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427
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428 // if we come to support FIQ properly...
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429 // if ( 0 == sources )
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430 // sources = *SA110_IRQCONT_FIQSTATUS;
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431
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432 // Nothing wrong with scanning them in the order provided...
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433 // and it'll make the serial device steal fewer cycles.
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434 // So, knowing this is an ARM:
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435 if ( sources & 0xff )
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436 index = 0;
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437 else if ( sources & 0xff00 )
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438 index = 8;
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439 else if ( sources & 0xff0000 )
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440 index = 16;
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441 else // if ( sources & 0xff000000 )
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442 index = 24;
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443
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444 do {
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445 if ( (1 << index) & sources )
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446 return index;
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447 index++;
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448 } while ( index & 7 );
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449
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450 return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
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451 }
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452
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453 //
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454 // Interrupt control
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455 //
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456
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457 void hal_interrupt_mask(int vector)
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458 {
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459 *SA110_IRQCONT_IRQENABLECLEAR = 1 << vector;
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460 }
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461
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462 void hal_interrupt_unmask(int vector)
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463 {
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464 *SA110_IRQCONT_IRQENABLESET = 1 << vector;
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465 }
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466
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467 void hal_interrupt_acknowledge(int vector)
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468 {
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469 // Nothing to do here.
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470 }
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471
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472 void hal_interrupt_configure(int vector, int level, int up)
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473 {
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474 // No interrupts are configurable on this hardware
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475 }
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476
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477 void hal_interrupt_set_level(int vector, int level)
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478 {
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479 // No interrupts are configurable on this hardware
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480 }
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481
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482 #include CYGHWR_MEMORY_LAYOUT_H
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483 typedef void code_fun(void);
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484 void ebsa285_program_new_stack(void *func)
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485 {
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486 register CYG_ADDRESS stack_ptr asm("sp");
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487 register CYG_ADDRESS old_stack asm("r4");
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488 register code_fun *new_func asm("r0");
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489 old_stack = stack_ptr;
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490 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
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491 new_func = (code_fun*)func;
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492 new_func();
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493 stack_ptr = old_stack;
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494 return;
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495 }
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496
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497 /*------------------------------------------------------------------------*/
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498 // EOF ebsa285_misc.c