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comparison packages/hal/arm/cma230/current/src/hal_diag.c @ 110:84e4bde58b26 ecos-sw-2000-07-14

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Merge from eCos master repository on 2000-07-14-22:00:02-BST
author jlarmour
date Mon, 17 Jul 2000 14:42:27 +0000
parents bf00f99aec69
children 25e238959bae
comparison
equal deleted inserted replaced
109:5720c4b6e1d2 110:84e4bde58b26
51 #include <cyg/hal/hal_arch.h> // basic machine info 51 #include <cyg/hal/hal_arch.h> // basic machine info
52 #include <cyg/hal/hal_intr.h> // interrupt macros 52 #include <cyg/hal/hal_intr.h> // interrupt macros
53 #include <cyg/hal/hal_io.h> // IO macros 53 #include <cyg/hal/hal_io.h> // IO macros
54 #include <cyg/hal/hal_diag.h> 54 #include <cyg/hal/hal_diag.h>
55 #include <cyg/hal/hal_cma230.h> // Hardware definitions 55 #include <cyg/hal/hal_cma230.h> // Hardware definitions
56 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS 56 #include <cyg/hal/hal_if.h> // Calling-if API
57 #include <cyg/hal/drv_api.h> 57 #include <cyg/hal/drv_api.h> // driver API
58 #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt 58 #include <cyg/hal/hal_misc.h> // Helper functions
59 #endif 59
60 60 #if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
61 // Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e. 61 || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)
62 // totally stand-alone) system. 62
63 63 static void cyg_hal_plf_serial_init(void);
64 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL) 64
65 #define HAL_DIAG_USES_HARDWARE 65 // FIXME: Copy LCD driver from powerpc/cogent
66 #endif 66 //static void cyg_hal_plf_lcd_init(void);
67 67
68 /*---------------------------------------------------------------------------*/ 68 void
69 #if CYGHWR_HAL_ARM_CMA230_DIAG_PORT==0 69 cyg_hal_plf_comms_init(void)
70 // This is the base address of the A-channel 70 {
71 #define CYG_DEVICE_SERIAL_RS232_16550_BASE CMA101_DUARTA 71 static int initialized = 0;
72 #define CYG_DEVICE_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIAL_A 72
73 #else 73 if (initialized)
74 // This is the base address of the B-channel 74 return;
75 #define CYG_DEVICE_SERIAL_RS232_16550_BASE CMA101_DUARTB 75
76 #define CYG_DEVICE_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIAL_B 76 initialized = 1;
77 #endif 77
78 78 cyg_hal_plf_serial_init();
79 // cyg_hal_plf_lcd_init();
80 }
81 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES
82
83 //=============================================================================
84 // Serial driver
85 //=============================================================================
86
87 //-----------------------------------------------------------------------------
88 // There are two serial ports.
89 #define CYG_DEV_SERIAL_BASE_A 0xe900047 // port A
90 #define CYG_DEV_SERIAL_BASE_B 0xe900007 // port B
91
92 //-----------------------------------------------------------------------------
93 // Default baud rate is 38400
79 // Based on 3.6864 MHz xtal 94 // Based on 3.6864 MHz xtal
80 #if CYGHWR_HAL_ARM_CMA230_DIAG_BAUD==9600 95 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
81 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0x00 96 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
82 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB 0x18 97 #define CYG_DEV_SERIAL_BAUD_LSB 0x18
83 #endif 98 #endif
84 #if CYGHWR_HAL_ARM_CMA230_DIAG_BAUD==19200 99 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
85 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0x00 100 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
86 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB 0x0C 101 #define CYG_DEV_SERIAL_BAUD_LSB 0x0C
87 #endif 102 #endif
88 #if CYGHWR_HAL_ARM_CMA230_DIAG_BAUD==38400 103 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
89 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0x00 104 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
90 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB 0x06 105 #define CYG_DEV_SERIAL_BAUD_LSB 0x06
91 #endif 106 #endif
92 #if CYGHWR_HAL_ARM_CMA230_DIAG_BAUD==115200 107 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
93 #define CYG_DEVICE_SERIAL_RS232_BAUD_MSB 0x00 108 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
94 #define CYG_DEVICE_SERIAL_RS232_BAUD_LSB 0x02 109 #define CYG_DEV_SERIAL_BAUD_LSB 0x02
95 #endif 110 #endif
96 111
97 #ifndef CYG_DEVICE_SERIAL_RS232_BAUD_MSB 112 #ifndef CYG_DEV_SERIAL_BAUD_MSB
98 #error Missing/incorrect serial baud rate defined - CDL error? 113 #error Missing/incorrect serial baud rate defined - CDL error?
99 #endif 114 #endif
100 115
101 // Define the serial registers. 116 //-----------------------------------------------------------------------------
102 #define CYG_DEVICE_SERIAL_RS232_16550_RBR \ 117 // Define the serial registers. The Cogent board is equipped with a 16552
103 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) 118 // serial chip.
104 // receiver buffer register, read, dlab = 0 119 #define CYG_DEV_SERIAL_RBR 0x00 // receiver buffer register, read, dlab = 0
105 #define CYG_DEVICE_SERIAL_RS232_16550_THR \ 120 #define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
106 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) 121 #define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
107 // transmitter holding register, write, dlab = 0 122 #define CYG_DEV_SERIAL_IER 0x08 // interrupt enable register, read/write, dlab = 0
108 #define CYG_DEVICE_SERIAL_RS232_16550_DLL \ 123 #define CYG_DEV_SERIAL_DLM 0x08 // divisor latch (MS), read/write, dlab = 1
109 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x00) 124 #define CYG_DEV_SERIAL_IIR 0x10 // interrupt identification register, read, dlab = 0
110 // divisor latch (LS), read/write, dlab = 1 125 #define CYG_DEV_SERIAL_FCR 0x10 // fifo control register, write, dlab = 0
111 #define CYG_DEVICE_SERIAL_RS232_16550_IER \ 126 #define CYG_DEV_SERIAL_AFR 0x10 // alternate function register, read/write, dlab = 1
112 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08) 127 #define CYG_DEV_SERIAL_LCR 0x18 // line control register, read/write
113 // interrupt enable register, read/write, dlab = 0 128 #define CYG_DEV_SERIAL_MCR 0x20
114 #define CYG_DEVICE_SERIAL_RS232_16550_DLM \ 129 #define CYG_DEV_SERIAL_MCR_A 0x20
115 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x08) 130 #define CYG_DEV_SERIAL_MCR_B 0x20
116 // divisor latch (MS), read/write, dlab = 1 131 #define CYG_DEV_SERIAL_LSR 0x28 // line status register, read
117 #define CYG_DEVICE_SERIAL_RS232_16550_IIR \ 132 #define CYG_DEV_SERIAL_MSR 0x30 // modem status register, read
118 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x10) 133 #define CYG_DEV_SERIAL_SCR 0x38 // scratch pad register
119 // interrupt identification register, read, dlab = 0 134
120 #define CYG_DEVICE_SERIAL_RS232_16550_FCR \ 135 // The interrupt enable register bits.
121 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x10) 136 #define SIO_IER_ERDAI 0x01 // enable received data available irq
122 // fifo control register, write, dlab = 0 137 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
123 #define CYG_DEVICE_SERIAL_RS232_16550_LCR \ 138 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
124 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x18) 139 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
125 // line control register, read/write 140
126 #define CYG_DEVICE_SERIAL_RS232_16550_MCR \ 141 // The interrupt identification register bits.
127 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x20) 142 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
128 // modem control register, read/write 143 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
129 #define CYG_DEVICE_SERIAL_RS232_16550_LSR \ 144 #define ISR_Tx 0x02
130 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x28) 145 #define ISR_Rx 0x04
131 // line status register, read
132 #define CYG_DEVICE_SERIAL_RS232_16550_MSR \
133 ((volatile cyg_uint8 *) CYG_DEVICE_SERIAL_RS232_16550_BASE + 0x30)
134 // modem status register, read
135 146
136 // The line status register bits. 147 // The line status register bits.
137 #define SIO_LSR_DR 0x01 // data ready 148 #define SIO_LSR_DR 0x01 // data ready
138 #define SIO_LSR_OE 0x02 // overrun error 149 #define SIO_LSR_OE 0x02 // overrun error
139 #define SIO_LSR_PE 0x04 // parity error 150 #define SIO_LSR_PE 0x04 // parity error
161 #define SIO_LCR_EPS 0x10 // even parity select 172 #define SIO_LCR_EPS 0x10 // even parity select
162 #define SIO_LCR_SP 0x20 // stick parity 173 #define SIO_LCR_SP 0x20 // stick parity
163 #define SIO_LCR_SB 0x40 // set break 174 #define SIO_LCR_SB 0x40 // set break
164 #define SIO_LCR_DLAB 0x80 // divisor latch access bit 175 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
165 176
177 // The FIFO control register
178 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
179 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
180 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
181
182
183 //-----------------------------------------------------------------------------
184 typedef struct {
185 cyg_uint8* base;
186 cyg_int32 msec_timeout;
187 int isr_vector;
188 } channel_data_t;
189
190 //-----------------------------------------------------------------------------
191 static void
192 init_serial_channel(const channel_data_t* __ch_data)
193 {
194 cyg_uint8* base = __ch_data->base;
195 cyg_uint8 lcr;
196
197 // 8-1-no parity.
198 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR,
199 SIO_LCR_WLS0 | SIO_LCR_WLS1);
200
201 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
202 lcr |= SIO_LCR_DLAB;
203 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
204 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
205 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
206 lcr &= ~SIO_LCR_DLAB;
207 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
208 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
209 }
210
211 static cyg_bool
212 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
213 {
214 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
215 cyg_uint8 lsr;
216
217 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
218 if ((lsr & SIO_LSR_DR) == 0)
219 return false;
220
221 HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch);
222
223 return true;
224 }
225
226
227 cyg_uint8
228 cyg_hal_plf_serial_getc(void* __ch_data)
229 {
230 cyg_uint8 ch;
231 CYGARC_HAL_SAVE_GP();
232
233 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
234
235 CYGARC_HAL_RESTORE_GP();
236 return ch;
237 }
238
239 void
240 cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
241 {
242 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
243 cyg_uint8 lsr;
244 CYGARC_HAL_SAVE_GP();
245
246 do {
247 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
248 } while ((lsr & SIO_LSR_THRE) == 0);
249
250 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_THR, c);
251
252 // Hang around until the character has been safely sent.
253 do {
254 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
255 } while ((lsr & SIO_LSR_THRE) == 0);
256
257 CYGARC_HAL_RESTORE_GP();
258 }
259
260 #if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
261 || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)
262
263 static const channel_data_t channels[2] = {
264 { (cyg_uint8*)CMA101_DUARTA, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_A},
265 { (cyg_uint8*)CMA101_DUARTB, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_B}
266 };
267
268 static void
269 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
270 cyg_uint32 __len)
271 {
272 CYGARC_HAL_SAVE_GP();
273
274 while(__len-- > 0)
275 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
276
277 CYGARC_HAL_RESTORE_GP();
278 }
279
280 static void
281 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
282 {
283 CYGARC_HAL_SAVE_GP();
284
285 while(__len-- > 0)
286 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
287
288 CYGARC_HAL_RESTORE_GP();
289 }
290
291 cyg_bool
292 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
293 {
294 int delay_count;
295 channel_data_t* chan = (channel_data_t*)__ch_data;
296 cyg_bool res;
297 CYGARC_HAL_SAVE_GP();
298
299 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
300 for(;;) {
301 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
302 if (res || 0 == delay_count--)
303 break;
304
305 CYGACC_CALL_IF_DELAY_US(100);
306 }
307
308 CYGARC_HAL_RESTORE_GP();
309 return res;
310 }
311
312 static int
313 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
314 {
315 static int irq_state = 0;
316 channel_data_t* chan = (channel_data_t*)__ch_data;
317 cyg_uint8 ier;
318 int ret = 0;
319 CYGARC_HAL_SAVE_GP();
320
321 switch (__func) {
322 case __COMMCTL_IRQ_ENABLE:
323 HAL_INTERRUPT_UNMASK(chan->isr_vector);
324 HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
325 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
326 ier |= SIO_IER_ERDAI;
327 HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
328 irq_state = 1;
329 break;
330 case __COMMCTL_IRQ_DISABLE:
331 ret = irq_state;
332 irq_state = 0;
333 HAL_INTERRUPT_MASK(chan->isr_vector);
334 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
335 ier &= ~SIO_IER_ERDAI;
336 HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
337 break;
338 case __COMMCTL_DBG_ISR_VECTOR:
339 ret = chan->isr_vector;
340 break;
341 case __COMMCTL_SET_TIMEOUT:
342 {
343 va_list ap;
344
345 va_start(ap, __func);
346
347 ret = chan->msec_timeout;
348 chan->msec_timeout = va_arg(ap, cyg_uint32);
349
350 va_end(ap);
351 }
352 default:
353 break;
354 }
355 CYGARC_HAL_RESTORE_GP();
356 return ret;
357 }
358
359 static int
360 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
361 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
362 {
363 channel_data_t* chan = (channel_data_t*)__ch_data;
364 cyg_uint8 _iir;
365 int res = 0;
366 CYGARC_HAL_SAVE_GP();
367
368 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IIR, _iir);
369 _iir &= SIO_IIR_ID_MASK;
370
371 *__ctrlc = 0;
372 if ( ISR_Rx == _iir ) {
373 cyg_uint8 c, lsr;
374 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_LSR, lsr);
375 if (lsr & SIO_LSR_DR) {
376
377 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_RBR, c);
378
379 if( cyg_hal_is_break( &c , 1 ) )
380 *__ctrlc = 1;
381 }
382
383 // Acknowledge the interrupt
384 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
385 res = CYG_ISR_HANDLED;
386 }
387
388 CYGARC_HAL_RESTORE_GP();
389 return res;
390 }
391
392 static void
393 cyg_hal_plf_serial_init(void)
394 {
395 hal_virtual_comm_table_t* comm;
396 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
397
398 // Disable interrupts.
399 HAL_INTERRUPT_MASK(channels[0].isr_vector);
400 HAL_INTERRUPT_MASK(channels[1].isr_vector);
401
402 // Init channels
403 init_serial_channel(&channels[0]);
404 init_serial_channel(&channels[1]);
405
406 // Setup procs in the vector table
407
408 // Set channel 0
409 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
410 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
411 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
412 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
413 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
414 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
415 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
416 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
417 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
418 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
419
420 // Set channel 1
421 CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
422 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
423 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
424 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
425 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
426 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
427 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
428 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
429 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
430 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
431
432 // Restore original console
433 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
434 }
435
436 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES
437
438
439 //=============================================================================
440 // Compatibility with older stubs
441 //=============================================================================
442
443 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
444
445
446 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
447 #include <cyg/hal/drv_api.h>
448 #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
449 #endif
450
451 // Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
452 // totally stand-alone) system.
453
454 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL)
455 #define HAL_DIAG_USES_HARDWARE
456 #endif
457
458 /*---------------------------------------------------------------------------*/
459 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL==0
460 // This is the base address of the A-channel
461 #define CYG_DEV_SERIAL_BASE CMA101_DUARTA
462 #define CYG_DEV_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIAL_A
463 #else
464 // This is the base address of the B-channel
465 #define CYG_DEV_SERIAL_BASE CMA101_DUARTB
466 #define CYG_DEV_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIAL_B
467 #endif
468
469 static channel_data_t ser_channel = { (cyg_uint8*)CYG_DEV_SERIAL_BASE, 0, 0};
166 470
167 #ifdef HAL_DIAG_USES_HARDWARE 471 #ifdef HAL_DIAG_USES_HARDWARE
168 472
169 void hal_diag_init(void) 473 void hal_diag_init(void)
170 { 474 {
171 static int init = 0; 475 static int init = 0;
172 char *msg = "\n\rARM eCos\n\r"; 476 char *msg = "\n\rARM eCos\n\r";
173 cyg_uint8 lcr; 477 cyg_uint8 lcr;
174 478
175 if (init++) return; 479 if (init++) return;
176 // 8-1-no parity. 480
177 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, 481 init_serial_channel(&ser_channel);
178 SIO_LCR_WLS0 | SIO_LCR_WLS1); 482
179
180 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
181 lcr |= SIO_LCR_DLAB;
182 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
183 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLL,
184 CYG_DEVICE_SERIAL_RS232_BAUD_LSB);
185 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_DLM,
186 CYG_DEVICE_SERIAL_RS232_BAUD_MSB);
187 lcr &= ~SIO_LCR_DLAB;
188 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LCR, lcr);
189 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_FCR, 0x07); // Enable & clear FIFO
190 while (*msg) hal_diag_write_char(*msg++); 483 while (*msg) hal_diag_write_char(*msg++);
191 } 484 }
192 485
193 #ifdef DEBUG_DIAG 486 #ifdef DEBUG_DIAG
194 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) 487 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
203 void hal_diag_write_char(char c) 496 void hal_diag_write_char(char c)
204 { 497 {
205 cyg_uint8 lsr; 498 cyg_uint8 lsr;
206 499
207 hal_diag_init(); 500 hal_diag_init();
208 do { 501
209 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr); 502 cyg_hal_plf_serial_putc(&ser_channel, c)
210 } while ((lsr & SIO_LSR_THRE) == 0); 503
211
212 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_THR, c);
213 #ifdef DEBUG_DIAG 504 #ifdef DEBUG_DIAG
214 diag_buffer[diag_bp++] = c; 505 diag_buffer[diag_bp++] = c;
215 if (diag_bp == DIAG_BUFSIZE) { 506 if (diag_bp == DIAG_BUFSIZE) {
216 while (1) ; 507 while (1) ;
217 diag_bp = 0; 508 diag_bp = 0;
219 #endif 510 #endif
220 } 511 }
221 512
222 void hal_diag_read_char(char *c) 513 void hal_diag_read_char(char *c)
223 { 514 {
224 cyg_uint8 lsr; 515 *c = cyg_hal_plf_serial_getc(&ser_channel);
225
226 do {
227 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
228 } while ((lsr & SIO_LSR_DR) == 0);
229
230 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_RBR, *c);
231 } 516 }
232 517
233 #else // HAL_DIAG relies on GDB 518 #else // HAL_DIAG relies on GDB
234 519
235 // Initialize diag port - assume GDB channel is already set up 520 // Initialize diag port - assume GDB channel is already set up
236 void hal_diag_init(void) 521 void hal_diag_init(void)
237 { 522 {
523 if (0) init_serial_channel(&ser_channel); // avoid warning
238 } 524 }
239 525
240 // Actually send character down the wire 526 // Actually send character down the wire
241 static void 527 static void
242 hal_diag_write_char_serial(char c) 528 hal_diag_write_char_serial(char c)
243 { 529 {
244 cyg_uint8 lsr; 530 cyg_hal_plf_serial_putc(&ser_channel, c);
245
246 hal_diag_init();
247 do {
248 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
249 } while ((lsr & SIO_LSR_THRE) == 0);
250
251 HAL_WRITE_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_THR, c);
252 HAL_IO_BARRIER ();
253 } 531 }
254 532
255 static bool 533 static bool
256 hal_diag_read_serial(char *c) 534 hal_diag_read_serial(char *c)
257 { 535 {
258 long timeout = 1000000000; // A long time... 536 long timeout = 1000000000; // A long time...
259 cyg_uint8 lsr; 537 while (!cyg_hal_plf_serial_getc_nonblock(&ser_channel, c))
260 538 if (0 == --timeout) return false;
261 do { 539
262 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_LSR, lsr);
263 if (--timeout == 0) return false;
264 } while ((lsr & SIO_LSR_DR) == 0);
265 HAL_IO_BARRIER (); // Prevent RBR preload.
266
267 HAL_READ_UINT8 (CYG_DEVICE_SERIAL_RS232_16550_RBR, *c);
268 HAL_IO_BARRIER ();
269 return true; 540 return true;
270 } 541 }
271 542
272 void 543 void
273 hal_diag_read_char(char *c) 544 hal_diag_read_char(char *c)
333 604
334 if( c1 == '+' ) 605 if( c1 == '+' )
335 break; // a good acknowledge 606 break; // a good acknowledge
336 607
337 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT 608 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
338 cyg_drv_interrupt_acknowledge(CYG_DEVICE_SERIAL_INT); 609 cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
339 if( c1 == 3 ) { 610 if( c1 == 3 ) {
340 // Ctrl-C: breakpoint. 611 // Ctrl-C: breakpoint.
341 cyg_hal_gdb_interrupt (__builtin_return_address(0)); 612 cyg_hal_gdb_interrupt (__builtin_return_address(0));
342 break; 613 break;
343 } 614 }
356 627
357 } 628 }
358 } 629 }
359 #endif 630 #endif
360 631
632 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
633
361 /*---------------------------------------------------------------------------*/ 634 /*---------------------------------------------------------------------------*/
362 /* End of hal_diag.c */ 635 /* End of hal_diag.c */