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annotate packages/hal/arm/cma230/current/src/hal_diag.c @ 110:84e4bde58b26 ecos-sw-2000-07-14

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Merge from eCos master repository on 2000-07-14-22:00:02-BST
author jlarmour
date Mon, 17 Jul 2000 14:42:27 +0000
parents bf00f99aec69
children 25e238959bae
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1 /*=============================================================================
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2 //
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3 // hal_diag.c
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4 //
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5 // HAL diagnostic output code
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6 //
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7 //=============================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //=============================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): nickg, gthomas
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35 // Contributors: nickg, gthomas
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36 // Date: 1998-03-02
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37 // Purpose: HAL diagnostic output
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38 // Description: Implementations of HAL diagnostic output support.
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //===========================================================================*/
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43
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44 #include <pkgconf/hal.h>
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45 #include <pkgconf/hal_arm_cma230.h> // board specifics
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47 #include <cyg/infra/cyg_type.h> // base types
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48 #include <cyg/infra/cyg_trac.h> // tracing macros
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49 #include <cyg/infra/cyg_ass.h> // assertion macros
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50
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51 #include <cyg/hal/hal_arch.h> // basic machine info
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52 #include <cyg/hal/hal_intr.h> // interrupt macros
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53 #include <cyg/hal/hal_io.h> // IO macros
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54 #include <cyg/hal/hal_diag.h>
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55 #include <cyg/hal/hal_cma230.h> // Hardware definitions
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56 #include <cyg/hal/hal_if.h> // Calling-if API
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57 #include <cyg/hal/drv_api.h> // driver API
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58 #include <cyg/hal/hal_misc.h> // Helper functions
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59
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60 #if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
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61 || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)
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62
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63 static void cyg_hal_plf_serial_init(void);
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64
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65 // FIXME: Copy LCD driver from powerpc/cogent
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66 //static void cyg_hal_plf_lcd_init(void);
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67
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68 void
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69 cyg_hal_plf_comms_init(void)
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70 {
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71 static int initialized = 0;
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72
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73 if (initialized)
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74 return;
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75
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76 initialized = 1;
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77
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78 cyg_hal_plf_serial_init();
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79 // cyg_hal_plf_lcd_init();
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80 }
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81 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES
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82
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83 //=============================================================================
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84 // Serial driver
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85 //=============================================================================
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86
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87 //-----------------------------------------------------------------------------
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88 // There are two serial ports.
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89 #define CYG_DEV_SERIAL_BASE_A 0xe900047 // port A
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90 #define CYG_DEV_SERIAL_BASE_B 0xe900007 // port B
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91
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92 //-----------------------------------------------------------------------------
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93 // Default baud rate is 38400
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94 // Based on 3.6864 MHz xtal
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95 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
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96 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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97 #define CYG_DEV_SERIAL_BAUD_LSB 0x18
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98 #endif
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99 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
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100 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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101 #define CYG_DEV_SERIAL_BAUD_LSB 0x0C
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102 #endif
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103 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
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104 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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105 #define CYG_DEV_SERIAL_BAUD_LSB 0x06
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106 #endif
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107 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
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108 #define CYG_DEV_SERIAL_BAUD_MSB 0x00
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109 #define CYG_DEV_SERIAL_BAUD_LSB 0x02
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110 #endif
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111
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112 #ifndef CYG_DEV_SERIAL_BAUD_MSB
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113 #error Missing/incorrect serial baud rate defined - CDL error?
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114 #endif
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115
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116 //-----------------------------------------------------------------------------
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117 // Define the serial registers. The Cogent board is equipped with a 16552
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118 // serial chip.
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119 #define CYG_DEV_SERIAL_RBR 0x00 // receiver buffer register, read, dlab = 0
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120 #define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0
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121 #define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
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122 #define CYG_DEV_SERIAL_IER 0x08 // interrupt enable register, read/write, dlab = 0
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123 #define CYG_DEV_SERIAL_DLM 0x08 // divisor latch (MS), read/write, dlab = 1
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124 #define CYG_DEV_SERIAL_IIR 0x10 // interrupt identification register, read, dlab = 0
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125 #define CYG_DEV_SERIAL_FCR 0x10 // fifo control register, write, dlab = 0
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126 #define CYG_DEV_SERIAL_AFR 0x10 // alternate function register, read/write, dlab = 1
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127 #define CYG_DEV_SERIAL_LCR 0x18 // line control register, read/write
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128 #define CYG_DEV_SERIAL_MCR 0x20
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129 #define CYG_DEV_SERIAL_MCR_A 0x20
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130 #define CYG_DEV_SERIAL_MCR_B 0x20
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131 #define CYG_DEV_SERIAL_LSR 0x28 // line status register, read
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132 #define CYG_DEV_SERIAL_MSR 0x30 // modem status register, read
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133 #define CYG_DEV_SERIAL_SCR 0x38 // scratch pad register
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134
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135 // The interrupt enable register bits.
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136 #define SIO_IER_ERDAI 0x01 // enable received data available irq
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137 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
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138 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
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139 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
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140
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141 // The interrupt identification register bits.
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142 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
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143 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
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144 #define ISR_Tx 0x02
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145 #define ISR_Rx 0x04
46
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146
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147 // The line status register bits.
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148 #define SIO_LSR_DR 0x01 // data ready
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149 #define SIO_LSR_OE 0x02 // overrun error
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150 #define SIO_LSR_PE 0x04 // parity error
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151 #define SIO_LSR_FE 0x08 // framing error
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152 #define SIO_LSR_BI 0x10 // break interrupt
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153 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
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154 #define SIO_LSR_TEMT 0x40 // transmitter register empty
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155 #define SIO_LSR_ERR 0x80 // any error condition
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156
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157 // The modem status register bits.
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158 #define SIO_MSR_DCTS 0x01 // delta clear to send
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159 #define SIO_MSR_DDSR 0x02 // delta data set ready
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160 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
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161 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
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162 #define SIO_MSR_CTS 0x10 // clear to send
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163 #define SIO_MSR_DSR 0x20 // data set ready
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164 #define SIO_MSR_RI 0x40 // ring indicator
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165 #define SIO_MSR_DCD 0x80 // data carrier detect
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166
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167 // The line control register bits.
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168 #define SIO_LCR_WLS0 0x01 // word length select bit 0
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169 #define SIO_LCR_WLS1 0x02 // word length select bit 1
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170 #define SIO_LCR_STB 0x04 // number of stop bits
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171 #define SIO_LCR_PEN 0x08 // parity enable
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172 #define SIO_LCR_EPS 0x10 // even parity select
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173 #define SIO_LCR_SP 0x20 // stick parity
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174 #define SIO_LCR_SB 0x40 // set break
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175 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
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176
110
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177 // The FIFO control register
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178 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
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179 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
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180 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
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181
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182
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183 //-----------------------------------------------------------------------------
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184 typedef struct {
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185 cyg_uint8* base;
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186 cyg_int32 msec_timeout;
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187 int isr_vector;
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188 } channel_data_t;
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189
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190 //-----------------------------------------------------------------------------
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191 static void
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192 init_serial_channel(const channel_data_t* __ch_data)
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193 {
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194 cyg_uint8* base = __ch_data->base;
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195 cyg_uint8 lcr;
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196
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197 // 8-1-no parity.
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198 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR,
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199 SIO_LCR_WLS0 | SIO_LCR_WLS1);
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200
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201 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
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202 lcr |= SIO_LCR_DLAB;
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203 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
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204 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
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205 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
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206 lcr &= ~SIO_LCR_DLAB;
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207 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);
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208 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, 0x07); // Enable & clear FIFO
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209 }
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210
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211 static cyg_bool
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212 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
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213 {
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214 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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215 cyg_uint8 lsr;
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216
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217 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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218 if ((lsr & SIO_LSR_DR) == 0)
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219 return false;
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220
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221 HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch);
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222
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223 return true;
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224 }
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225
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226
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227 cyg_uint8
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228 cyg_hal_plf_serial_getc(void* __ch_data)
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229 {
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230 cyg_uint8 ch;
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231 CYGARC_HAL_SAVE_GP();
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232
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233 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
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234
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235 CYGARC_HAL_RESTORE_GP();
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236 return ch;
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237 }
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238
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239 void
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240 cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
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241 {
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242 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
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243 cyg_uint8 lsr;
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244 CYGARC_HAL_SAVE_GP();
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245
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246 do {
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247 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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248 } while ((lsr & SIO_LSR_THRE) == 0);
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249
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250 HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_THR, c);
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251
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252 // Hang around until the character has been safely sent.
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253 do {
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254 HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
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255 } while ((lsr & SIO_LSR_THRE) == 0);
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256
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257 CYGARC_HAL_RESTORE_GP();
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258 }
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259
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260 #if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
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261 || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)
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262
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263 static const channel_data_t channels[2] = {
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264 { (cyg_uint8*)CMA101_DUARTA, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_A},
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265 { (cyg_uint8*)CMA101_DUARTB, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_B}
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266 };
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267
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268 static void
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269 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
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270 cyg_uint32 __len)
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271 {
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272 CYGARC_HAL_SAVE_GP();
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273
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274 while(__len-- > 0)
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275 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
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276
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277 CYGARC_HAL_RESTORE_GP();
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278 }
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279
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280 static void
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281 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
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282 {
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283 CYGARC_HAL_SAVE_GP();
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284
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285 while(__len-- > 0)
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286 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
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287
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288 CYGARC_HAL_RESTORE_GP();
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289 }
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290
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291 cyg_bool
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292 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
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293 {
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294 int delay_count;
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295 channel_data_t* chan = (channel_data_t*)__ch_data;
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296 cyg_bool res;
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297 CYGARC_HAL_SAVE_GP();
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298
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299 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
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300 for(;;) {
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301 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
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302 if (res || 0 == delay_count--)
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303 break;
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304
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305 CYGACC_CALL_IF_DELAY_US(100);
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306 }
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307
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308 CYGARC_HAL_RESTORE_GP();
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309 return res;
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310 }
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311
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312 static int
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313 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
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314 {
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315 static int irq_state = 0;
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316 channel_data_t* chan = (channel_data_t*)__ch_data;
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317 cyg_uint8 ier;
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318 int ret = 0;
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319 CYGARC_HAL_SAVE_GP();
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320
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321 switch (__func) {
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322 case __COMMCTL_IRQ_ENABLE:
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323 HAL_INTERRUPT_UNMASK(chan->isr_vector);
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324 HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
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325 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
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326 ier |= SIO_IER_ERDAI;
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327 HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
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328 irq_state = 1;
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329 break;
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330 case __COMMCTL_IRQ_DISABLE:
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331 ret = irq_state;
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332 irq_state = 0;
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333 HAL_INTERRUPT_MASK(chan->isr_vector);
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334 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
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335 ier &= ~SIO_IER_ERDAI;
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336 HAL_WRITE_UINT8(chan->base+CYG_DEV_SERIAL_IER, ier);
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337 break;
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338 case __COMMCTL_DBG_ISR_VECTOR:
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339 ret = chan->isr_vector;
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340 break;
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341 case __COMMCTL_SET_TIMEOUT:
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342 {
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343 va_list ap;
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344
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345 va_start(ap, __func);
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346
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347 ret = chan->msec_timeout;
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348 chan->msec_timeout = va_arg(ap, cyg_uint32);
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349
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350 va_end(ap);
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351 }
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352 default:
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353 break;
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354 }
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355 CYGARC_HAL_RESTORE_GP();
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356 return ret;
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357 }
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358
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359 static int
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360 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
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361 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
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362 {
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363 channel_data_t* chan = (channel_data_t*)__ch_data;
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364 cyg_uint8 _iir;
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365 int res = 0;
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366 CYGARC_HAL_SAVE_GP();
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367
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368 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_IIR, _iir);
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369 _iir &= SIO_IIR_ID_MASK;
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370
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371 *__ctrlc = 0;
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372 if ( ISR_Rx == _iir ) {
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373 cyg_uint8 c, lsr;
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374 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_LSR, lsr);
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375 if (lsr & SIO_LSR_DR) {
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376
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377 HAL_READ_UINT8(chan->base+CYG_DEV_SERIAL_RBR, c);
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378
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379 if( cyg_hal_is_break( &c , 1 ) )
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380 *__ctrlc = 1;
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381 }
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382
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383 // Acknowledge the interrupt
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384 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
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385 res = CYG_ISR_HANDLED;
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386 }
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387
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388 CYGARC_HAL_RESTORE_GP();
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389 return res;
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390 }
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391
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392 static void
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393 cyg_hal_plf_serial_init(void)
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394 {
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395 hal_virtual_comm_table_t* comm;
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396 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
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397
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398 // Disable interrupts.
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399 HAL_INTERRUPT_MASK(channels[0].isr_vector);
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400 HAL_INTERRUPT_MASK(channels[1].isr_vector);
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401
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402 // Init channels
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403 init_serial_channel(&channels[0]);
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404 init_serial_channel(&channels[1]);
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405
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406 // Setup procs in the vector table
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407
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408 // Set channel 0
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409 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
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410 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
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411 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
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412 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
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413 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
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414 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
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415 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
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416 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
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417 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
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418 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
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419
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420 // Set channel 1
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421 CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
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422 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
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423 CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
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424 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
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425 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
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426 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
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427 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
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428 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
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429 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
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430 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
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431
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432 // Restore original console
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433 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
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434 }
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435
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436 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES
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437
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438
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439 //=============================================================================
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440 // Compatibility with older stubs
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441 //=============================================================================
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442
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443 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
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444
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445
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446 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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447 #include <cyg/hal/drv_api.h>
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448 #include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
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449 #endif
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450
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451 // Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
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452 // totally stand-alone) system.
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453
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454 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL)
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455 #define HAL_DIAG_USES_HARDWARE
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456 #endif
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457
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458 /*---------------------------------------------------------------------------*/
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459 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL==0
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460 // This is the base address of the A-channel
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461 #define CYG_DEV_SERIAL_BASE CMA101_DUARTA
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462 #define CYG_DEV_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIAL_A
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463 #else
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464 // This is the base address of the B-channel
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465 #define CYG_DEV_SERIAL_BASE CMA101_DUARTB
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466 #define CYG_DEV_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIAL_B
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467 #endif
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468
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469 static channel_data_t ser_channel = { (cyg_uint8*)CYG_DEV_SERIAL_BASE, 0, 0};
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470
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471 #ifdef HAL_DIAG_USES_HARDWARE
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472
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473 void hal_diag_init(void)
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474 {
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475 static int init = 0;
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476 char *msg = "\n\rARM eCos\n\r";
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477 cyg_uint8 lcr;
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478
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479 if (init++) return;
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480
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481 init_serial_channel(&ser_channel);
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482
46
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483 while (*msg) hal_diag_write_char(*msg++);
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484 }
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485
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486 #ifdef DEBUG_DIAG
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487 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
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488 #define DIAG_BUFSIZE 32
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489 #else
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490 #define DIAG_BUFSIZE 2048
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491 #endif
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492 static char diag_buffer[DIAG_BUFSIZE];
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493 static int diag_bp = 0;
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494 #endif
46
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495
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496 void hal_diag_write_char(char c)
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497 {
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498 cyg_uint8 lsr;
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499
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500 hal_diag_init();
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501
110
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502 cyg_hal_plf_serial_putc(&ser_channel, c)
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503
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504 #ifdef DEBUG_DIAG
46
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505 diag_buffer[diag_bp++] = c;
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506 if (diag_bp == DIAG_BUFSIZE) {
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507 while (1) ;
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508 diag_bp = 0;
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509 }
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510 #endif
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511 }
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512
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513 void hal_diag_read_char(char *c)
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514 {
110
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515 *c = cyg_hal_plf_serial_getc(&ser_channel);
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516 }
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517
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518 #else // HAL_DIAG relies on GDB
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519
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520 // Initialize diag port - assume GDB channel is already set up
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521 void hal_diag_init(void)
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522 {
110
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523 if (0) init_serial_channel(&ser_channel); // avoid warning
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524 }
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525
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526 // Actually send character down the wire
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527 static void
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528 hal_diag_write_char_serial(char c)
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529 {
110
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530 cyg_hal_plf_serial_putc(&ser_channel, c);
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531 }
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532
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533 static bool
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534 hal_diag_read_serial(char *c)
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535 {
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536 long timeout = 1000000000; // A long time...
110
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537 while (!cyg_hal_plf_serial_getc_nonblock(&ser_channel, c))
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538 if (0 == --timeout) return false;
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539
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540 return true;
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541 }
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542
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543 void
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544 hal_diag_read_char(char *c)
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545 {
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546 while (!hal_diag_read_serial(c)) ;
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547 }
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548
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549 void
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550 hal_diag_write_char(char c)
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551 {
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552 static char line[100];
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553 static int pos = 0;
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554
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555 // No need to send CRs
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556 if( c == '\r' ) return;
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557
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558 line[pos++] = c;
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559
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560 if( c == '\n' || pos == sizeof(line) )
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561 {
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562 CYG_INTERRUPT_STATE old;
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563
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564 // Disable interrupts. This prevents GDB trying to interrupt us
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565 // while we are in the middle of sending a packet. The serial
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566 // receive interrupt will be seen when we re-enable interrupts
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567 // later.
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568
50
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569 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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570 CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
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571 #else
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572 HAL_DISABLE_INTERRUPTS(old);
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573 #endif
46
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574
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575 while(1)
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576 {
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577 static char hex[] = "0123456789ABCDEF";
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578 cyg_uint8 csum = 0;
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579 int i;
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580 char c1;
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581
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582 hal_diag_write_char_serial('$');
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583 hal_diag_write_char_serial('O');
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584 csum += 'O';
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585 for( i = 0; i < pos; i++ )
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586 {
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587 char ch = line[i];
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588 char h = hex[(ch>>4)&0xF];
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589 char l = hex[ch&0xF];
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590 hal_diag_write_char_serial(h);
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591 hal_diag_write_char_serial(l);
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592 csum += h;
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593 csum += l;
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594 }
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595 hal_diag_write_char_serial('#');
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596 hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
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597 hal_diag_write_char_serial(hex[csum&0xF]);
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598
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599 // Wait for the ACK character '+' from GDB here and handle
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600 // receiving a ^C instead. This is the reason for this clause
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601 // being a loop.
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602 if (!hal_diag_read_serial(&c1))
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603 continue; // No response - try sending packet again
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604
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605 if( c1 == '+' )
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606 break; // a good acknowledge
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607
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608 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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609 cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
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610 if( c1 == 3 ) {
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611 // Ctrl-C: breakpoint.
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612 cyg_hal_gdb_interrupt (__builtin_return_address(0));
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613 break;
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614 }
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615 #endif
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616 // otherwise, loop round again
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617 }
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618
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619 pos = 0;
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620
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621 // And re-enable interrupts
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622 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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623 CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
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624 #else
46
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625 HAL_RESTORE_INTERRUPTS(old);
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626 #endif
46
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627
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628 }
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629 }
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630 #endif
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631
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632 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
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633
46
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634 /*---------------------------------------------------------------------------*/
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635 /* End of hal_diag.c */